enabling breakthroughs in...
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Mike MayberryDirector of Components Research
VP, Technology and Manufacturing Group
Intel Corporation
June 2011
Enabling BreakthroughsIn Technology
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Enabling a Steady Technology Cadence
TECHNOLOGY GENERATION
MANUFACTURING DEVELOPMENT RESEARCH
65nm
200545nm
200732nm
200922nm
201114nm
201310nm
20157nm
2017Beyond
2020
What to do nowto enable
these future generations ?D
efi
ne
d
To b
e d
efi
ne
d
Not to scale
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But first some old technology …
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Exploration – late 90’s• Talk of 0.1um as the end
due to leakage power• 248nm lithography limited
device exploration
Then enabled• Creation of sub-resolution features• Study of dense patterns (later)
1997 Intel Invention Spacer based pattern
Intel: 10nm planar transistor
Exploration was not limited by lithography
2002
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Exploration – late 90’s• Talk of 0.1um as the end
due to leakage power• 248nm lithography limited
device exploration
Exploration today193 immersion lithography
1997 Intel Invention Spacer based pattern
Exploration (still) not limited by lithography
Pitch Quartering with
193i, 16nm features
+ Spacer based pattern twice
Scalable toSub 10nm features
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Evaluation – early 00’s• 15 yrs discussion of possible
non-planar device concepts• No systematic scaling studies
Then enabled• Assessment of scaling challenges
and critical parameters• Focus for optimization
Planar Thin body SOI Trigate on SOIFinFET on SOI
Build all variations and compare
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Evaluation – early 00’s• 15 yrs discussion of possible
non-planar device concepts• No systematic scaling studies
Evaluation today• Assessment of scaling challenges
and critical parameters for III-V
Thin body SOI
Trigate on SOIFinFET on SOI
InP
InAlAs
In0.7Ga0.3As QW
InAlAs Barrier
III-V Barrier
Ga
teHiK HiK S/D
n+cap
S/D
n+cap
InP
InAlAs
In0.7Ga0.3As QW
InAlAs Barrier
III-V Barrier
Ga
teHiK HiK S/D
n+cap
S/D
n+cap
S/D
n+cap
S/D
n+cap
Quantum Well
equivalent to
Thin body SOI
3D devices
InGaAs
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Intel dataIntel data
IEDM 2006
Integration – mid 00’s• Move to bulk silicon (cost)• Catch up to planar for
high k/metal gate + strain• Create working CMOS
Then enabled• Quality decision to adopt• Development roadmap• Lots more work !!!!
Tri-gateSRAM cells
demonstrated
Tri-gate RMG process flowdeveloped
High-K
2006
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Integration – mid 00’s• Move to bulk silicon (cost)• Catch up to planar for
high k/metal gate + strain• Create working CMOS
Integration Today• III-V grown on bulk silicon• High k integration done• Strain engineering – not needed• 3D devices – partially done• N and P on same wafer – NOT DONE
Tri-gateSRAM cells
demonstrated
Tri-gate RMG process flowdeveloped
High-K
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Optimizing Choices for Transistors on Multiple Fronts
InAlAs Barriers
QW
SEM Micrograph
InP
Energy Band DiagramEnergy Band DiagramEnergy Band Diagram
Si
d
Gate
SourceDrainn-Ge
Gate
SourceDrainn-Ge
Strain GeIII-V
Increasing MOBILITY
(better ON)
Increasing COUPLING
(better OFF)
GrapheneCNT
PlanarWith High K
Fins Wires/DotsUTB SOI(or QW)
THEN
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Optimizing Choices for Transistors on Multiple Fronts
InAlAs Barriers
QW
SEM Micrograph
InP
Energy Band DiagramEnergy Band DiagramEnergy Band Diagram
Si
d
Gate
SourceDrainn-Ge
Gate
SourceDrainn-Ge
Strain GeIII-V
Increasing MOBILITY
(better ON)
Increasing COUPLING
(better OFF)
GrapheneCNT
PlanarWith High K
FinsUTB SOI(or QW)
NOW
Wires/Dots
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Interconnects Need to Scale
Needed Focus
Thin conformal plateable barrier
… or self forming barrier
Tall vias might use non-Cu
Non-SiO2 dielectrics
Exotic long interconnects: CNT (10’s um), optical (>mm)
3D stacking
5nm conformal Cu
On-chip opticalinterconnect
~15nm Cu nanowire
CNT
14nmfilled trench
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Broad Range of Options
M. Luisier (Purdue)EDL 2009
Liu IEDM 2010
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We Expect Technology Innovation to Continue
14nm
2013*10nm
2015*7nm
2017*Beyond
2019+
MANUFACTURING DEVELOPMENT
45nm
200732nm
200922nm
2011*
RESEARCH
65nm
2005
*projected
III-V
MaterialsSynthesisHigh-K
Germanium
Dense Memory
NanowiresInterconnects
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Conclusions
Moore’s Law is not a law of nature, it is an expectation of continued innovation
We expect to continue through focused research, rapid development, investment in production
Scaling research is increasingly about materials research, solving problems brings opportunities
New product opportunities will arise from continued advances in integration, connectivity
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Discussion