Lecture Details

Tentative schedule (Saturday, May 4th

, 2019)

8:00 - 8:30 Registration

8:30 –8:45 Inauguration

8:45- 9:00 IEEE EDS overview and membership benefits

9:00 -10:30 Gate Stack Engineering for Ge MOS and FinFETs

10:30-11:00 Tea break

11:00-12:30 Compact Modeling of Emerging Devices: Academic versus

Industrial Approaches

12:30-14:00 Lunch break

14:00-15:30 Fundamentals of Negative Capacitance Transistors

15:30-15:45 Tea Break

15:45-17:15 Reliability Challenges of Nano-Interconnects

17:15-17:30 Valedictory & Certificate Distribution

Registration Details :

All interested may kindly pre-register (link given below ) and deposit the registra-

tion fee through online bank transfer (latest by 02/05/2019)

Registration fees : Rs 200/- only (IEEE members)

: Rs 300/- only (For others )

Payment Options:

Payments can be made by either of the one option given below:

1. Online Mode: Through Internet Banking.

2. Offline Mode: Cash deposit in the Bank.

Bank Details:

Account number - 32943696701

Account name - IEEE EDS SBC IITR

Br. Name - SBI IIT Roorkee, Branch, Branch code 001069

IFSC Code - SBIN0001069, MICR Code– 247002094

Note:

Scan copy of Online/Offline transaction receipt must be sent via email to

ieee.eds.sbc.iitr@gmail.com

For Registration page, please click on the link given below:

https://docs.google.com/forms/d/13RlT6upeXj_gu4RkMaYXkI81hVRckMTMBI8fPfHevkI

For further details kindly contact

Mr. Sandeep Chauhan, Research Scholar IIT Roorkee (9897013768)

IEEE EDS Mini Colloquium (MQ)

on Emerging Nanoscale Devices:

Compact Modeling and Reliability

IEEE Electron Devices Society (EDS) Student Chapter, IIT Roorkee is Organizing an IEEE

3rd Mini Colloquium on “Emerging Nanoscale Devices: Compact Modeling and Reliability ”.

IEEE Distinguished Lecturer talks in the MQ have been planned to deliberate Future Nanoscale

CMOS Technologies and Device Modeling. The challenges in the emerging nanoscale CMOS,

nanoelectronics, and nanotechnology and the possible solutions will be discussed. The researchers

working in these area will be able to enhance their knowledge and benefit from the interaction with

the renowned experts from Taiwan, Hong Kong, and India. The invited talks will focus on: Com-

pact Modeling of Emerging Nanoscale Devices, Negative Capacitance FET, Gate Stack Engi-

neering for Ge-MOS and FinFET and Reliability issues of Nanoscale Interconnects.

We cordially invite you all to attended the Mini - Colloquium & get benefited

Speakers:

Venue : LHC – 002, New Lecture Hall Complex, IIT Roorkee

Date: 4th May, 2019

Time Duration: 08:00 am - 05:30 pm

Who Should Attend: B.Tech/M.Tech/Ph.D Students, Faculty & Scientists

How to Apply: Interested candidates should register & deposit registration fees

Kindly Note:

Number of the seats are limited and they will be filled on first-come-first serve basis.

Dr. Sanjeev K. Manhas

(Faculty Advisor, IEEE-EDS Chapter, SBC, IIT Roorkee)

Mr. Sandeep Singh Chauhan (Treasurer)

Mr. Sourabh Jindal (Student Chair)

Sponsored by

4th May, 2019

Dr. K. Chang-Liao Topic: Gate Stack Engineering for Ge MOS and

FinFETs

Dr. Mansun Chan Topic: Compact Modeling of Emerging Devices:

Academic versus Industrial Approaches

Dr. Yogesh Chauhan Topic: Fundamentals of Negative Capacitance

Transistors

Dr. Tan Cher Ming Topic: Reliability Challenges of Nano-Interconnects

Dr. Yogesh Chauhan Associate Professor

Dept. of ECE

IIT Kanpur

Kanpur, India

Dr. K. Chang-Liao Professor

Dept. of Engg. & System

Science

National Tsing Hua

University, Taiwan

Dr. Tan Cher Ming Professor

Dept. of Electronic Engg.

Chang Gung University

Taoyuan City, Taiwan

Dr. Mansun Chan Chair Professor

Dept. of ECE

Hong Kong University

of Science & Tech.

Kowloon, Hong Kong

Compact Modeling of Emerging Devices: Academic versus Industrial Approaches

Mansun Chan

Dept. of ECE, Hong Kong University of Science & Technology,

Clear Water Bay, Kowloon, Hong Kong

E-mail: mchan@ust.hk

Abstract: With the recent concern to continue the scaling roadmap after ITRS has stopped its prediction, a lot of

activities have been devoted to computational study of emerging devices to extend the scaling process. In

particular, compact models have been serving as a bridge to evaluate the relative advantages of new devices in

circuits and systems. The development of compact model, however, has a strong bias towards the physical

correctness with little attentions devoted to interface the model to circuit simulators. New applications with that

require device with time dependent dynamic device behaviors such as neuromorphic computing or artificial

neural-network circuits require a new interaction between the compact model and circuit simulator. This

presentation will explain the compact model development process focusing on the model-simulator interface and

how an academic model can be adopted by the industry. The recent acceleration of technology development has

called for a more efficient model development platform. The NEEDS (Nano-Engineered Electronic Device

Simulation) and i-MOS (interactive Modeling and Online Simulation) projects have emerged as the collaborative

platforms for model developer. The new paradigm to incorporate modern software engineering methodology to

shorten model development cycle will be described.

Biography:

Prof. Mansun Chan received his BS in Electrical Engineering and Compute

Science with highest honors from the University of California at San Diego and

then completed his MS and PhD at the University of California at Berkeley. At

Berkeley, was one of the major contributors to the unified BSIM model for

SPICE, which has been accepted by most US companies and the Compact Model

Council (CMC) as the first industrial standard MOSFET model. Subsequently,

he joined the Electrical and Electronic Engineering Department at Hong Kong

University of Science and Technology. His research interests include emerging

nano-device technologies, 2-D device for flexible electronics, Artificial Neural

Network devices and applications, new-generation memory technology,

BioNEMS, device modeling and ultra-low power circuit techniques. Between July 2001 and December 2002, he

was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is

currently still consulting on the development of the next generation compact models.

Prof. Chan has been actively contributing to the professional community and hold many positions. He was a

Board of Governor, Chair of the Education Committee, the Region 10 subcommittee and the EDS Student

Fellowship Committee. He has also chaired many international conferences and acting as editors for a number

of technical journals. In addition, he has received many awards including the UC Regents Fellowship, Golden

Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship,

R&D 100 award (for the BSIM3v3 project), IEEE EDS Education Award, HKUST SENG Distinguished

Teaching Award, the Shenzhen Science and Technology Innovation awards etc. He is a Distinguished Lecturer

and a Fellow of IEEE.

Gate Stack Engineering for Ge MOS and FinFETs

Kuei-Shu Chang-Liao

Abstract—High performance Ge pMOSFETs are demonstrated by engineering interfacial layer. A Hf-rich buffer

layer (HBL), GeON interfacial layer (IL) formed with NH3 plasma, and microwave annealing (MWA) are

proposed to improve electrical characteristics of Ge MOSFET. A very high peak hole mobility of ~ 900 cm2/V-

s, extremely low JG of ~ 10-5 A/cm2, and EOT of~ 0.5 nm in Ge pMOSFET are simultaneously achieved by the

proposed IL treatments. The high performance can be attributed to the formation of high oxidation states in IL.

The O-N polar covalent bonds in GeON are efficiently annealed by MWA to increase Ge oxidation sate in the IL.

Ge out-diffusion or GeO desorption can be suppressed by a MWA thanks to less thermal budget. Therefore, HBL,

GeON IL, and MWA are promising process techniques for high performance Ge MOSFET.

Biography: Kuei-Shu Chang-Liao

Department of Engineering and System Science,

National Tsing Hua University, TAIWAN

Email: lkschang@ess.nthu.edu.tw

http://www2.ess.nthu.edu.tw/~lkschang/

Kuei-Shu Chang-Liao received the B.S. and M.S. degrees in Telecommunication and Electronics from National

Chiao Tung University, 1984 and 1989, respectively, and the Ph.D. degree in Electrical Engineering from

National Taiwan University in 1992.

In 1992, Dr. Chang-Liao joined the faculty at the National Tsing Hua University where he has been a

Professor of Department of Engineering and System Science since 1999. In 2000, he was a visiting research

fellow at the Department of Electrical Engineering of Yale University, where he was involved in Flash memory

and charge pumping measurement. During 2007-2010, he served as the Associate Chairman of Department of

Engineering and System Science. His current research interests include high-k/metal gate stack processes in

FinFET, Ge or SiGe MOS devices, charge-trapping flash memory devices, and trap analysis in MOS device by

charge pumping measurement.

Dr. Chang-Liao is a Distinguished Lecture of IEEE EDS, senior member of IEEE, and member of the

Electrochemical Society. He served as the Editor of IEEE Electron Device Letters during 2012-15. He received

the excellent Industry-Academic Research Award from Ministry of Education in 2003. He has published over

300 papers in prestigious journals and conferences. He has chaired and served as committee members in several

international conferences.

Reliability Challenges of Nano-interconnects

Cher Ming Tan

Abstract: The continuous scaling of VLSI has rendered the interconnects to be very narrow. The reliability of

the narrow interconnects are also changed as compared to their wider counterpart. This talk will show the different

reliability degradation of the interconnects. Further scaling is now pushing the copper interconnects running out

of steam, and many proposals are made. In this talk, the various proposals are discussed and a viable approach is

shown.

Biography:

Dr. Tan is a Singaporean, and he received his Ph.D in Electrical Engineering from

the University of Toronto in 1992. He has 10 years of working experiences in

reliability in electronic industry before joining Nanyang Technological University

(NTU), Singapore as faculty member in 1996 till 2014. He joined Chang Gung

University, Taiwan and set up a research Center on Reliability Sciences and

Technologies in Taiwan and acts as Center Director. He is Professor in Electronic

Department of Chang Gung University, Honorary Chair Professor in Ming Chi

University of Technology, Taiwan, Adjunct Professor in the College of Medicine,

and Researcher in the Chang Gung Memorial Hospital, Linkou. He has published

350+ International Journal and Conference papers, and giving 10+ keynote talks

and 50+ invited talks in International Conferences and several tutorials in International Conferences. He holds 14

patents and 1 copyright on reliability software. He has written 4 books and 3 book chapters in the field of

reliability. He is an Editor of Scientific Report, Nature Publishing Group, an Editor of IEEE Transaction on

Materials and Devices Reliability, Series Editor of SpringerBrief in Reliability, and Associate editor of

Microelectronic Reliability. He is a member of the advisory panel of Elsevier Publishing Group.

He is a past chair of IEEE Singapore Section in 2006, senior member of IEEE and ASQ, Distinguish Lecturer of

IEEE Electronic Device Society on reliability, Founding Chair and current Chair of IEEE Nanotechnology

Chapter - Singapore Section, Fellow of Institute of Engineers, Singapore, and Fellow of Singapore Quality

Institute. He is the Founding Chair of IEEE International Conference on Nanoelectronics, General Chair of ANQ

Congress 2014. He is a recipient of IEEE Region 10 Outstanding Volunteer Award in 2011. He was Guest Editor

of International J. of Nanotechnology, Nano-research letter and Microelectronic Reliability. He is in the reviewer

board of several International Journals such as Thin Solid Film, Microelectronic Reliability, various IEEE

Transactions, Reliability Engineering and System Safety etc. He is the first individual recipient of Ishikawa-Kano

Quality Award in Singapore in 2014. He is active in providing consultation to multi-national corporations on

reliability.

His research interests include reliability and failure physics modeling of electronic components and systems, finite

element modeling of materials degradation, statistical modeling of engineering systems, nano-materials and

devices reliability, and prognosis & health management of engineering system.

For more detail, please visit www.chermingtan.com

Fundamentals of Negative Capacitance Transistors

Yogesh Chauhan

Abstract: The ongoing scaling of CMOS technology is now reaching its limit, due to supply voltage reduction

being restricted by the subthreshold swing (SS) of 60mV/decade achievable at room temperature owing to

Boltzmann transport of the charge carriers. Concept of negative capacitance proposed to achieve a sub-

60mV/decade SS is currently seen as one of the potential solutions to the problem. A “negative capacitance

transistor (NCFET)” employs a ferroelectric material in the gate stack of a FET providing a negative capacitance

and thereby an “internal voltage amplification” at the gate of the internal FET which helps in reducing SS. Several

experiments have successfully demonstrated an improved SS with the bulk MOSFET, FinFET, and 2D FETs.

The improvement in subthreshold characteristics is also accompanied with the advantage of an increased ON

current relative to the reference FET as has been observed both in simulation studies and experiments. In this talk,

I will discuss the physics and modeling of various NCFET structures and impact of this new transistor on circuits

including processors.

Biography:

Yogesh Chauhan is an associate professor at IIT Kanpur. He was with IBM

Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University

of California Berkeley during 2010-2012. He is the developer of several industry

standard models: ASM-GaN-HEMT model, BSIM-BULK model (formerly

BSIM6), BSIM-CMG model and BSIM-IMG model. His research group is

involved in developing compact models for GaN transistors, FinFET,

Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs

and 2D FETs.