embedded systems design

52.360 Embedded Systems Design

Embedded Systems Design

52.360

2


What is an embedded system ? 80%+ of all processors currently sold are used in

embedded systems digital enabling technology is hidden inside the

product such as TV remote control or automotive control module

even PC’s have embedded microprocessors - the keyboard will include an embedded processor for scanning the keys and sending the data to the motherboard

highly integrated digital technology provides advantages: processing power, cost, size, time-to-market

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What is an embedded system ? A large car may have 50 microprocessors

engine management systems anti-lock brakes transmission with electronic traction control electronic gearboxes airbag systems and other safety aids air-conditioning … etc

A washing machine may have a microprocessor based control unit

motor power control for pump, wash and spin wash program control + timing

4


What is an embedded system ? Mobile phones contain more computing power

than a desktop computer had a few years ago Many toys and domestic appliances use

microprocessor control the cheapest microprocessor will cost maybe

30 pence the word “control” is at the heart of many

embedded applications for many systems the goal is to control a physical

system (temperature, motion, audio…..) using a variety of user/sensory inputs

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What is an embedded system ? Dedicated to controlling a specific device or

function - sometimes with real-time constraints Self-starting (no human intervention required).

The user does not know whether there is a microprocessor or dedicated electronic hardware inside

not designed to be programmed by a user in the same way a PC is

Self-contained, with the program( and any OS) stored in some non-volatile memory

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History …... Microprocessor invented as a programmable

replacement for calculator chips in the late 70’s up till then, control systems using digital

technology utilised individual integrated circuit devices

many chips required to form an adder function.. then an adder became available on one chip -

providing higher integration levels - smaller circuit boards

then a complete calculator functionality on one chip - even higher integration

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History …... So calculator was now low cost…..but every

change to the functionality required a new chip to be designed and created

what was needed was a more flexible device with some re-programmability inside it

a chip which took data in, processed it and sent it out again…..

so instead of silicon engineers having to revise gate-level circuits and create new chips, the user of the chip could create a new wider range of products by changing the program code…….

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A Birth in the family…. The microprocessor was born, providing

flexibility and low-cost The goal is always less cost and more

functionality the same embedded control board can be used for a

range of products ( some functions or interfaces may not even be used)

the software can be changed or upgraded and can have different versions for different applications

the cost of production per unit can be lowered by using a large production run of the same hardware

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More benefits…. Even if hardware is not re-usable the time-to-

market advantage is clear and important consider the rapid evolution of domestic

electronics VCR’s, televisions and microwave cookers need

control panels/timers. These can be designed and taken to production quicker using the highly-integrated functionality of microcontrollers to form the heart of the system

Other systems (machine tools, telephone switchgear...) can have software upgrades but utilise existing embedded hardware

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The benefits just keep coming... Many systems which would have required

expensive hardware upgrades in the past now need only software changes

this can sometimes be done remotely, using communication links

mechanical systems can be more effectively controlled by microprocessor

sensor derived data can lead to more effective control, thus reducing mechanical wear

diagnostics are available

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Embedded Systems : some areas of exploitation

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Embedded Systems : a few examples

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An engine management system... Embedded microprocessor controls fuel mix

and ignition control software considers accelerator position,

temperature and other factors engine is controlled efficiently different configurations can be supplied with

emphasis on power, torque or fuel-efficiency can even compensate for component wear (if

sensory data is available) can provide driver with information

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Don’t try this at home…. Hackers get everywhere !

There is an expanding market for “chipped” engine management units

third-party companies modify the software that is used by the control unit ( using inside information) to provide more power or torque.

Can lead to dramatic changes in the performance of the car

this may invalidate your guarantee :( this may be very unsafe :( :( may infringe the original manufacturer’s

intellectual property rights(IPR)

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Embedded Systems..smaller and cheaper Tamagochi (electronic pets)

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Scenes from a small life….

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It’ll happen to us all…...

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Cost advantage... These devices start at a cost of only £3 think about all the parts required :

casing buttons LCD display embedded microprocessor with program circuit board battery packaging

the manufacturer will wish to produce the units for a third of the retail price

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About IPR Programs are expensive to create. Hardware

and software design knowledge is what gives a company it’s competitive edge.

A hardware design may be created with only off-the-shelf parts so it can be difficult to protect the IPR. Competitors can get a board, trace the printed-circuit and if they know what the components are, can reproduce the board

some companies remove the markings from chips to make them anonymous

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Embedded software can resist detection... Some embedded software is placed in a

PROM(programmable read only memory) external to the microprocessor

this could be copied if the PROM is unsoldered from the board and read in another circuit or PROM programmer :(

Software can be programmed into PROM internal to the microprocessor. It is invisible and usually impossible to access. The IPR is protected :)

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Embedded Engineering Systems Certain logical and temporal demands are

placed on many of these systems they react to sensory information

if temperature > 40oC then …..

they may have strict deadlines sampling must be undertaken 200 times/second from the occurrence of a comm’s message a reply

must be sent within 1mS the stepping motor must be advanced 500

steps/second maximum with acceleration and deceleration ramps

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Embedded Engineering Systems may be complex systems, heavily event driven

events generated by timers, sensors, user-controls and peripheral devices ( comm’s ports, vision systems)

Systems will be engineered with cost, size, weight, robustness and reliability constraints

may required specialised operating systems and programming languages

(pSOS, VxWorks, OS/9 are examples of real-time operating systems)

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Embedded Engineering Systems (Ada is an example of a multitasking language. C is

inherently single-threaded but can be extended to multitasking capability using a library of calls to a multitasking operating system)

may require the developer to have a knowledge of the hardware/software boundary

needs knowledge of internal peripheral chip organisation, taken from data-sheets - addressing, control/data register configuration, timing issues

may require specialist development equipment such as emulators and logic analysers

emulators can trace and store processor/program activity logic analysers can capture hardware signal activity

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Embedded Systems : environment Industrial embedded systems have special

problems to cope with: electrical noise in the environment

( factory automation and automotive systems have to cope with high levels of electrical noise emissions )

wide temperature fluctuations high levels of mechanical vibration fluctuating humidity levels liquids and gases in the environment

require specially ruggedised equipment

standard Personal Computers not suitable

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Real-Time example : Process Control

PressureSensor

PressureSensor

ControllableValve

ControllableValve

PipePipe

ValveMotorValveMotor

Sensor

conditioningPressure

Reading

Processing

Computer

Output

Valve Angle

Motor

control

A/D

D/A

Controlled

Gas Flow

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Process ControlProcess

Control

Computer

ValveTemperature

Transducer

(sensor)

Chemicals and

materials

Stirrer

A Transducer generates

an electrical signal proportional

to the physical quantity being

measured

A Transducer generates

an electrical signal proportional

to the physical quantity being

measured

A valve is an example

of an Actuator. It moves

in response to electrical

stimuli

A valve is an example

of an Actuator. It moves

in response to electrical

stimuli

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Manufacturing Systems

Production

Control

Computer

Machine Tools Parts

Movement

Embedded Computer(s)

Manipulators

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Embedded Systems are often Real-Time Real-time systems can be categorised

hard real-time systems have absolute response times. If they are not met the system has failed

flight control systems, power-station control

soft real-time systems do not have such stringent deadlines and the occasional missed deadline is not critical

some systems will have both types of deadlines a soft deadline 0f 100ms (for optimal response) and a

hard deadline of 800mS (system failure if there is no response by this time)

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Remote

Devices

User

Controls

An overview….Control

Algorithms

Data Logging

and processing

Data Retrieval

and display

Communications

User Interfacing

I/O

System

Displays

Sensors Actuators

Engineering

System

Storage

devices

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Storage

Peripherals

Embedded Systems : componentsReal Time

Clock

Processor(s)

Memories

Counter/timers

Frequency

Generators

Analogue I/O

Pulse-width

ModulatorsSerial

Peripheral

Interfaces

Comm’s

Interfaces

Display

InterfacesParallel I/O

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Embedded Systems: Two examples in one

User Interface User Interfaces

IR Communications

Engineering

System

Data Retrieval

and display

Algorithms for

digital control Embedded Processorboard

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Real Time Embedded Systems Characteristics Can be large and complex

require extensive maintenance systems must be extensible because of change

and evolution in the application environment Can be small and compact

zero maintenance would be ideal we don’t want a software update for our washing-

machine or video recorder firmware (non-changeable software in ROM/PROM)

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Real Time Characteristics Can involve complex control algorithms

mathematical modelling feedback and feed-forward systems

Demand error

Controller Plant

Control

Output

Feedback (position, velocity, acceleration, temperature…)

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Real Time Characteristics

Controller

D/A Amplification

ConditioningA/D

Parallel I/O

Parallel I/O

Plant

Actuators/

sensors

Demand

Feedback

Control

Output

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Real Time Characteristics Reliability and Safety issues important

system designs must reflect the nature of their application environment

autoteller machines, medical equipment, chemical control systems, aeronautic systems

fail-safe systems and multiple redundant systems may be implemented

human error should be minimised If possible the computer system should always

double-check decisions made by humans

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Real Time Characteristics Many different real-world elements exist at

the same time motors, conveyance-systems, sensors,

displays, user-controls, databases… will require sufficient computing power to allow all

deadlines to be met

can be widely geographically distributed may require distributed computer systems or

multiprocessor systems

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Require a software structure which clearly represents the concurrency and parallelism present in the real world

Ideally we should use a software methodologies and languages which can express concurrency rather than use programmer-invented schemes

Why ? We wish to move the programmer’s awareness

and effort away from low-level structures which are not directly related to the application level activities

Less obscure solutions, easier to validate correctness, easier analysis/design, easier testing, easier maintenance

Real Time Characteristics : Software

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Real Time Characteristics : Software Requirement for a software structure which

clearly represents the time-related aspects of system behaviour

programs must be logically and temporally correct under ALL conditions. This may mean basing processor loading on “worst-case behaviour” so that it still meets deadlines predictably under all conditions

need to meet deadlines : times at which actions are to be performed when they have to be completed respond to situations when all the timing

requirements cannot be met or the timing changes dynamically due to system re-configuration

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Real Time Characteristics : Software Example real-time requirements :

sample (at certain times) at a given sampling rate sample data from sensor between 8.00 - 23.00 at

200 Hz react to certain data-patterns within a certain time-

scale (deadline) Therefore we must have a predictable behavioural

response from the computer system to the sampled data if we wish to meet the deadline

example : In a gas control system, if pressure is suddenly lost then there is a requirement to isolate part of the supply network within a finite time

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Characteristics: Interaction with hardware The nature of embedded systems is such that

computer will need to interact with the outside world using peripheral devices

software interaction with the peripherals requires the program to be able to address the peripheral hardware interface devices

peripheral interface chips will have addressable locations for reading/writing control/status/data

interface chips may generate interrupts for the processor indicating that certain operations have taken place or an error condition has arisen

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Characteristics: Interaction with hardware

Program

with

I/O read/write

calls

read

write

get_status

others…...

I/O driver

routines

read

write

get_status

others…...

I/O driver

routines

read

write

get_status

others…...

I/O driver routines

Display

Sensors

keypad

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Characteristics: Efficient Implementation efficiency of execution means that the

programmer cannot always use the highest-level of representation

the highest level abstraction may take extra execution time which may be excessive for a particular application

the programmer must be aware of the cost of particular software operations

if a response to an event is required within 20 microseconds then it is no good using a high-level software feature which takes 40 microseconds

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Embedded systems software We will return later to the subject of software for

embedded systems multitasking + scheduling real-time kernels languages communication synchronisation mutual exclusion I/O drivers and hardware interaction prioritisation

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Back to hardware….. First we have an introduction to the hardware

contained in embedded systems… we will start by a brief examination of digital signal

processing and see how analogue electronic systems can be replaced by digital systems……….

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Digital can replace analogue Increasing levels of processor power allow high

performance applications to be performed digitally - digital signal processing

take an example of an analogue filter required to remove noise and other high frequency components from a sensor signal

+

-input

output

t

V

t

V

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Analogue components Analogue components work on a continuous basis,

with infinite values within the range they work in can implement sophisticated mathematical functions they are cheap and can form many different circuits are extremely fast ( can easily process GHz rate signals)

but suffer (to a small extent) from component ageing drift (with temperature for instance) noise pickup

also fairly fixed functionality once the circuit is implemented

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Digital signal processing (DSP) The digital equivalent of the filter is a fast

processor which can sample the input signal, process it and output the signal sufficiently often to maintain similar accuracy, resolution and frequency response

it must provide the same function as the original analogue implementation

but there is a major difference since the digital version must sample the input then

this is not a continuous system - rather, it is a discrete system.

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Digital signal processing The implementation of the filter function

requires an equation of the form :

where C comes from a coefficient table and the X values are sampled analogue input values

this means there must be a set of multiply and accumulate operations executed for every sample

we must continuously sample, execute the instructions for the equation, then output the new value

n

kxc knn

0)()(

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Time analysis for a digital filter….Sample/

hold A/D Processor D/A

t

SamplenSamplen+1

outputProcess n instructions

The higher the input bandwidth, the higher the sampling rate needs to be to collect sufficient samples

the higher the sampling rate, the faster the processor has to be to execute the n instructions between samples

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Sampling power required…. For DSP applications the sampling speed is

usually twice the frequency of the highest frequency signal signal being processed

Nyquist's theorem: A theorem, developed by H. Nyquist, which states that an analogue signal waveform may be uniquely reconstructed, without error, from samples taken at equal time intervals. The sampling rate must be equal to, or greater than, twice the highest frequency component in the analogue signal.

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Processing power required…. Let’s look at options for a DSP application:

Instructioncycle-time

Samplingfrequency

Inter-sample time

No. ofinstructionsbetween twosamples

1KHz 1mS 1K10KHz 100S 100100KHz 10S 10

1S

1MHz 1S 11KHz 1mS 10K10KHz 100S 1K100KHz 10S 100

100nS

1MHz 1S 10

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Processing power and sampling rate... The faster the sampling rate the more power is

required. For example: to achieve a 1MHz sampling frequency,

a 10 MIPS processor is required whose instruction set is powerful enough to complete the required processing in under 10 instructions

from Nyquist’s theorem, this would allow us to process signals up to 500kHz

specialised DSP processors with an architecture and special instructions geared to the types of operations required by signal processing applications

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Why use digital signal processors ? Given the complexity involved, why do we

bother using DSP technology ? No component ageing low drift ( apart form A/D which requires careful

printed-circuit layout and clean power supply) no adjustments required high noise immunity ( we are using all digital

processing) small amounts of analogue noise voltage have no

effect on digital logic devices. In analogue components(especially amplifiers and adders) noise can be a problem.

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Why use digital signal processors ? Can include extra self-testing features. This helps at

production-time and also for maintenance and fault-finding

Software is the ultimately flexible tool. Just by changing a few coefficients we can have a completely different filter for example. We can parameterise the software to allow a wide range of functionality with the same hardware.

DSP can be performed by ordinary microprocessors, but the general-purpose nature of their instruction-set limits their performance and thus frequency response.

We will look at a representative DSP device later

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Embedded system components: Processor does it provide required processing-power ?

Tasks can be under-specified or under-estimated system evolves during development and

outgrows the processing power inadequate benchmarking has been performed

for instance, a test program which is inadequate may run only in the processor cache and thus make the processor look very impressive. The actual programs may not manage to utilise the cache in the same way and execute mainly out of cache, leading to a slower system than was anticipated

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Embedded system components: Processor Software overheads for high-level-

languages(HLL’s) Operating systems and heavily loaded interrupts may tax the processor

the overall cost of a processor is not just the chip! How much power does it consume ? Heat-sink required ? Space on PCB required other support chips required ? What is it’s availability and delivery time ? Engineer’s experience of processor / learning

curve price of software tools ( compilers, debuggers,

emulators, operating systems)

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Embedded system components: Memory Software storage -ROM and PROM on-chip Read Only Memory (ROM)

external Programmable ROM (PROM) development versions of these are called Erasable

PROM (EPROM) Contains initialisation (bootstrap) code and application

code External RAM is used for data storage microcontrollers usually contain a small amount of internal

RAM as well as ROM storage - maybe as little as 256 bytes up to a few K’s. Some applications are engineered to use just on-chip RAM as an economy. External RAM may cost as much as a processor

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Embedded system components: Memory Non-volatile memory devices can be programmed as

a system is powered-up and executing. The stored data is retained when the system is powered-down

battery-backed-up RAM modules non-powered non-volatile RAM devices Flash memory devices - high density (1Mbyte

upwards in each device) - can be used to create Flash-disks (totally semiconductor non-volatile file storage)

many microcontrollers may include an area of non-volatile memory internally

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Embedded system components: Peripherals interfaces for analogue peripheral devices

Input conditioning Conversion/buffering

processing

Conversion/storageOutput conditioning

sensors

Motors, actuators,

pumps, temperature

control, position-

control, audio, video etc

analogue digital

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Embedded system components: Peripherals Example : a PWM motor controller:

inputs are: demanded speed - user input actual speed - sensor output

output is: pulse-width modulated (PWM) waveform to control

power-switching to the motor

Counter/timer

microcontroller

A/D converter

+ - start stop

Parallel interface

Power amplifier

PWM Waveform

V

t

Speed Sensor (tachometer) output

Software to implement

motor control

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Embedded system components: Peripherals Main types of peripherals :

binary outputs - simple external pins which can output a ‘1’ or a ‘0’ (5V or 0V approx.).Often grouped together to form parallel ports where a group of bits can be input or output simultaneously. Once a bit is set, the value remains because it uses a latching flip-flop implementation

serial outputs - send and receive data using a transmit(tx) pin and a receive(rx) pin on a chip. Parallel data is written to a register and the serial port logic automatically sends it serially, bit by bit, out on the tx pin at a program selectable rate. Status register information is available to be read by a program and error information is also available.

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Embedded system components: Peripherals Analogue interfaces: the real world often provides

continuous analogue information whereas the digital world works with discrete values. Conversion circuits are required

Displays : simple seven-segment light-emitting-diode(LED) displays, individual LED’s, liquid-crystal-displays(LCD) of various forms including graphic and alpha-numeric, monitors and other display technologies

Time related values: counter-timer devices allow rate-generation, PWM, single-shot pulse(one pulse of deterministic length) and also allow measurement of time and rate from externally generated pulse sources.

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Microcontrollers Microcontrollers are self-contained systems

with processor, memory and peripherals in many cases an application can be created just by

adding software in other cases extra external memory (PROM, RAM)

and other peripherals can be added while still utilising the internal functionality)

processors are often 8 or 16-bit stack-based architectures

there are also cheap 4-bit processors available usually a family of microcontrollers will have several

variants with different or extra facilities added

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Motorola Microcontroller: MC68HC11EA9

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Microcontrollers Microcontroller will be available in several

forms: devices for prototyping:

programmer must be able to load code into the processor

Ultra-Violet(UV) erasable EPROM or electrically erasable(EEPROM) parts are used to store the program

this replaces the ROM into which the program will be mask-programmed during a production-run of the processor (a volume of 2000 upwards may be required by the manufacturer before they will do this).

66


Microcontrollers Internal non-volatile RAM (NVRAM)versions mean

that a company can create a low-volume production run of a particular product with the program set into the NVRAM

NVRAM also permits customisation of the program if a number of variants of a product are required

One-time programmable(OTP) are available. These are cheaper than the PROM or EEPROM versions and can thus be used economically for low to medium volume production runs. They have a slight disadvantage in the cost of time/personnel to program them, but the flexibility outweighs this

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Microcontrollers for high-volume product Devices for high-volume production

Customer supplies software to chip manufacturer manufacturer creates the masks which form the ROM

of the device these masks are used to form a new layer on partially

completed silicon wafers (to reduce turnaround time) costs are lowered production time lowered (no chip programming to be

done by the chip user) but………..

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Microcontrollers for high-volume product Minimum order must be placed based on the number of

chips that a wafer-batch can produce one-off tooling charge for creating the mask software cannot be changed until another production run there may already be parts in the production

pipeline(packaging/testing etc) and these will have to be scrapped if a program needs changed

some customisation may be available in the form of different software modules being included in the ROM. Modules can be selected by a coded word read into a port of the microcontroller. A design could include extra external hardware to allow the code to be set for a particular product.

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Expanded microcontroller mode This very flexible mode allows the use of external

RAM/ROM/other external devices where internal facilities are insufficient there is is a resultant

cost in the extra components and the non-availability of the ports used up by the external devices. However, many designs utilise this mode while still using the internal facilities

Data/address buses

RAM PROM

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Evolution….. There is very much a trend towards high levels of

integration to put as many functions as possible inside a single chip

in earlier years people might use standard microprocessors (such as appear in workstations/PC’s) and add external peripheral hardware. Foe example: MC68020, 30 and 40. Intel 80286,386.486, Pentium… , Power-PC, MIPS

Now the latest processors are combined with many peripheral functions to form special purpose integrated processors. These are much more powerful than the small microcontrollers.

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Board-based embedded systems We have assumed so far that the hardware always needs to

be designed, built and debugged before the product development can progress further. This process can delay a product for weeks or months depending on the board(s) complexity. There exist a range of levels of integration

One alternative is to use a board-based solution where already existing hardware boards are used. These are built to certain recognised standards (VME-bus interconnect for instance) and are ready-to-go.

Main advantage is reduced workload (don’t need expert hardware engineers), reduced time-scales and the availability of perhaps OS/software application modules. Good solution for low-volume

there is a higher cost and perhaps restricted functionality or unused functionality (not really a problem)

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Board-based embedded systems VME-bus rack system

Boards slot-in here

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Board-based embedded systems A VME-bus card.

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Embedded processors Embedded processor evolution has closely followed

that of standard microprocessors better chip fabrication technology

higher transistor density - more transistors lower power dissipation smaller processor core leaves room for

peripherals to be integrated onto chip four basic architectures used:

8-bit 16/32 bit complex instruction set (CISC) Reduced Instruction Set (RISC) Digital Signal Processor (DSP)

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Embedded Microcontrollers are a big business World-Wide Microcontroller Shipments (in millions of dollars)

'90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00

4-bit 1,393 1,597 1,596 1,698 1,761 1,826 1,849 1,881 1,856 1,816 1,757

8-bit 2,077 2,615 2,862 3,703 4,689 5,634 6,553 7,529 8,423 9,219 9,715

16-bit 192 303 340 484 810 1,170 1,628 2,191 2,969 3,678 4,405

World-Wide Microcontroller Shipments (in Millions)

'90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00

4-bit 778 906 979 1036 1063 1110 1100 1096 1064 1025 970

8-bit 588 753 843 1073 1449 1803 2123 2374 2556 2681 2700

16-bit 22 38 45 59 106 157 227 313 419 501 585

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Embedded Microcontrollers are a big business look back at the table even the lowly 4-bit processor device is holding its own

what use is a 16-bit part in a toaster? the 8-bit market just keeps growing, and will probably

continue to grow. 8-bit devices account for over half of the market, and will eventually have a larger proportion.

All silicon manufacturer market their 8-bit processor range very aggressively because the market is worth billions of dollars world-wide

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Electronics is the driving force...Average Semiconductor Content per Passenger Automobile (in Dollars)

'90 '91 '92 '93 '94 '95 '96 '97 '98 '99 '00

$ 595 634 712 905 1,068 1,237 1,339 1,410 1,574 1,852 2,126

Source: ICE - 1994

The automotive market is the most important single driving force in the microcontroller market, especially at it's high end.

Several microcontroller families were developed specifically for automotive applications and were subsequently modified to serve other embedded applications.

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Sales Company Units (K) 1993Motorola 358,894Mitsubishi 71,674NEC 70,180Hitachi 67,873Philips 56,680Intel 46,876SGS-Thomson 37,350Microchip 35,477Matsushitta 34,200Toshiba 32,205National Semiconductor 31,634Zilog 31,000Texas Instruments 29,725Siemens 20,874Sharp 17,505

SOURCE:DataQuest June 1994

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Growing markets….. The automotive market is demanding. Electronics must

operate under extreme temperatures and be able to withstand vibration, shock, and EMI. The electronics must be reliable, because a failure that causes an accident can (and does) result in multi-million dollar lawsuits.

Reliability standards are high - but because these electronics also compete in the consumer market - they have a low price tag.

Automotive is not the only market that is growing. DataQuest says that in the average North American's home

there are 35 microcontrollers. By the year 2000 - that number will grow to 240. Consumer electronics is a booming business.

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How do you choose ? When deciding which devices to implement in a design, there

are lots of things to consider besides who else is using these devices (and how many are they using). Can I expect help when I am having problems? What development tools are available and how much do they

cost What sort of documentation is available (reference manuals,

application notes, books)? Can I reduce prices by purchasing more devices at one

manufacturer? That is, purchasing not only the microcontroller, but also peripherals (A/D, memory, voltage regulator, etc.) from one company).

Do they support one-time programmable(OTP), windowed devices, mask-programmable(at the chip manufacturer) parts?

81


Embedded processors - life cycle Standard microprocessors have a life cycle…..

they are released as high performance devices over a period of 15 or more years they gradually

become medium-to-low performance(comparatively speaking) as higher performance devices are released

their life-cycle would naturally end here. They are no longer sold as standalone processors but…..

The basic design continues to be used when the processor core has been utilised as the heart of a highly integrated device.

82


Embedded processors - life cycle Take for example the Motorola M6800 - one of the

early microprocessors released in 1975 a simple 8-bit architecture with 1Mhz clock speed most of the instructions execute in 2 or 3 clock cycles no sophisticated architectural features The 6800 had end-of-life in 1993. No new designs utilising

6800 would have been started for a number of years - but existing product production may have demanded the availability of the chip

However, there are over 200 MC6801/6805/68HC11 microcontroller variants in production, utilising a processor architecture/instruction-set similar to the 6800 (speeds from 1MHz to 4MHz, 90 extra op-codes in HC11’s )

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Embedded processors - floor-plan - 68HC11A8

Here is a Motorola MC68HC11A8 microcontroller chip. Notice the small space taken by the CPU against the space taken by all the other parts integrated on the chip.

85


Embedded processors - floor-plan - 68HC11Here is a Motorola MC68HC11E9 microcontroller chip. More RAM and ROM on-chip means more space given to these.

86


HC11A8 packaging

87


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HC11 registers Although this looks like a primitive model the

addressing modes enrich the functionality : many instructions can act directly on memory using

the index registers as pointers the A and B registers can also be manipulated as a

single 16-bit data register (D reg) for add, subtract and shift operations. Multiply is still 8-bit operands only

there is a dedicated stack pointer register stack is used to provide local storage for functions

and also hold return addresses for function calls and interrupts

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Addressing memory…... When 8-bit microprocessors appeared in the

1970’s, memory was .. expensive only available in small sizes (256 bytes up to 1K) applications were small

written in assembler before specialised compilers were written for the processors

the 64K address space offered by the processors seemed huge and would never be used up!

advent of high-level-languages(HLL’s) and operating systems (like CP/M) increased memory requirements

memory started to become a limitation

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System Integrity Simple architectures can be unpredictable in handling error

conditions and limit the use of the processors to non-critical applications

software bug could cause data corruption system crash system hangs system performs unforeseen operations !

There is no partitioning between programs and data within the architecture

an application could overwrite its program area using a corrupt pointer for example

in some architectures certain undocumented code sequences could put a machine into test mode !!!!!

91


Integrated Processors These combine high performance processors

together with specialised I/O facilities to form the basis of powerful but low chip-count systems

The processor core is usually an already proven design which has development facilities and software available

the MC683xx family contains a 68000 family core, timer systems, watchdogs, secondary RISC processor to handle specialised data-communication peripherals and also specialised timer systems

new versions are also available with a PowerPC processor core

92


Integrated Processor example:MC68LC302

The main features of this device are outlined in the next two pages. They are provided to indicate the richness of functionality available within highly integrated devices and are not to be committed to your memory!

93


Features of MC68LC302 :On-Chip Static 68000 Core supporting a 16- or 8-Bit M68000 Family System• System Interface Bus Including:

•Independent Direct Memory Access (IDMA) Controller•Interrupt Controller with Two Modes of Operation•Parallel Input/Output (I/O) Ports, Some with Interrupt Capability•On-Chip 1152-Byte Dual-Port RAM•Three Timers Including a Watchdog Timer•New Periodic Interrupt Timer (PIT)•Four Programmable Chip-Select Lines with Wait-State Generator Logic•Programmable Address Mapping of the Dual-Port RAM and IMP Registers (provides flexibility in designing the system memory map)•On-Chip Clock Generator with Output Signal•On-Chip PLL Allows Operation with 32 kHz or 4 MHz Crystals•Glue-less Interface to EPROM, SRAM, Flash EPROM, and EEPROM

94


Features of MC68LC302 :•Built-in communications processor (CP) Including a RISC Processor •Two independent full-duplex serial communications controllers (SCCs) supporting various protocols:

•High-Level/Synchronous Data Link Control (HDLC/SDLC)•Universal Asynchronous Receiver Transmitter (UART)•Binary Synchronous Communication (BISYNC)•Autobaud Support and V.110 Rate Adaption

•Four Serial DMA Channels for the Two SCCs•Flexible Physical Interface Accessible by SCCs Including:

•Motorola Interchip Digital Link (IDL)•General Circuit Interface (GCI, Also Known as IOM-2 1 )•Pulse Code Modulation (PCM) Highway Interface•Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem

•SCP for Synchronous Communication•Two Serial Management Controllers (SMCs)

•100 Pin Thin Quad Flat Pack (TQFP) Packaging

95


Highly Integrated : the benefits... Functions which normally require external chips

are now integrated inside one chip save money save board space (so it’s smaller and also cheaper) the more integrated, the higher the overall system

reliability as processor cores become mainstream, they can be

included as the core of these integrated products the latest versions of these Motorola integrated

processors are using a 50MHz PowerPC processor core.

Buffering and low-level protocol management is performed by the specialised comms processor

96


Highly Integrated : the benefits... This particular device (MC68LC302 ) is a specialised

communications device, so.. As the low level protocol code is actually

implemented in microcode inside the comms co-processor, the main processor (68000 or PowerPC) is freed-up to take care of the higher-level layers of the protocols

Can cope with a combined bandwidth up to 2Mbits over three comms channels

also, chip select lines are available so these devices can be connected to external chips (EPROM, RAM etc) without the requirement for an external decoder………….

97


Space saving: before……..

Address decoder

Glue logic - probably a PLD

RAM

ROM

Address Bus. The data bus and other connections are not

shown and……..

Chip select lines

Standard processor

98


Space saving: after……..Look..no glue logic required!

RAM

ROM

Address Bus. The data bus and other connections are not

shown

Chip select lines

Processor with built-in decoding

for external devices

99


Digital signal Processors In the strict sense of the term, digital signal processing refers

to the electronic processing of signals such as sound, radio, and microwaves.

In practice, the same characteristics that make Digital Signal Processors (DSPs) so good at handling signals make them suitable for many other purposes, such as high-quality graphics processing and engineering simulations.

DSPs are essentially super fast number-crunchers and just about any application that involves rapid numeric processing is a candidate for digital signal processing.

100


Digital Signal Processors Overview Like earlier advances in microprocessors and computer memories,

digital signal processing is a foundation technology with the power to transform broad areas of the electronics industry. Its impact is being felt in applications as diverse as stereo systems, cars, personal computers, and cellular phones. In the next few years, digital signal processing will give rise to hundreds of new products and change what people expect from technology.

Digital signal processing takes real-time, high-speed information, such as radio, sound or video signals, and manipulates it for a variety of purposes. Digital signal processing can restore vintage jazz recordings to their original clarity, erase the static from long-distance phone lines and enable satellites to pick out terrestrial objects as small as a golf ball.

101


Digital Signal Processors Overview In cars, Digital Signal Processors (DSPs) create digital audio

“surround sound” and are responsible for active suspension systems that adjust automatically to road conditions. In cellular phones, digital signal processing helps squeeze more conversations onto crowded airwaves and can scramble signals to thwart eavesdroppers. In multimedia computers, digital signal processing generates business communication at the user’s fingertips and professional audio sound in real time.

Once used primarily for academic research and futuristic military applications, digital signal processing has become a widely accessible commercial technology. In the last few years, a variety of high-performance, integrated DSP’s have made digital signal processing technology easier and more affordable to use, particularly in low-end applications.

102


Digital Signal Processors Overview Also, software and development tools are more available so

equipment manufacturers are becoming experienced in the use of DSPs and sales are expanding rapidly.

The market for DSP chips is growing at twice the rate of the semiconductor industry as a whole, according to Forward Concepts of Tempe, Arizona. Over the next few years the digital signal processing business is expected to increase by 33 percent annually, leading to an overall market of $11 billion in 1999. About $4.5 billion of this will be for general purpose DSPs.

Specialist DSP’s are available for applications such as audio processing where the DSP core is integrated with audio functionality (A/D, D/A, filters etc) on one chip

103


DSP Background Started as specialist processors for digital signal

processing algorithms an example is a finite impulse response (FIR)

filter requires the setting-up of two tables, one

containing sampled data, the other filter-coefficients that determine the filter response

program then performs a series of repeated multiply and accumulates using values form the tables

the attainable bandwidth of the filter depends on the speed of these simple operations

104


Motorola DSP56002 DSP This processor uses a DSP56000 core ( as

described in Heath) and adds internal memory storage for program and data - lowering the system cost/complexity/size

Enhanced Harvard architecture 3 separate internal buses work in parallel :

one program bus 2 data buses

24 x 24bit multiplication six 24-bit registers for loop counts, operating

mode, stack manipulation and condition codes

105


106


Motorola DSP56002 DSP ALU has two 56-bit accumulators A and B Four 24-bit registers X0, X1, Y0, Y1

can also be paired to give two 48-bit registers The power of this type of processor is provided

through its ability to deliver fast parallel operations typically the multiply accumulate (MAC)

instruction is optimised for parallel operation this is the operation which we saw used repeatedly

in a typical digital filter application

n

kxc knk

0)()(

multiplyaccumulate

107


Multiply accumulate instruction

ALU operations for MAC

instruction

24-bit 24-bit

multiply

56-bit accumulator

adder

X-memory

Y-memory

108


Multiply accumulate instruction details When a MAC instruction is executed, two 24-bit

values from X or Y regs in the ALU are multiplied together and the result added or subtracted from the 56-bit accumulator

While this execution takes place, two new values are taken from X and Y memory into the X and Y regs in the ALU ready for the next calculation

So, loading, multiplication and accumulation are all taking place at the same time. A 27MHz version of the chip does all these operations within a single 75 nanosecond machine cycle (1000 nanoseconds in a microsecond. A microsecond is one millionth of a second)

109


other features to note Instruction-set has many other commonly used

instructions as well as the specialised ones Internal ROM-based lookup tables to for sine waves

conversions and other commonly used signal processing conversions - lookup is far faster than a computed solution

external address bus offers 64K address space to external data/program memory and peripheral devices

there is now a manufacturer trend to integrate peripheral functions with a DSP core to provide very high computational performance with high integration

110


Processor Selection

Microcontrollers

Integrated Processors

Discrete Microprocessors

Performance

Sys

tem

Cos

t

Microcontrollers

Integrated Processors

Discrete Microprocessors

Performance

Sys

tem

In

tegr

atio

n

111


Memory Systems There are many types of memory devices -

each with a range of application areas issues include

access speed density (how many locations can be crammed

into a certain space on silicon) cost chip size programmability (PROM, EPROM, EEPROM...) volatility

112


The memory interface In general the interface is a shown below

address lines

bidirectional data lines

Chip Select line

Read/notWrite line

Memory chip

Output enable line

113


Memory signals Address bus

allows selection of a particular address within the device.

Signals may be multiplexed (DRAM usually has multiplexed lines) or non-multiplexed ( SRAM will be non multiplexed)

Data bus allows data in to and out of the chip. Usually the same

pins are used for input and output since either a read or a write operation will take place at one time. Some types have separate read and write data lines.

The data direction is governed by the state of the read/notWrite line

114


Memory chip signals When he read/notWrite line is high then data is

read from the chip at the current address on the address lines

When he read/notWrite line is low then data is written to the chip at the current address on the address lines

the output enable line governs whether the chip can drive the data bus during a read operation

since many peripheral/memory devices will share the data-bus, there must be a method for isolating them from driving the data bus except when they are required to provide data onto the bus

115


Tristate isolationin out

Tristate enable

One bit of a data-bus

in out

Tristate enable

Chip 1

Chip 2

Chip 1 output enable

Chip 2 output enable

In tristate out

0 0 isolated

1 0 isolated

0 1 0

1 1 1

116


Memory chip signals A chip select line is like an additional address line so

that an individual memory chip can be enabled if there is an array of memory chips connected to a processor Address bus

from processor

Data from RAMAddress decoder

Higher address

lines

Individual chip selects

117


Processor-Memory interface

Read/notWrite

Address decoder

Higher address

lines

Individual chip selects

Data bus

Address bus

Clock line Processor

RAM RAM RAM

118


DRAM (dynamic RAM) devices Used where large amounts of memory are

required at low cost the cost per bit of a memory device is dependent on

two factors the number of transistors required to store each

bit of data the type of packaging that is used

DRAM has high density and low cost because it uses only a single transistor cell to store each bit of data

119


DRAM configuration The storage element is actually a small capacitor whose

voltage represents a binary zero or one a capacitor is an electronic component which stores

charge for a short period of time - the amount of charge stored and the time period it is stored for is related to the value(or capacitance) of the device. The charge will disappear after a number of milliseconds

A single transistor is used to enable the storage and readback of the stored value.

In comparison, a static RAM (SRAM) cell requires at least four or five transistors for each bit of storage because each bit is formed from a flip-flop gate configuration which can be flipped from a 1 to a 0 state

120


DRAM cell

Address enabled

Data bit 1

WRITE CYCLE

Address enabled

Data bit

1 READ CYCLE

capacitor

capacitor

transistor

transistor

121


DRAM issues DRAM does have some drawbacks and some benefits

when compared to static RAM devices the term ‘dynamic’ refers to the requirement for a

DRAM device to have each of its locations refreshed. Unless the charge in the capacitors is topped-up(refreshed) then the memory values will be lost

the overhead is that 3-4% of the theoretical access time must be given over to refresh cycles. This is done by an external controller chip which will refresh all DRAM devices in a system or by a processor which has in-built DRAM refresh logic

this small percentage is a small price to pay for the added density available - four times the density of SRAM

122


DRAM interface

notRAS

notCAS

A0-A9

Data out Read data

Row address

Column address

123


Internal Construction DRAM or SRAM - Only one data-bit shown

D Q D Q

D QD Q

D QD Q

D Q D Q

Column decoder

11 10 01 00

A1 A0

1 1

Row decoder

A21

1

0

Data In

Read/notWrite

Data Out

Data Inputs

Data Outputs

Select inputs

000

111

124


Static RAM Does not require refresh

maintains data indefinitely as long as it is powered-up supports low-power operation

lower power than DRAM Although containing more transistors, the memory

cell only uses power when being switched from one value to another. If the cell is not accessed then the power drain is negligible (micro-Amps)

DRAM have to be refreshed regularly so consume much more power

SRAM memory interface is much simpler than DRAM interface

125


Static RAM Typical use of SRAM

low-power main memory for portable equipment expansion memory (external memory) for

microcontrollers cache memories video memory

Pseudo static RAM: DRAM and refresh controller inside one chip

provides high density simplifies the microprocessor interface low cost but needs more power

126


DRAM Refresh Techniques Periodic refresh to maintain all data

access the DRAM using special refresh cycle no other access available at this time

Refresh involves first reading memory locations then immediately writing the contents back into a cell

usually done a whole row or column at one time whole chip must be accessed within a certain time period

or the data will be lost common refresh periods - 15.6 microseconds and 125

microseconds with each refresh lasting 125 microseconds Typically 3-4% of the processor time is given to refresh

DRAM inaccessible to processor so processor has to wait until a refresh cycle is complete

127


DRAM Refresh Techniques Burst versus distributed refresh

a 4M x 1bit DRAM requires 1024 refresh cycles should the cycles all happen in a burst or should they

be distributed across the whole time? A burst may mean a delay of 0.2mS in this

example a distributed implementation would mean a worst-

case delay 0f 170nS In real time systems we may not be able to afford the

0.2mS delay because we might miss deadlines!

128


DRAM Refresh controller

Multiplexer

Arbiter

DRAM

Refresh Address counter

System address bus

MemRequest

wait

RefreshRequestNormal/notRefresh

Address select

129


DRAM Refresh Refresh involves reading each memory location

then immediately writing back the contents usually done one row or column at a time refresh counter is required to cycle through all

memory locations Multiplexer allows both processor access and refresh

counter access arbiter allows either the processor or the reafresh

logic to take control at one time, but not both.

130


Other memory types Pseudo static RAM

uses DRAM with internal refresh logic. Makes the device look like it has an SRAM interface

Battery-backed-up SRAM uses integrated battery to keep RAM powered when

equipment is powered-down. The SRAM drain on the battery can be lower than the battery’s own leakage current.

EPROM used for programs and data(such as tables) which

does not change. Re-usable and one-time-programmable versions(cheaper) are available

131


Other memory types Flash memory

another non-volatile memory device with high density. Low cost per byte Slow to write(can take several milliseconds) as against

60-100nS for DRAM and faster for SRAM. Useful as solid-state disk-drive on a write operation an entire block of memory has to

be replaced at once so not so good for random access writing use

Useful for remote software upgrades. New modems use flash memory to store their programs. Software upgrades are available by download and are then installed inside the internal flash memory.

132


Other memory types EEPROM

electrically erasable PROM high density slow to write they “wear out” after a few 10’s of thousands of

write cycles so are not good for general-purpose memory

good for program storage or infrequently changed persistent data

133


Other memory types Dual port memory

two sources can access the memory device to allow sharing of data or programs.

Used as a communication mechanism between processors

requires arbitration logic to prevent simultaneous access from two sources

one processor may be held in a memory “wait state” until the other has finished a memory cycle

134


Other memory types Microcontrollers often have several memory

types integrated. For example: Non-volatile (EEROM) - data or program Static RAM maybe 128 bytes up to a few K’s ROM - mask programmed 16K or 32K EPROM - UV erasable - data or program

135


Synchronous and Asynchronous interface Synchronous - fixed cycle time

address and data appear on the bus for a fixed period of time measured in processor clock cycles all peripherals must be able to be written to or read from at this speed cannot make any special use of a faster peripheral chip - must work at the speed of the slowest many simple microprocessor and microcontrollers work with synchronous busses

136


Synchronous and Asynchronous interface Asynchronous - variable cycle time

address and data appear on the bus for a variable period of time related to how long a transfer takes to any particular peripheral chip

can use slow or fast peripheral chips and work at the speed of each of them

137


Asynchronous Timing Diagram - M68000

A0 - A31

Not Data Acknowledge

Not Data strobe

Not Address strobe

Read/notWrite

D0-D15

138


Asynchronous Timing Diagram - M68000A Read Cycle:1. Address and read/notWrite line become active

2. Address Strobe(notAS) validates(indicates that the signal is valid) the address lines and the data-strobe(notDS)

3. A certain time after the occurrence of the address strobe the peripheral activates the notDTACK (notDataAcknowledge) line to indicate that the data is available. The processor will maintain the read cycle until the notDTACK is asserted.

4. The processor will read the data on the next clock cycle and remove the notAS/notDS strobes and the address on the bus.

139


Asynchronous Timing - M68000 Some peripheral devices include internal logic to

generate the notDTACK signal. They are designed to interface with this type of Motorola processor.

Many other devices, including memory chips, will have no notDTACK generation since the chips are designed to be used with many processor types - synchronous or asynchronous.

In this case some extra timing logic has to be provided to generate the notDTACK signal for each peripheral.

140


Peripherals: parallel port To input or output binary data

one pin for each bit of the I/O port Output: each bit can be set to a “1” or a “0” which

appears as 0V or 5V at the relevant pin Input: 5V or 0V at an input pin can be read by the

processor procesor reads or writes to all bits at once only a limited current is available from pins when they

are configured as outputs amplification required if a non logic-level device is

to be driven by an output

141


Parallel port internal configuration

1 1 0 0 0 1 0 0

0 0 1 1 0 1 1 1

Data direction register. “1” = read, “0” = Write

Data direction bit = “1” so this buffer is enabled - allowing this to be an input

Disabled since DDR sets this bit to be in read modepin

0pin

1

Data register

142


Motorola 68HC11 : multifunction I/O ports are available. If not configured to use the specialised peripherals(SPI, SCI. Timers, A/D) these ports can be used as input, output or I/O pins. The configuration is under software control.

143


Parallel port outputs Output pins may typically only provide up to 25mA

current output at 5V This may be sufficient to drive (for example) a low

current LED but not any higher power device

Current flow

Parallel port output

1

144


Parallel port outputs For higher power devices amplification is

required


1

24V

24V, 1 amp5V, 20 mA

24V DC Pump, On/Off control

Amplifier is a source of current

145


Parallel port outputs Other power-transistor devices can sink current


1

24V

1 amp5V = ON 0V = OFF negligible current flow required to switch transistor

24V DC Pump, On/Off control

146


Counters and Timers Generate waveforms

rate controlsimple audio frequenciesDRAM refresh clock pulse every 15 microseconds

PWM outputmotor speed controlaverage power control

one shot pulse output

147


Counters and Timers Time measurement

example : measure time between two pulses to calculate motor speed

Slotted disc and Slotted Hall-effect sensor

5V

Hall effect sensor

Counter timer

microcontroller

motor

148


Counters and Timers Timed interrupt generation

OS periodic Clock “tick” for scheduling. Each clock tick runs an ISR which updates the system time and also allows the OS scheduler to check for rescheduling (if time-sliced scheduling is being used)

OS time functions examples: sleep(10) or delay(50)

Counter timer

microcontroller

Interrupt handling

149


Counters and Timers Structure Basic structure of a simple counter/timer

00000

Pre-scalar or clock-divider

5-bit pre-scalar can provide ÷1 up to ÷64

Dividers only offer division by powers of two ÷2 , ÷4, etc

6425189

Addressable counter register

I/O Control

Input signals

Output signals

interrupts

150


Counters and Timers modes Interrupt on terminal count

6425189

6425187

...0000001

Load initial value

Count down by 1 on every clock signal

0000000 Interrupt generated

151


Counters and Timers modes Programmable One-shot

6425189

6425187

...0000001

Load initial value

Count down by 1 on every clock signal

Output goes high

0000000 Output goes low

152


Serial Ports Pin efficient method of communicating with

other devices in an embedded system the narrow interface is traded-off against longer

transfer time since the data is not transmitted in parallel but serially, one bit at a time

some simple microcontrollers may have a very low pin count (maybe 16-pins) and may not have a parallel port so a serial port is the only way that they can communicate with other devices

various peripherals are available with serial I/O connections instead of the normal parallel connections

153


Serial Ports The simplest serial ports are a pair of shift registers

connected together with one input (receiver) connected to the output of the other(transmitter)

They are clocked together by a common clock and data transferred from one register to the other

The transfer time is dependant on the clock frequency and the number of bits to be transferred.

The shift registers are normally 8-bits wide When a register is emptied (last bit has been

transferred) it can generate a local interrupt which can indicate to the processor that it is time to write a new value into the register

154


Serial Ports The receiver can also generate an interrupt when a

complete byte is received so it can be read by the program

Most serial ports will use a FIFO buffer to ensure that the last byte(s) is not overwritten by the next data transfer before the program has a chance to read the value

A transmitter can also have a FIFO so that a number of bytes to be transmitted can be inserted in the FIFO

The size of the FIFO is important in terms of reducing processor overhead and increasing the throughput of data since no processor intervention is required to allow continuous transmission of data as long as the FIFO’s are filled and read regularly

155


Serial connection

Serial peripheral

port

Serial peripheral

port

Tx

Rx Tx

Rx

clock

Micro A Micro B

Only one source for the clock - Micro A or Micro B

156


Basic data transfer

0 1 1 0 1 1 0

0 1 1 0 1 1

0 1 1 0 1

0 1 1 0 1 1 0 0

0 1

0 1 1

0 1 1 0

0

0

0 0

1 0 0

1 0 1 1 0 0

0 1 1 0 0

1 1 0 0

1 1 0 1 1 0 0

0 1 1 0 1 1 0 0

n

n+8

Interrupt: transmitter empty Interrupt: receiver full

157


Asynchronous Communications Interface The previous scheme required a Tx, Rx and

clock line to allow data to be synchronised. Data is strobed into the Rx shift register on each clock pulse

with a small distance between chips the small voltage and current levels are acceptable

if data is being transmitted over longer distances then another scheme is required

cable resistance and capacitance mean that signal levels can be reduced and also signal edges can get skewed. Clock signals could get slightly out of sync with data signals causing the wrong data to be accepted

158


Asynchronous Communications Interface What we require is a more robust transmission

standard (in terms of voltages, currents) which does not require a separate clock line

the term asynchronous means that we do not require a separate transmission clock

The RS232 standard defines a physical standard for voltage/current levels and is usually associated with asynchronous serial data transmission

159


RS232 standard - Physical Interface Logic level voltages are transformed to higher

magnitudes logic “1” is transformed to a voltage between -3V

and -15V and a logic “0” to a voltage between +3V and +15V. Many systems use +12 and -12V

higher voltages are more resistant to small amounts of noise voltage

Asynchronous comms

interface

RS232 driver and receiver

chips

Tx

Rx

RS232 line

levels

microcontroller

160


Asynchronous communications data The data format is shown below

1 or 2 start bits

6,7 or 8 data bits

0,1 or 2 stop bits

Odd or even parity bit

161


Asynchronous communications data The internal clocks at transmitter and receiver are

used for timing the transfer Both transmitter and receiver must have the same

baud rate - otherwise the transfer will be erroneous Both transmitter and receiver must have the same

Start, Stop, Parity and data-length configuration The baud rate generators will normally work at 16x

the frequency of transmission allows the internal peripheral logic to sample the

beginning of the start bit and therefore work out the middle of each bit time to sample all the other bits of the received data word

162


Asynchronous communications data The receiver resynchronises on each new character

received

Start bit Data bits Stop bit

Synch point

Sample points

163


Asynchronous communications data The receiver logic will filter out small amounts

of noise using sampling techniques for instance, a logic ‘1’ or ‘0’ will be recognised by a

majority voting system. The data-bit is sampled at the middle clock period

and also the periods immediately before and after.

Normally all the sampled bit data will be the same.

A small amount of noise may change one of the bit values but a 2 from 3 majority voting circuit chooses the bit value which occurs twice

164


Asynchronous communications data Majority voting eliminates noise until 2 bits of noise

occur at the middle of the data-bit time

Single data bit with no noise, data = ‘1’

Single data bit with a little noise, data = ‘1’ (majority voting)

Single data bit with a more noise, data = ‘0’ (majority voting) Data Corruption!

165


Other simple error detection mechanisms Parity - will detect only odd number of corrupt

bits

original 11001100 0 (even parity)

corrupted 11101100 0 even parity error

corrupted 11101110 0 no parity error!

Corrupted 11001101 1 no parity error! Block protocols - add sum checks as extra bytes

on a block of n characters sent over the line. Sum check calculated and sent by transmitter,

calculated by receiver and matched to original received - allowing detection of error (but not correction)

166


Asynchronous remote connections No clock required so various options possible..

Asynchronous comms

interface

Tx

RxAsynchronous

comms interface

Rx

TxWired RS232

Asynchronous comms

interface

Tx

RxAsynchronous

comms interface

Rx

Tx

IR link - no

wires

167


IR Communications Infra Red Transmitter

Modulator - 30KHz

Provides high peak light intensity but limits average power dissipated (good)

Infra red receiver

diode

Low pass filter

Data bit

Modulated data bit

168


IR problems IR communication is suitable where there is a

clear line of sight between transmitter and receiver. Problems include :

line of sight being temporarily obscured, blocking some of the data transmission

a protocol with bi-directional communication can allow transmitter and receiver to synchronise

high ambient light can be disruptive if it saturates the IR receiver

data transmission rates are relatively low

169


Radio transmission Radio transmitters and receivers

two different carrier frequencies can be used for bi-directional comms

Asynchronous comms

interface

Tx

RxAsynchronous

comms interface

Rx

Tx

radio links - no wires

170


Radio transmission Frequency modulation (FM) is one possible

technique logic ‘1’ and ‘0’ transmitted with different frequencies

based around a certain carrier frequency

Amplitude modulation (AM) is another carrier frequency stays the same but its amplitude is

modulated by whether the data is a ‘1’ or a ‘0’

171


Radio transmission Different power transmitters can be used for

various distances - low power transmitters do not require a license

line of sight not required - suitable for mounting inside equipment - perhaps the equipment needs to be portable

lowest power devices suitable for use within 20 metres of each other

other devices may be suitable for transmission over several miles

172


modems Modulator-demodulator allows the data bits to

be transformed into modulated audio waveforms, transmitted through some telecommunications medium and then demodulated and received as a data stream

Asynchronous comms

interface

Tx

RxAsynchronous

comms interface

Rx

TxStandard phone lines

modem modem

173


Modems and digital mobile phones Speed is currently limited to 9600 bits per second -

but will change over the next few years just like a normal modem connection to a Plain Old

Telephone Line (POTS) a mobile connection can provide web, email, file transfer, data-transfer, video-phone…...

Asynchronous comms

interface

Tx

RxAsynchronous

comms interface

Rx

Tx

Mobile phones

modem modem

174


Interfacing to the analogue world The real world is analogue in nature. In this

section we investigate the means of the computer interfacing with the analogue world

First we look at analogue to digital conversion an analogue signal is sampled at a regular interval each sample is divided or quantised by a given value

to determine the number of given units of value that approximate to the analogue value.

The number is the digital equivalent of the analogue signal magnitude

175


A/D Conversion

time

+3V

-3V

0V

Sampled Digital Values

Original Analogue Signal

176


A Closer look The conversion process suffers from errors

One of the most fundamental of these is quantisation error

the conversion process is step-based and consists of selecting one of a finite number of values

The analogue signal has an infinite range of values

The difference between the actual analogue value and the digital approximation is the quantisation error

177


Size4-bit8-bit16-bit32-bit

Resolution0.06250.00390.000015260.0000000002

Storage1Sec22050 bytes44100 bytes88200 bytes176.4 Kbytes

Storage60Secs1.323Kbytes1.98Mbyte5.29Mbye10.58Mbyte

Storage5min6.6Mbyte9.9Mbyte26.46Mbyte52.9 Mbytes

Quantisation

A larger digital representation provides smaller error, lower quantisation error and lower distortion, but more storage is required

Sampling at audio CD rate - 44.1KHz, Mono. Stereo takes twice the storage

178


Quantisation error

1

2

3Quantisation error

time

179


Sample rate and regularity The number of samples taken in a given time

period, normally measured in Hertz sampling rate determines the speed of converter

required - a 1mS conversion time will not provide a sample rate any higher than 1KHz

faster converters tend to be more expensive higher resolution converters are more expensive

The sampling rate determines the highest frequency that can be converted

Sampling must be performed on a regular basis with exactly the same time period between samples - irregularity (or jitter) causes distortion

180


Sample rate errors Late + early sampling

1

2

3

time

Erroneous value due to late sampling

Erroneous value due to early sampling

181


Sampling jitter

time

+3V

-3V

0V

Value sampled at correct time

Value sampled at wrong time

182


Phase error There will always be some phase error - this is

the cumulative delay through the conversion process

this may not matter as long as the data is recorded faithfully

however, in the context of real-time data-processing (especially real-time audio processing) such delays must be minimised

183


Phase error because of delay in sampling

Analogue value

Digital value

184


Sampling regularly

Counter - timer

CPU

Regular interrupt generation

SampleISRSampleISR()

{

newVal:= ReadADConverter()

call StartNewConversion()

}

High priority interrupt

Rate control is provided by a regular clock being used as an interrupt generator. If the processor has multi-level prioritised interrupts then a high priority interrupt level should be chosen.

185


Sample rate The number of samples taken in a given time

period, normally measured in Hertz sampling rate determines the speed of converter

required - a 1mS conversion time will not provide a sample rate any higher than 1KHz

faster converters tend to be more expensive higher resolution converters are more expensive

The sampling rate determines the highest frequency that can be converted

Sampling must be performed on a regular basis with exactly the same time period between samples

186


Nyquist’s Theorem Sample rate must be chosen to match the highest

frequency of the analogue signal being converted Nyquist’s theorem states that the minimum sampling rate

frequency must be twice the maximum frequency of the analogue signal.

A 4KHz digital signal needs to be sampled at twice (or greater) that frequency to convert it digitally

A hi-fi audio signal with a maximum frequency of 20kHz needs to be sampled at 40kHz or higher

When replayed, the analogue signal output from a DtoA converter will be put through an analogue filter to remove frequency components caused by the sampling frequency

187


Sampling and the frequency domain

Sampling points

Quantisation levels

Quantized signal stored

DtoALow Pass filter

188


Effect of sampling frequency on quantized signal

frequency

amplitude

f0time

amplitudeTime Domain

Frequency Domain

frequency

f0

amplitudefs = f0

Sample points

DC = zero frequency

189


Aliasing

frequency

f0

amplitudef0 < fs < 2f0

f’

This is called aliasing. A new frequency component f’ is generated which was not present originally. This is a result of the sampling frequency being too low.

190


Combating aliasing Aliasing can be a problem even if the correct

sampling frequency is chosen if the analogue signal to be sampled actually has

higher frequency components than expected then aliasing will occur

in practice a special low-pass filter called an anti-aliasing filter is used to remove frequency components above the maximum required frequency before sampling takes place

frequency

amplitude

f0

Filter Frequency response

A/DAnti-aliasing filter

191


Sampling at the 2f0 rate

frequencyf0

amplitudefs = 2f0

amplitude

Unwanted higher order harmonics

fs = 2f0

amplitude

Low Pass filter used to remove higher order harmonics

frequencyf0

3f0 5f0

192


Codecs We have looked at the A/D and D/A conversion process

A conversion system which includes both A/D and D/A conversion can be called a codec (coder decoder)

Usually a codec also includes some sort of software algorithm as well - very often for compression purposes, to minimise the storage required

Compression saves disk space or transmission bandwidth

A/D

Compression algorithm

Decompression algorithm

D/A

File

Transmission medium

or

193


Codecs Note - there are other types of codec for different

types of data streams - for instance a PC will have several codecs for audio and video compression and decompression

Frame Grabber



File

Transmission medium

or

Video camera

Graphics board

Video Codecs will be implemented in software or hardware and will transform the raw video data into a compressed for for storage or for transmission. A videoconferencing system will work like this - using a particular video codec.

software software

194


Codecs

Frame Grabber and compresser on one board



File

Transmission medium

or

Video camera

Graphics board including decompression hardware

The compressor could use a dedicated hardware chip(s) or use a fast DSP and compression software. Both approaches leave the main system processor free to perform other things.

195


Linear Codecs A linear codec is like the A/D and D/A devices described

previously the relationship between the analogue value and the digital

representation is linear

analogue

digital

Each quantisation interval is equal

Digital values change at the same rate as

analogue values

196


Non-linear Codecs For voice telecommunications applications where

bandwidth is limited, non-linear codecs are used to improve the audio quality whilst keeping the amount of bits down to a minimum

bandwidth in this context is the number of bits per second that can be sent across a communications line

If we analyse the amount of energy over the analogue voltage range then we find that most of the energy (and audio detail) is at the lower signal levels

197


Non-linear Codecs The human ear is more sensitive to the lower signal levels

non-linear codecs allocate more bits to the more important lower part of the signal - thus improving the overall audio resolution with the same number of bits

198


Non-linear Codecs Less bits are allocated to the higher analogue levels

although there is now coarser resolution at the higher levels, the human ear does not discern a reduction in quality

How are the bits allocated ?analogue

digital

Each quantisation interval is equal

Digital values change exponentially with

respect to analogue values

199


Non-linear Codec standards Two logarithmic codes commonly used are a-

law(UK standard) and -law(US standard) conversions between linear codes and the

logarithmic codes are easily done by look-up table

DSP chips often have the lookup tables built-in to internal ROM

200


D/A converter construction A typical D/A uses a binary weighed resistor

network depending which resistors are switched through to

the reference voltage source (Vref), then a set of currents flow into the summing amplifier

the summing amplifier acts like a current-to-voltage converter

an output voltage is produced proportional to the sum of the input currents

the binary input value controls the input currents the amplifier type used was originally developed

for analogue computers

201


Resistor ladder multiplying DAC - 4 bits shown

Vref

gndH LH L H L H L

R 2R 4R 8R

8I 2I4I I

8I + I = 9I

Analogue out = digital input * Vref

Analogue out = digital input * Vref

Analogue out = 9R * Vref

Analogue out = 9R * Vref

1 0 0 1latches

D0D1D2D3

Summing amplifier and voltage to current converter

202


DAC InterfaceVref

notWriteChip select

D-A

8-bit Data Bus

Vout

Address decoder

Read/notWrite

Processor

Address Bus

Data Bus

clock

203


Successive Approximation ADC

Vref

Analogue Input

DAC

Latch

Control Logic

Digital output

Usually 8,10,12,14,16-bit devices are used

204


Successive Approximation ADC Controller output is set to start at the middle of the

range (10002 for our 4-bit ADC example) comparator output is tested to see whether the DAC

output is higher or lower than the analogue input if it is higher then the count should be decreased if it is lower then the count should be increased

The method of increase and decrease is determined by a binary search algorithm

this algorithm provides a fast result - an n-bit word conversion takes only n clock cycles

205


Typical Signal Conditioning Chain

Sensor amplifier LPfilter sample/hold converter processor

R/notW

Data bus

chipSelect

startConv

Ready

Sensors : Temperature, position, displacement, humidity, velocity, acceleration, force, pressure, flow-rate, liquid-level, light-level, colour, acoustic, optical...

Must filter-out the noise and any frequency components not required

Must amplify the sensor voltage so that we make use of the whole range of the A/D, otherwise we do

not get the full A/D resolution

Must use Sample and Hold circuit to

steady the analogue signal

during the conversion time

tv

206


Power Control Most embedded designs are required to switch

power controlling ON/OFF style devices

LED pump heater lighting

continuous control of power variable speed/torque motors temperature control lighting intensitycontrol

207


Power Control Can use electromechanical or semiconductor

switches electromechanical

Relay device has a coil which is energised and forms an electromagnet which makes/breaks one or more set of contacts Relay power

‘1’ or ‘0’

amplifier

240V AC Live

240V AC Neutral

240V AC Pump, ON/OFF Control

208


Electromechanical relays - advantages Can be used to switch DC or AC power no electrical connection between the relay

coil/energising circuit and the relay contacts/power load that is being switched

therefore they naturally provide safety isolation between microprocessor control system and the device being powered

often used to switch high loads (high voltages and high currents)

easily understood by maintenance staff

209


Electromechanical relays - disadvantages Relay coil can generate a voltage when it is

switched off, due to stored energy in the coilRelay power

Off, so high resistance, not

conducting

I

Instantaneous potentially transistor damaging

voltage

Diode provides a conduction path when transistor is

switched off

I

210


Electromechanical relays - disadvantages Electromagnetic noise generated by switching

coil which can be picked-up by sensitive analogue circuits

switch contacts will degenerate over a period of time

switch bounce creates electromagnetic noise slow to switch (10’s of mSecs) relay cannot be driven from logic levels

211


Switching AC power Switching 240V AC at 10’s of Amps can create

high contact noise - depending on which part of the phase the switching takes place

High electromagnetic noise because

instantaneous rate of change is high

Perfect switching point

Worst switching point

212


Other switching devices Solid-state relay

contains electronics in a package which gives the functionality of a relay but totally semiconductor based

DC versions or AC versions available (these are different - one version cannot be used for both AC and DC)

AC version has a zero crossing circuit so that when the control-input demands the device to switch, it is actually switched at the next zero-crossing point - eliminating the switching noise

213


Other switching devices Power MOSFET

can be switched by logic level signals at the gate can switch high power low on-resistance means less power dissipation

inside the device

AC Solid state relay

5V 240V L 240V N

Pump

Parallel I/O port

Counter-Timer, set toRun in PWM mode

24V DC

Motor ON/OFF

Power MOSFET

gate

See Heath, pages156 - 159 for

a description of PWM timing

214


An H-Bridge circuit - motor static

gnd

Motor power

0 0

onon

Two bottom transistors ON, no current flow through motor

offoff

215


An H-Bridge circuit - motor static

gnd

Motor power

1 1

onon

Two top transistors ON, no current flow through motor

offoff

216


An H-Bridge circuit-motor rotating forwards

gnd

Motor power

1 0

offon

current flow through motor - motor goes in one direction

onoff

I

217


An H-Bridge circuit-motor rotating backwards

gnd

Motor power

10

off on

current flow through motor - motor goes in the other direction

on off

I

218


Digital Optical Isolation

R

Buffered Input

Opto-isolator - a single chip

Device

Processor ground

Input device ground

Allows transmission of a digital signal between an external device and a microprocessor system without having a physical Ground connection. This means that potentially damaging voltages and currents cannot find their way into the computer system from the external world. Also prevents noise voltages being picked-up and entering computer circuitry.

Digital Input Isolation

Processor

219


Digital Optical Isolation

R

output

Opto-isolator Processor ground

•Opto isolators can be used both for inputs and outputs.

Digital Output Isolation

Parallel I/O port

Processor

220


Analogue Isolation Used to provide isolation for analogue signals Also used in the following example situation

Analogue input voltage range 120V-125V Common Mode Voltage = (120 + 125) / 2 = 122.5V Voltage is too large to go into standard low-voltage electronic

circuits If we try to scale the whole voltage range down to a suitable small

voltage then the actual variation over the range will be minimal There is no suitable common ground connection between the

high-voltage signal and the conversion circuits What we are really interested in is the 5V of variation over the

whole range

221


Analogue isolation The following device is typically available as a

single package

120V “Common”

120V-125V Signal

Variable gain amplifier

Vsupply(isolated)

Modulator

Demodulator

Isolated Power Supply

0-5V

Modulator DemodulatorFilter

0V

Vout

Vsupply

0-5V

Referenced to 120V Referenced to 0V

222


Analogue isolation device construction We cannot connect the 120V common of the source

system to the 0V ground of the microprocessor system - so we must isolate the two parts

We isolate the two “grounds” The input amplifier must be powered but we cannot

do this with the microprocessor power supply because we would then be joining the grounds again

We must create a new “isolated power supply” whose ground is “floating” with respect to the microprocessor supply

This is done by a transformer based isolated-power supply system - at the lower part of the schematic

223


Analogue isolation device construction The source signal is taken through the amplifier and

amplified if necessary (if the signal variation is smaller than we require)

It is then sent through a modulator, sent through the isolation barrier and then through the demodulator to provide the original signal value

This time the signal value is referenced with respect to the microprocessor 0V rather than the original 120V in out example

Finally the signal is filtered to remove any modulation noise left from the demodulation circuits

224


Analogue isolation device construction There will be some error introduced with the

various stages present within the device There will be a limit to the highest frequency

variation that can be tolerated in the source signal because of the internal modulation process

The highest signal frequency will be specified in the device data sheet, as will the magnitudes or percentages relating to various internal errors

225


Interrupts - An introduction An interrupt is an event from either a processor

internal or an external source processor completes current machine instruction switches to a new instruction sequence completes this sequence returns to the original instructions

Interrupt service routine (ISR)

Main code

226


Interrupts Allows mainstream code to be de-coupled from

code which responds to events without the use of interrupts the mainstream code would

have to stop what it was doing and poll the peripheral devices to find out if there had been a change of state

unstructured - code lacks clarity because of extra tests embedded throughout main code

uses valuable CPU cycles when polling poor response time response time is related to how-often devices are

polled - this will change as mainstream code is modified - not recommended

227


Main code thread

Interrupt interaction in a simple system

Serial port

interrupt

processor

ISR reads serial-port data

ISR runs in response to

interrupt

ISR writes data to buffer area

and then increments

buffer pointer1

2

3

4

ISR

he Buffer pointer

Reading from a serial port with no OS support

228


Possible simple serial read functions BOOL CheckSerial()

returns True if there are any characters in the buffer INT GetSerial(myBuffer, byValue maxChars)

waits if there are no characters in buffer, polling until there is one or more chars available

gets chars(up to a maximum number of chars) and places them in myBuffer. The function return value indicates the number of characters read

INT ReadSerial(myBuffer, byValue maxChars) if no chars available returns -1 otherwise it gets chars in the same way as getSerial

OR ….INT GetSerial(myBuffer, byValue maxChars, timeoutPeriod) timeout period added for escape purposes

229


Interrupt interaction in a simple system Main code thread need only check to see if

data is available, then use the data data transfer to/from peripheral is much more efficient

since it takes place on demand data transfer is transparent to main code thread no device polling is necessary

However, this does not make the main code thread any more responsive to the peripheral data event. It just makes the system more efficient and improves the structure

A Real-time OS will improve things

230


Interrupt sources Internal interrupts

on-chip peripherals such as serial/parallel ports and counter-timer devices

External interrupts allow external peripheral devices to alert the

processor whenever they have a particular change of state

a network peripheral could alert the processor when a certain amount of data is in its internal buffer

an interrupt output pin on the peripheral would connect to an interrupt pin on the processor

231


Basic Interrupt Mechanism Interrupt is asserted by peripheral processor completes execution of the current

instruction processor saves PC, CCR and perhaps some other

registers into a stack area Processor identifies the interrupt vector associated

with the particular interrupt The interrupt vector holds the address of the ISR processor executes ISR ISR reaches an RTI (return form interrupt) instruction Processor replaces previous values from stack into

its registers - processing continues as previously

232


Basic Interrupt Mechanism for a Simple Microcontroller

Interrupt processing

timer

microcontroller

External interrupts

100AInterrupt

vectors are stored in memory

FFFE/F

16-bit address

FFFC/D

FFFA/B

12

3

FFF8/9

1AF0

1B02

1B80

Reset12

3

memory

ISR’s100A

1AF0

1B02

1B80

233


Basic Interrupt Mechanism for a Simple Microcontroller Note:

The reset-vector points at the address of the code which runs when the processor is powered-up or reset - this is often called the bootstrap code

There must be an RTI (return from interrupt instruction) or some other way of returning the processor to its original processing state

Any unused interrupts should point to a handler so that if they do unexpectedly get invoked, then some recovery action can take place

there must be sufficient stack space so that nested interrupts do not overrun the allotted space and corrupt other memory locations

234


Software for embedded systems We will now look at the type of software

development required for responsive real-time systems

A control-loop structure with no OS support Real-time operating systems

235


Program Structure First we will look at a simple control-loop structure.

This is built using several component parts : ISR’s (Interrupt Service Routines) allow

peripheral devices to alert the processor to certain conditions ( for example : ‘ready for data’, ‘new data arrived’ ) and have the processor execute the ISR code. This code will read data from peripheral chips and buffer it

Flags: Software variables which can be set and interrogated by ISR’s and main application code

Buffers : Areas for storing data to be written-to the peripheral chip or read from peripheral chip

236


Program Structure First we will look at a simple control-loop structure.

This is built using several component parts : ISR’s (Interrupt Service Routines) allow

peripheral devices to alert the processor to certain conditions ( for example : ‘ready for data’, ‘new data arrived’ ) and have the processor execute the ISR code. This code will read data from peripheral chips and buffer it

Flags: Software variables which can be set and interrogated by ISR’s and main application code

Buffers : Areas for storing data to be written-to the peripheral chip or read from peripheral chip

237


Check flags

and buffers

Check flags

and buffers

ISR’s

(Interrupt Service

Routines)

Data Buffers

Flags

Code

238


Program Structure : Control-loop Problems :

Lack of Prioritisation of activities System reaction time determined by where the

control loop is currently executing Extra tests have to be included in code to lower

reaction time Lack of structure and clarity Prioritisation is ad-hoc and difficult to validate

239


If (not timeoutCondition or StopPressed) and (rotationSpeed < LIMIT) then {

processRotationSensor();

processForceSensor();

if not commsReady() then

displayRotationSpeed()

else {

bufferComms() ;

displayRotationSpeed();

}

}

else if commsReady() then

………….

Program Structure : Control-loop

What do you

think about

this ?!

240


Program Structure : Control-loop The previous code module is composed of

disparate elements with no logical or physical connection to each other

in the last example, communication and speed sensing are not connected but the execution of these code elements is bound up inside the control loop structure

There is no way of allowing pre-emption - once a processing activity is started no other events can be considered until the processing is complete

241



Test and branch

Test and branch

A BC

Reaction time is extended

depending on the length of

code to be executed. The system

is unable to react to other events

until the current code module has

completed execution

242



Test for high-priority event and branch if

required

data processing for low-priority event ( part of

the code executed only)

check for high-priority event here to decide

what to do next

execute high-priority

code if required

High priority code

Remainder of data processing for low-

priority event

Reacting to high priority events by subdividing code

243


Program Structure : Control-loopForeground code module execution

Interrupt code

including high priority

data-processing Return to foreground

code module execution

Reacting to high priority events by extension of interrupt code

Interrupt from high priority device happens

244


Program Structure : Control-loop problems Problems with these solutions :

If code is subdivided then clarity is reduced, maintenance is more difficult and expensive. Re-use is difficult

prioritisation is still still difficult to implement if interrupt code is extended then the interrupts

themselves start to be queued the rule for interrupts is that they should be short,

fast pieces of code it is extremely difficult to follow the flow of control of

the program.

245


Program Structure : Control-loop problems There are problems in the use of variables accessed

both by the foreground-code and interrupt code no locking mechanisms available corruption possible

software development difficult and costly reliability problems hard to test maintenance expensive impossible to show code correctness under all

circumstances the synchronous structure of the loop is directly

opposed to the asynchronous nature of the real world

246


Program Structure : Control-loop advantages No run-time support software required

note : run-time support software includes OS’s, OS kernels and virtual-machine kernels (Java for example)

this lowers the cost ( but this saving may be insignificant on the product cost - in fact the extra cost in development/testing may make the overall cost much higher)

just need compiler, linker, debugger and perhaps an emulator for development time.

However, this solution applies only to the very simplest systems. A more structured approach is required for most real-time systems

247


Program Structure: a better solution….. Requirements

a software model which can deal with the multiplicity of concurrent activities present in the physical world

a model which can react to real-world asynchronous events as they happen

a well-defined and understood software model

A proposed solution use a process-based software model

processes allow us to perform a natural mapping of real-world activities to well-defined software constructs

248


Process-based model:benefits Processes can be constructed and execute as

independent software entities can be linked directly to the interrupt handlers in the

system so that events can directly synchronise with data-processing code

processes execute in an order determined by the events

processes can be transparently pre-empted by other higher-priority processes, therefore important activities can be processed, independent of what is currently being processed

activities which require more responsiveness can be allocated to higher priority processes

249


Process-based model:benefits a number of processes can be active “at the same

time” , even on a single processor system Processes provide high modularity and promote re-

use of code different physical activities have separate process

code force sensor data-processing process motion control process

processes only interact with each other when required

process interaction is via well-defined services easier to debug & maintain, therefore lowering costs

250


Concurrent Programming We wish to have a programming model which

matches the parallelism of the application domain

virtually all real-time systems are inherently concurrent

if the domain has motion-control, sensing, timing and user-controls then we wish to build a software model which can express these parts as separate entities but also allow structured interactions between the parts

251


Concurrency - Implementation Some languages ( such as C, Basic, Pascal,

Cobol) are examples of sequential programming languages

they have a single thread of control they start executing in some state and can follow

many paths through the program depending on input data and internal states

however, for any execution there will be a single path through the code

252


Concurrency - Implementation

Single threaded execution - one of many possible routes

through the code is shown - but only one thread of control is

spun during the execution of the program

branch

loop

253


Concurrency - Implementation

A single program with two threads of control - two concurrent processes are implemented in this example program

Process 1Process 1

Process 2Process 2

A Program with two

processes

A Program with two

processes

254


Concurrency - Implementation Concurrent Program :

a collection of autonomous sequential processes executing (logically) in parallel

on a single processor it is obvious that only one process will be executing at any one time

processes can be pre-empted and other processes restarted transparently through some scheduling mechanism

scheduling can be performed on a priority or time-sliced basis

Concurrent programming languages incorporate, implicitly or explicitly the notion of a process - each process has a single thread of control

255


Concurrency - Implementation Actual implementation could be :

processes multiplex their executions on a single processor

multiplex their executions on a multiprocessor system where there is access to shared memory for process interactions - true parallel process execution possible

multiplex their executions on several processors which are geographically isolated - this is known as a distributed system - true parallel process execution possible

256


Concurrency - Implementation The term concurrent indicates potential

parallelism the programmer can represent the notion of separate

logical activities without having to be concerned about the details of actual implementation

if a concurrent program is executed within a multiprocessor environment then some of the processes will execute in parallel

the programmer still has to be aware of response-times and deadlines

therefore, processes have to be organised in such a way that high-priority data-processing can occur when required

257


Concurrency - process life-cycle The life cycle of the process starts with….

creation initialisation execution (process running on the processor)

includes possible pre-emption (process is runnable but not running)

possible suspension ( process exists but can’t execute)

includes resumption (process is runnable again) termination - the process is gone forever

258


Concurrency - process life-cycle simplifiedNon

existentNon

existent

Created and initialised

Created and initialised

runnablerunnable

runningrunning

But it’s not this simple……...But it’s not this simple……...

259


Process Life Cycle - more detail required...

runnablerunnable

runningrunning

What else can happen to the process when it is executing ?What else can happen to the process when it is executing ?

????

260


Process Transitions: Pre-emptionrunnablerunnable

runningrunning

A process will be pre-empted by another higher priority process becoming ready to run or because of round-robin (or other) scheduling

A process will be pre-empted by another higher priority process becoming ready to run or because of round-robin (or other) scheduling

time

261


Process Transitions: Suspensionrunnablerunnable

runningrunning

suspendedsuspended

A process is suspended so that it no longer can be run. It can later be unsuspended and will be runnable again.

A process is suspended so that it no longer can be run. It can later be unsuspended and will be runnable again.

262


Process Transitions: Blocking (Pending)runnablerunnable

runningrunning

Blocked (pended)Blocked (pended)

A process blocks itself. It requests a resource (semaphore, message, hardware device, etc) which is not currently available or ready

A process blocks itself. It requests a resource (semaphore, message, hardware device, etc) which is not currently available or ready

263


Process Transitions: Blocking (Pending)runnablerunnable

runningrunning

Blocked (pended)Blocked (pended)

The unblocked process makes a transition to the runnable state. This may be because a message or semaphore becomes available, device becomes ready, etc..

The unblocked process makes a transition to the runnable state. This may be because a message or semaphore becomes available, device becomes ready, etc..

264


Process Transitions: Termination

runnablerunnable

runningrunning

TerminatedTerminated

A process is Terminated so that it no longer exists. There is no way back…...A process is Terminated so that it no longer exists. There is no way back…...

265


Process Execution : the challenge Execution of a concurrent program is more

complicated than a sequential program Processes must be created, scheduled, and be able

to synchronise & communicate with other processes Processes must be able to share resources safely

shared data structures (data pools) hardware devices

Processes must be able to be synchronised with interrupt service routines

266


Process Execution: support What is required is a Run Time Support System

or Real-Time-Kernel The RTSS has many of the properties of the

Scheduler in a conventional Operating System It also includes many other useful run-time

facilities It forms (from the perspective of the programmer) a

Real Time Virtual Machine This provides to the programmer with a higher

level, more abstract ( and more powerful) machine to work with ……….

267


Without the RTSS : Compiling for a Bare processor

Target System: processor and peripheral hardware

Application Program uses : Language-supplied and programmer-built abstractions and development Library

abstractions. Basic data-types, lists, queues, buffers, other abstract data-types, I/O device driver library (customised for particular peripheral devices used on the processor board)

……...

Program compiled and linked for the

particular target system

268


With the RTSS : Utilising the Real Time Virtual Machine Layer


Application Program uses all the abstractions detailed on the last slide PLUS a new set of real-time multi-processing

abstractions provided by the RTSS



RTSS provides a completely new set of abstractions for the programmer to use: scheduled processes with prioritisation or

timeslicing, messaging, timers, communication, synchronisation, watchdogs and I/O device drivers. Implemented as a software

library (in RAM or PROM) for the particular processor or possibly as microcode inside a processor

Real-Time Virtual

Machine Layer

Real-Time Virtual

Machine Layer

269


So what’s the difference between this and a normal OS layer ?


Application Program uses all the abstractions provided by the programming language, the programmer and the OS



OS layer provides multi-processes, communication, synchronisation, timers, mutual-exclusion, I/O drivers etc……

But not with the guaranteed execution and response times, process prioritisation, controllability and

specialist features offered by the RTSS

Here’s the difference !

Here’s the difference !

270


Concurrent Programming choices for the programmer Use a concurrent programming language where

the programmer implements some of the synchronisation code using language facilities ( e.g. Modula-2)

Use a concurrent programming language whose library’s include its own RTSS code (many versions of the Ada language do this)

Use a processor which has the RTSS implemented in microcode inside the processor

271


Concurrent Programming choices for the programmerUse a language such as C which does not

include concurrency within the language definition or syntax.

Use this together with a RTSS so all the multi-process and other facilities are made available to the programmer via library calls.

Now we have an efficient high-level implementation language with real-time features (for example VxWorks or pSOS real-time kernels)

272


Concurrent Programming choices for the programmerUse a concurrent language like Java where

the Run-Time-Support-System exists as an interpreter for the intermediate code generated by the compiler. The compiled Java code is therefore made very portable and can be run on any computer system which has an interpreter.

273


Concurrent Programming choices for the programmerAll operating systems (whether real-time or

not) provide multi-process facilities in a standard OS usually each process works in

isolation from others with its own Virtual-Memory space, avoiding interference with other unrelated processes - each process is, in effect a single program

recently, some OS’s and languages allow the programmer to create processes within a program. These processes are often called threads and they have access to the shared memory space of the program.

274


Where should concurrency support be provided? In the language ?

Leads to more maintainable and readable programs greater portability an embedded computer may not have an OS compiler can provide comprehensive checking of the

interactions between processes

In a RTSS ? It may be difficult to implement a language’s model of

concurrency efficiently so for instance C/VxWorks Real-Time OS route would be much more efficient

OS standards are emerging now to allow program portability between different machines

275


Concurrent Programming Constructs Fundamental facilities required :

expression of concurrency through the notion of a process

process synchronisation interprocess communication mutual exclusion

Process behaviour : independent co-operating competing

276


Independent Processes Do not communicate or synchronise with each

other

Process in runnable state

shown with solid line

277


Co-operating Processes Will communicate or synchronise with each

other. Example …..

Process B Blocked waiting

on Sync

Process A sends Sync

Process B is now runnable

278


Competing Processes All processes may compete for processor time at some point. Consider

a single processor implementation of the scenario below when from time tn till tn+1 both processes become runnable...

tn

ttn+1

Wait for Synch so cannot execute

Synch arrives

Wait for Synch again

279


Competing Processes They can’t both use the processor at the same time !

Solution 1: Time-sliced implementation with equal time slots for both processes during the time they both need to run concurrently…..

t

Process-A Process-B Process-A Process-B

Is this a good solution in a real-time context ? What problems could there be with this solution ?

Is this a good solution in a real-time context ? What problems could there be with this solution ?

CPU Utilisation over timeCPU Utilisation over timetn till tn+1

tn tn+1

Wait for Synch again

280


Competing Processes They can’t both use the processor at the same time !

Solution 2: Use a priority based scheme for scheduling the processes that wish to run at the same time

t

Process-A

Process-B

Process-A

CPU Utilisation over timeCPU Utilisation over time

Process Priority

Wait for Sync again so blocks itself and lets Process-A execute

Process B receives a sync and is given use

of the processor

Process A is pre-empted

281


Process Representation:Explicit Process declaration

The structure of a concurrent program can be made much clearer if the routines themselves indicate that they will be executed concurrently

Here is an Ada example. First, we create a task type:

with Ada.Strings.Unbounded; use Ada.Strings.Unbounded;

package Babble is

task type Babbler is entry Start(Message : Unbounded_String; Count : Natural); end Babbler;

end Babble;

282


with Ustrings; use Ustrings;

package body Babble is

task body Babbler is Babble : Unbounded_String; Maximum_Count : Natural; begin accept Start(Message : Unbounded_String; Count : Natural) do Babble := Message; -- Copy the rendezvous data to Maximum_Count := Count; -- local variables. end Start; for I in 1 .. Maximum_Count loop Put_Line(Babble); delay 1.0; -- Wait for one second. end loop; -- We're done, exit task. end Babbler;

end Babble;

Next we have the task declaration and task body

283


with Babble, Ustrings;use Babble, Ustrings; procedure Noise is Babble_1 : Babbler; -- Create a task. Babble_2 : Babbler; -- Create another task.begin -- At this point we have two active tasks, but both of them -- are waiting for a "Start" message. So, send them a Start. Babble_1.Start(U("Hi, I'm Babble_1"), 10); Babble_2.Start(U("And I'm Babble_2"), 6);end Noise;

Now the creation of two tasks and their initialisation:

The output from this program is an interleaved set of messages on the display.

284


Communication and Synchronisation Major difficulties in real-time programming arise

from process interaction correct behaviour is dependent on two aspects:

synchronisation the satisfaction of constraints on the interleaving of

the actions of different processes - for example one process can only perform a particular action once another process has performed a certain activity.

Also refers to two processes simultaneously reaching predefined states.

285


Communication and Synchronisation Communication

passing of information from one process to another some forms of communication include synchronisation

data communication usually based upon shared variables or message passing

shared variables are objects that more than one process can gain access to. Communication can proceed by processes referencing these variables when required. Semaphores are classed as a shared variable construct

message passing involves the explicit exchange of data between processes by means of a message that passes from one to the other via some agency

286


Using Semaphores - Condition Synchronisation Semaphores allow the implementation of condition

synchronisation and critical sections. condition synchronisation :sem condSynchronise; /* initially 0 */

Process_A() Process_B()

{............ { ...............

............ Signal(condSynchronise);

wait (condSynchronise); ............

............ }

}

If process_A executes its wait first it will be delayed until process_B has executed the signal operation. If process_B executes its signal first, then when process_A executes a wait it will pass through immediately.

287


Using Semaphores - Mutual Exclusion Mutual exclusion requires the bracketing of the critical

section with a wait & signal pair as follows :

sem mutual_exclusion; /* must initialise this to 1 */

process_A() Process_B()

{ do { ........ { do {........

wait (mutual_exclusion_sem); wait (mutual_exclusion_sem);

<execute critical section > <execute critical section>

signal(mutual_exclusion_sem); signal (mutual_exclusion_sem);

............ ........

} FOREVER } FOREVER

}

288


Mutual Exclusion Here, only one process can gain access to its critical

section. This structure obviously only makes sense when the relevant processes are manipulating mutually shared objects within the system.

A collection of critical sections (1 or more ) is known as a class. Each class of critical section will require a separate semaphore for protection of that class.

The wait (sem ) operation cannot be completed if one of the critical sections in class sem has already been entered.

289


Hiding the complexity In keeping with best practice, a good programmer

will hide the detail of the operation by creating higher levels of abstraction

So instead of embedding operations within the main task code

--------- /* task code */

getSem(displaySem);

setCursor(a,b);

displayString(“test”); /* out to display */

putSem(displaySem);

-----------

290


Higher levels of abstraction--------- /* task code */

writeToDisplay(a,b, “test”)

---------

void writeToDisplay(int x, int y, char * displayText)

{

getSem(displaySem);

setCursor(x,y);

printString(displayText)

putSem(displaySem);

}

291


Sharing the resource between tasks

----

writeToDisplay(a,b, “ ;) ” )

----

----

writeToDisplay(a,b, “ ;) ” )

----

TaskA

----

writeToDisplay(m,n, “ :( ” )

----

----

writeToDisplay(m,n, “ :( ” )

----

Taskb

The resource is shared safely and the detail is hidden

292


Process Blocking Within the discussion of the busy-wait framework it

was shown that there is great inefficiency in allowing a process to remain in a state where it has to regularly poll a set of flags, whilst waiting for permission to continue.

A more efficient method is to remove the calling process from the list of runnable processes whilst the wait condition is unfulfilled. The new state will be known as the blocked state ( sometimes known as suspended).

293


Process Blocking When a process_M executes a wait on sem_x this is

channelled to the support system....... The value of the semaphore is checked and if it is 0 then the

process effectively blocks itself. It is placed on a queue of blocked processes.

The support system scheduler will then select and dispatch another process_N using the various scheduling criteria being used.

294


Process Blocking Eventually, another process should execute a signal

operation on sem_x. The kernel call will allow the scheduler to be invoked

and the blocked-process list will be scanned to find a process blocked on this particular semaphore.

The particular process chosen will return to the ready to run state again and be eligible to execute.

The criteria for choosing the actual process to be run (if there are several possible processes blocked on the same semaphore) will depend on the scheduler characteristics but will include process priority .

295


Messages within a real-time OS These allow a task (or ISR) to communicate and

synchronise with another task Allows separate but cooperating tasks to interact

and pass data to each other provides both synchronisation and communication in

one primitive

Messaging includes built-in queuing messages can be variable length A task will wait if there is no message available

optional timeout is available so a task can become unblocked after a period of time if the message call is not satisfied

296


Messaging examples

QQ

QTask

Task

Task

send

receive

One-To-One or Many-To-One

297


Co-ordinator Task

Display Control Task

Speed Control Task

Using messaging to synchronise and communicate within an application

stopstart + _

Key ISR Keypad

decoder

interrupt

read

writebuffer

Blocking ReadQ

Q

currenthistory brightness

Speed Control

Display Control

Speed Control messages

QQ

Display Control messages

semaphore

One-To-Many

motor

See Device-drivers section

later

See Device-drivers section

later

298


Commentary… Note the use of the blocking read operation to

allow the calling task to block itself until data is ready

the ISR reads the data from the peripheral device(keypad decoder in this example), buffers the data and then calls a semPut operation to make the semaphore available to free a calling task

A task calling a read operation will block if there is no data available. If there is data available in the buffer the data will be returned and no blocking will take place

299


Commentary… The co-ordinator task reads the key-press data

and then sends messages to the individual tasks which take care of system functions

messages provide both : synchronisation - tasks can block waiting for

messages and will be unblocked when a message appears

communication - messages pass data between tasks

these tasks will be prioritised according to their importance and their deadlines

300


Keypad TaskKeypadTask

{

do forever {

read(keypad, myBuffer, 1) /* blocking read */

case (keyPadCode){

start,stop,plus, minus :

sendmessage(MotionQ, keyPadCode, sizeOfMessage)

-- Do any other stuff

history, current, brightnesss :

sendmessage(DisplayQ, keyPadCode)

-- Do any other stuff

}

}

}

301


Motion Control TaskMotionControlTask

{

do forever {

--block until message

readMessage(MotionQ,theMessage,wait,forever)

case(theMessage) {

----

- do motion stuff

}

}

}

302


Client-Server Model

QQ

QTask

Task

Task

Send request

Receive requests resource

taskID RequestCode Parameters returnQID

Format of request message

QQ

Q

Send any return values

receive

303


Timeout example In a multitasking application, Process-A receives

a data item from Process-B on a regular basis. If a period of 10-seconds elapses without

Process-A receiving new data from B then an alarm task should execute to the exclusion of all other tasks..

304


Proc_A()

{

---

if (get_message(mailboxA,theMessage, 10_SEC_TIMEOUT_PERIOD)

and TIMEOUT)

then sendMessage(alarmMailbox,ALARM_MESSAGE)

else

OK……………………

}

/* AlarmProcess is highest priority process */

AlarmProcess()

{

---

theMessage=get_message(alarmMailbox,theMessage NO_TIMEOUT_PERIOD)

case (theMessage) :

…..

}

305


Device drivers An OS device driver is a set of functions/ISR’s

written to the particular OS standard and designed to provide a level of abstraction between a standard I/O call within the OS and the underlying hardware-dependent I/O code

typical functions which have to be provided: read, write, initialise, get_status, open, close, create,

remove the code for these deals with specific hardware

registers at specific memory addresses

ISR’s are used to allow peripherals to indicate events (data-ready, ready for new data, etc)

306


Device driver call

User Program level: Write(deviceX , data)

SerialPortWrite (deviceX, data)

Function call to actual driver function which is found by looking up a table to find-out what

type of device it is

Serial Port X

Hardware specific code for serial port

307


ISR and semaphore use

Key ISR Hardware

device

interrupt

write

Driver buffer area

thisDeviceSem

Read data

ReadSerialPort(portY, userBufferArea)If data Available in Driver Buffer then

read the data into usrBufferArea

else

getSem(thisDeviceSem)

read the data into usrBufferArea

Serial Port Y

308


Timer functions within a real-time OS The Posix portable real-time OS standard

implements timer functions a number of virtual clocks(timers) can be created these are based on the OS system clock tick ISR once created and armed, these timers can be made

to: signal a task some time in the future (single-shot

mode) repeatedly signal a task(repetitive mode) at some

rate

309


Posix Clocks make use of Signals Signals are a common feature in many

operating systems Any task or ISR can signal another task The signalled task immediately stops its current

thread of execution and jumps to a signal handler function

a signal handler function executes even if its task is blocked

signals are a fast and efficient way of asynchronously invoking code with very low overhead - the currently executing task does not need to be pre-empted

310


A repetitive timer

createTimer(a, --,--,-,-)

connectTimer(a, handler)

1

task

Signal handler function

timer

signals

--- --- --- --- t

signals

OS real-time Clock

311


Timer usage Timers can be used for

regular sampling regular control one-off delays a series of delays of different sizes etc...

312


Posix timer calls/* create a new timer and pass its ID back in *//* the variable: timerid */timer_create(CLOCK_REALTIME, NULL, &timerid)

/* when a timer fires it will send a signal *//* which will then invoke the function: timerRoutine*//* the optionalParam is a parameter value sent *//* to the handler function when it is invoked */ timer_connect(timerid, timerRoutine, optionalParam)

/* a task will arm the timer to GO mode *//* by calling this function */timer_settime(timerid, flags,&value,NULL)

/* subsequently, at each timer expiry the handler *//* function (timerRoutine) will execute, even if the*//* task that set up the timer is blocked */

313


Watchdog timers Allows the creation and triggering of a simple

timer and allows execution of a related handler function at the end of the stated time period

It’s called a watchdog because it is very often used as a secure way of alerting the system of the fact that a particular piece of code has not executed by a certain tiem

With this type of usage the watchdog is a software recovery mechanism

314


Watchdog timerscreateWatchdog(a)

watchDogStart(a, tenSeconds,handlerFunction)

/* now perform application activities */

/* which must complete within 10 seconds */

/* elapsed time */

-------

---

------------

/* normally the code would be complete by this time */

/* so the watchdog timer is cancelled */

cancelWatchdog(a)

If the code over-runs its allotted time then the watchdog timer expires and the handler function is invoked to take whatever action is required.

The watchdog allows the system to recover and take appropriate action

315


Hardware watchdog timers The scheme discussed is only as good as the

current state of the processor If the processor has crashed then this software

scheme will not work, so there will be no recovery this is not appropriate for systems which need to be

reliable and provide total recovery If we need total reliability then a separate hardware

watchdog scheme is required the Motorola HC11 series of processor include a

built-in hardware watchdog system which is typical of the high-reliability requirement; it is called the COP watchdog (Computer Operating Properly)…...

316


Hardware watchdog A hardware counter is available It can be reset to its maximum value It counts down at a certain rate (several rates are

available to allow different timeout periods) A sequence of bytes with certain values is written

to certain register locations in the microcontroller to reset the watchdog

the reason for the sequence is that if the program crashes and starts to perform arbitrary writes to locations then there is a very low probability that the correct reset byte sequence will be generated to write to the specific reset address

317


Hardware watchdog As long as the program resets the watchdog

regularly, in normal usage, then the watchdog will not time-out

If the watchdog times-out it is arranged that the processor gets reset and therefore the application can recover by use of appropriate software

Even if the processor crashes this scheme will work because it is based on separate hardware - not the CPU hardware

318


Hardware watchdog Even if a CPU does not have such a scheme, it

could be facilitated by some simple external hardware, connected to the reset pin of the processor

On a reset, the program could interrogate the external hardware through a buffer to see if the reset had been caused by the watchdog

319


Scheduling in real-time applications priority-based pre-emptive scheduling:

All processes can be allocated priorities according to their importance in an application. If a process wishes to be activated (i.e. it makes a transition to its ready state) and it has a higher priority than the process already running, then the current process will be forced to the ready state so that this higher priority process may proceed.....

This scheme guarantees that the highest priority process in the system can always run and meet its deadline ( assuming the processor together with the process-switching algorithm are fast enough to allow the meeting of the deadline).

320


Priority based pre-emptive strategies For example, if a lower-level process is running and a

device interrupts, it may lead to a blocked higher-priority process being unblocked and made runnable, pre-empting the currently running process

However, it can be difficult to choose the correct priority for processes

what at first may seem a reasonable set of priorities may not match the deadlines imposed by the application………….

321


Priority based pre-emptive strategies example

a set of two timed periodic processes:P1 has highest priority because it is the most

important.

P1 50 10 units 20%

P2 10 2 units 20%

execution requireme

ntprocess period

CPU utilisation

P1 needs 10 units of execution time every 50 units. P2 needs 2 units of execution time every 10 units.

If both processes start at the same time then P1 runs for 10 units of execution to meet its deadline. It will then block itself for a further 40 time units. However, by this time P2 cannot meet its first deadline, because the first 10-unit time period has expired and it has not had a chance to run during this period.

322


The rate-monotonic approach for periodic processes Rather than assigning a priority according to

process importance, priority is assigned to a process according to its period

the shorter the period, the higher the process priority.

The scheme still uses pre-emptive scheduling If we review the example above, using the rate monotonic

approach, P2 receives the highest priority because it has the lowest period. Therefore the execution follows the pattern below:

P1 oooooooo oo P2 oo oo oo t

323


An application has three tasks. They all execute regularly and have the requirements listed below:Task Name Task Period Execution Time Required

Task 1 200mS 50mSTask 2 20mS 4mSTask 3 10mS 1mSThe only deadline requirement is that the tasks guarantee to execute within the time frame shown above. There is no external synchronisation activityThe overall task utilisation as a percentage of total CPU time =25% + 20% + 10% = 55% (+ overheads for task switching etc).

Rate-monotonic allocates priority according to period to ensure that more frequently executing tasks meet their deadlines. Smallest period gets highest priority. So tasks in priority order, from highest: Task3, Task2, Task1

324


Rate Monotonic Scheduling

0 50 100 150 200 250

Task 3, Highest priority

Task 2, Medium priority

Task 1, Lowest priority

325


What about the asynchronous activity? With rate-monotonic scheduling(which is based on

scheduling periodic processes) the asynchronous activity have to be modelled as code which runs at a specific rate

for instance to model the asynchronous data from a serial-port we must budget for the time consumed by every interrupt call generated by the port

we have to do this for the highest data rate that is possible from the port - just to ensure that at times of high loading that all the programs can be scheduled

this worst-case technique is also to calculate a budget for any asynchronous tasks in the system

326


Is this theoretical analysis valid? probably not completely accurate it can be difficult to accurately benchmark task execution times

under all conditions (branches, loops etc cause variable execution times)

most real designs try to work to a utilisation of 75% or less - just to ensure that there are spare CPU cycles

other problems include the difficulty of analysing the effect of inter-task

comms/synchronisation the effect of caching on program execution times

327


Process Control We will look at how a computer can be used as

part of a feedback control system This example is based on a temperature

control system using a heater (heater current controls heater power) and a temperature sensor as feedback

Oven

Computer control system

Oven Power Oven current control

Temperature sensor

Control signal

0 - 100% power

or

PWM V

t

Control signal is PWM or a voltage proportional to the power required Requested

temperature (the set-point)

Temperature feedback

328


Process Control: Open Loop If the temperature of the oven was only affected by the

input from the heater element and known convection losses through radiation, convection and conduction, the control problem would be very simple

Experimentation could determine how much current should be sent to the heater to maintain the required temperature

all the control system would have to do is to switch on that amount of current

a start-up routine would be determined by experiment to quickly reach the desired temperature

No feedback control would be required - this is open-loop control

329


Process Control Most real situations do not match the ideal. There are

uncontrolled variables such as: the ambient temperature (outside the oven) the contents of the oven may vary

We need to be able to monitor the temperature and make adjustments to allow better temperature stability under all conditions

we make use of the temperature feedback in a closed-loop control system

the difference between the value read-in from the sensor and the set-point (the chosen temperature) is called the error

if the demanded temperature is 200OC and the sensor says the temp is 215OC then the error is +15OC

330


Control choices There are various control strategies:

On/Off control Proportional control Integral Derivative

We will look at each in turn and investigate how they can interact with each other

331


On/Off control When there is an error the response is to provide full-

power to restore the system to the set-point suppose the temperature control system can only turn the

heater element fully on or off the demanded set-point is 200OC if the temperature is lower than this the heater is turned

fully on if the temperature is higher than this the heater is

switched-off A scheme like this will be unsuitable

each small decrease in temperature will bring the full power of the heater and there would be large temperature swings

332


On/Off control A slightly better method is to leave a deadband

across which no action takes place in our example no change of control occurs if,

say, the temperature is between 190OC and 210OC, assuming the application can tolerate such a range of values

if the rate of cooling is constant then we will get a sawtooth as shown below

OC

time

190

210

deadband

333


Proportional Control For systems which require finer control, other

methods are employed Integral control feeds back to the input not just full-

on and full-off values but intermediate values proportional to the error signal

error = setPoint - actual temperature

The further away the temperature from the set-point, the higher the power supplied to the heater

heaterCurrent = kp x (setPoint - measured temperature)

where kp is a constant of proportionality determined by

theory or experiment. This value is often adjusted when a system is set up.

334


Proportional Control The system can be represented graphically

0% Output

100% Output

Temperature Set-point

Proportioning band

Too hotToo cold

The proportioning Band is the area around the set-point where the controller is actually controlling the process; The output is at some level other than 100% or 0%.

Max temperaturemin

335


Proportional Control The larger the value of kp the narrower the

proportional band will be and the faster the response to any given error

the problem with narrowing the band is that the controlled system may overshoot because it is oversensitive to changes

the problem with lowering kp too much is that

the system can become sluggish and take too long to respond to a given error

336


Proportional ControlOC

200

OC

200

Overshoot with

excessive gain applied

undershoot with low gain

applied

time

time

337


Proportional Control redefined Because there is steady loss of temperature

because of the factors listed earlier, real systems do not usually use a 0% control factor at the set-point

Instead, an additional constant value is added to the formula - this value is sometimes known as the manual reset or offset value - again, this can be tuned for best performance. The formula now includes an extra factor, C which is the offset value: heaterCurrent = kp x (setPoint - measured temperature) + C

338


The new framework The effect of this constant is to give the following

framework, where the proportioning band has shifted. In this example a 30% (because of heat losses) output level maintains the temperature at set point:

0% Output

100% Output

Temperature Set-point

Proportioning band

Too hotToo cold Max temperaturemin

In this example, 30% output can maintain the temperature

near the set-point

339


Integral Feedback (automatic reset) Corrects for any offset (between set-point and

process variable) automatically over time by shifting the proportioning band.

Aims to automatically increase the quality of control so that controlled system can sit nearer its set-point

It does this by looking back in time at the system behaviour

it calculates the integral of the error over time and uses this to shift the proportioning band

It is used to improve proportional control - it is not used by itself

In our examples the process variable is temperature

340


Integral Feedback (automatic reset) Temperature history:

Integrate over the

last n seconds

The integral value calculated from the temperature history over the last n

seconds is used to shift the proportioning band to give a greater or

lesser output depending on recent history. It can lead to better stability

near the set-point

temperature

time

341


Integral control effect….

min Max temperature

32OC842OC

0%100%

Proportioning band359OC 441OC

50%

SP400OC

• 10% proportional band (10% of the entire span of 32 to 842OC)

• setpoint is 400OC

• manual reset originally has been tuned to put the output at 50% power to maintain the temperature

Current oven temperature

342


min Max temperature

32OC842OC

0%100%


50%

SP400OC

Temp

time

400Integral over the last n seconds

• The band has been shifted to allow faster closing of the loop by allocating a larger output value for any given error. It has been shifted because of the value of the integrated error

Set-point

Last n secs

343


min Max temperature

32OC842OC

0%100%


50%

SP400OC

Temp

time

400

Last n secs • Getting closer to the set point

• the integral value still has an effect but this time the integral is smaller and the shift is smaller

344


min Max temperature

32OC842OC

0%100%


50%

SP400OC

Temp

time

400

Last n secs• Getting to the set point and then

overshooting

345


min Max temperature

32OC842OC

0%100%


50%

SP400OC

Temp

time

400

Last n secs

• Integral controller stops moving the proportioning band as soon as the setpoint and PV are equal. In the above example the Integral Controller determined that approximately 38% output is required to maintain setpoint. Stable control is achieved and the temperature matches the setpoint of 400.

346


Derivative control(rate control) Shifts the proportioning band on a slope change of

the process variable (in our case the process-variable being controlled is temperature).

Rate in effect applies the "brakes" in an attempt to prevent overshoot (or undershoot) on process upsets or at start-up.

Derivative controller calculates the rate of change of controlled variable over the last period of time

this value is used to shift the proportioning band to try to minimise the effect of high rate of change

347


Derivative control(rate control) A high rate of change leads to a shift in the

proportioning band to lower the output control level

otherwise we may get overshoot or undershoot near the set-point

Derivative can be used with proportional control giving PD control, or used with PI to give PID

It cannot be used on its own because a constant(non-fluctuating) error would have a derivative value of zero which would not allow a new control value to be set

348


Derivative control(rate control)

setpoint

Derivative control will be applied more when there is a high rate of change. It attempts to damp the effect of the existing control

output value by shifting the proportional band so that the

output is decreased

349


Common combinations Proportional control (P) Proportional-Integral(PI) Proportional-Derivative(PD) Proportional-Integral-Derivative(PID) The controller will output a final value which is

derived from the combination of the various parts For instance, at a certain point an integral controller

could indicate an increase in the output power but the derivative controller term may then decrease the value slightly if the rate of change is high which might cause an overshoot.

embedded systems design

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