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Abdulrahman Mahmoud
Bio: Abdulrahman is a doctoral candidate in the Computer Science department at UIUC. His
research interests lie broadly in the areas of computer architecture, systems, and reliability.
Abdulrahman's dissertation work seeks to address the role hardware errors play on an
application's error tolerance by designing tools and techniques to understand how hardware errors
propagate and affect the software. Abdulrahman's research has been published in the top
computer architecture and dependability conferences (MICRO, ASPLOS, SC, DSN). Abdulrahman
is the recipient of many awards during his graduate studies, including a Mavis Future Faculty
Fellowship, the Lynn Conway Research award for best technical demonstration, an invitation to
the 7th Heidelberg Laureate Forum, and multiple awards for teaching and mentoring
undergraduate students. Prior to joining UIUC, Abdulrahman completed his BSE from Princeton
University, where he was the recipient of the John Ogden Bigelow Jr. Prize in Electrical
Engineering.
Interested positions: Academic Research, Industry Research, Postdoc Research interests: System Architecture; Systems ML; Approximate Computing; Reliability
Email: [email protected]
Website: http://amahmou2.web.engr.illinois.edu/
Aporva Amarnath
Bio: Aporva Amarnath is a Ph.D. candidate at the University of Michigan. She is a part of the
Circuits and Architecture Design Research (CADRe) group, advised by Prof. Ronald Dreslinski.
Her dissertation research aims to build efficient computer architectures and systems for emerging
non-Si technologies by developing solutions across the compute stack. Aporva’s research work
has been published in top computer architecture and EDA conferences (ISLPED, HPCA, DAC).
Aporva has also completed three summer internships at AMD Research and IBM Research.
Honors/Awards:
• My work was nominated for the best paper award at ISLPED 2017
Interested Positions: Industry Research, Postdoc Research interests: Computer Architecture, Emerging Technologies, Memory Systems
Email: [email protected] Website: https://web.eecs.umich.edu/~aporvaa
Chao Zhang
Bio: Chao Zhang is currently a fifth-year Ph.D. student in the Department of Electrical and
Computer Engineering at Lehigh University and expected to graduate in May 2021. He received
his B.S degree in Electronic Science and Technology from the University of Electronic Science
and Technology of China in 2016. His research interests include energy-efficient computer
architectures, non-volatile memories, and domain-specific architectures.
Honors/Awards:
• Rossin Doctoral Fellowship
Interested Positions: Industry Research, Industry
Product, Postdoc
Research interests: Memory systems,
Processing-in-memory, Computer architecture
Email: [email protected]
Website: https://www.lehigh.edu/~chz616/
Hossein Golestani
Bio: Hossein Golestani is currently working towards the PhD degree in computer science and
engineering at the University of Michigan, where he works with Prof. Thomas F. Wenisch. His
current area of research is computer architecture, with particular emphasis on data plane design
in datacenter systems and also performance modeling.
Honors/Awards:
• Best paper award in ISPASS 2019
Interested Positions: Industry Research, Industry
Product, Postdoc
Research interests: Computer Architecture,
Datacenter Systems, Bottleneck Analysis
Email: [email protected]
Website: https://www.linkedin.com/in/hossein-golestani-193003127/
Joanna Cecilia da Silva Santos
Bio: Joanna C. S. Santos is a Ph.D. student in Computing and Information Sciences at Rochester
Institute of Technology (RIT). She has an M.Sc. in Software Engineering from Rochester Institute
of Technology (RIT, USA) and a B.Sc. in Computer Engineering from Federal University of Sergipe
(UFS,Brazil).
She is the recipient of the Best Paper Award at the 2017 IEEE International Conference on
Software Architecture (ICSA) for the paper "Understanding Software Vulnerabilities Related to
Architectural Security Tactics: An Empirical Investigation of Chromium, PHP and Thunderbird".
Her main research interests are in the domain of Software Engineering.
Honors/Awards:
• Best paper award at ICSA'17
• Scholarship from CAPES (Brazil) to pursue a masters degree at RIT (2014-2016)
Interested Positions: Academic Research, Academic Teaching, Industry Research Research interests: Software Security, Software Architecture, Empirical Software Engineering, Software Traceability
Email: [email protected] Website: https://people.rit.edu/jds5109/
Leila Delshadtehrani
Bio: Leila Delshadtehrani is a PhD candidate at Boston University’s Integrated Circuits and
Systems Group working with Prof. Ajay Joshi and Prof. Manuel Egele. Her research interests are
in computer architecture, end-to-end hardware design, and practical hardware solutions for
security. Prior to starting her PhD studies at Boston University, she received her M.Sc. and B.Sc.
degrees from Sharif University of Technology.
Interested Positions: Industry Research, Industry Product, Postdoc Research interests: Computer Architecture, Hardware Security, System Security
Email: [email protected]
Newton
Bio: Newton is a Joint-PhD student in the School of Computing at the National University of
Singapore (NUS) and the Department of Electrical Engineering at Indian Institute of Technology
(IIT) Bombay. He is a recipient of Visvesvaraya PhD Fellowship by Indian Government and NUS
Strategic India Initiative study award by Singapore Government. Prior to starting his research
studies, he was a senior software engineer.
Apart from the research, he likes to learn about the science of well-being and happiness.
Honors/Awards:
• Visvesvaraya PhD Fellowship
• NUS Strategic India Initiative Study Award, Travel Grants (VDAT, CASS)
Interested Positions: Academic Research,
Industry Research, Postdoc
Research interests: Hardware Accelerators,
Cache Memory, PIM, 3-D Stacked Memory, Non
volatile memories
Email: [email protected] Website: http://www.ee.iitb.ac.in/student/~newton
Pantea Zardoshti
Bio: I am a PhD candidate in Computer Science at Lehigh University. I enjoy working at the
intersection of the compiler, memory systems, and concurrent systems, with a focus on simplifying
persistent concurrent programming. Recently, I have been focusing on providing static analysis
and transformation to enable programmers to take advantage of non-volatile memory devices like
Intel Optane without modifying the legacy applications. I have experience working on concurrent
systems and non-volatile memory as part of my internships at Oracle Lab, Oracle Corp, and Intel
Corp. Outside of work, I serve as a board member of AnitaB.org Technology Committee trying to
advance opportunities for women in technology, from students in the classroom to executives in
the industry.
Honors/Awards:
• Best paper award nomination at IPDPS 2020
• CRA-W Scholarship 2017, GHC Scholarship 2018/2020, ACM Travel Award
2018/2019/2020, NSF Travel Award 2018
• Ranked 109th in the Nationwide University Entrance Exam for B.Sc., 2005
• Silver Medal Winner, National Computer Olympiad, 2004
• Best Iranian Student Award, National Organization for Development of Exceptional
Talents, 2004
Interested Positions: Industry Research, Industry
Product
Research interests: Concurrent Systems,
Compilers, Memory Systems, Parallel Computing
Email: [email protected] Website: https://www.linkedin.com/in/pantea-zardoshti/
Qijing Jenny Huang
Bio: Qijing Jenny Huang is a PhD student at the University of California, Berkeley, advised by
Prof. John Wawrzynek. Her interests are in computer architecture, computer-aided design,
reconfigurable computing, and machine learning. She has been working on building efficient
FPGA accelerators for emerging ML applications, HLS-based hardware/software flow, and ML-
assisted HLS and compiler transformation. Her thesis work focuses on novel design and
scheduling techniques for accelerating machine learning algorithms on heterogeneous spatial
architecture. She received her B.A.Sc. in Electrical and Computer Engineering at the University of
Toronto, where she was granted the University of Toronto Excellence Awards for her
undergraduate research.
Honors/Awards:
• 2017 FPT Best Paper: Synthesis of program binaries into FPGA accelerators with runtime
dependence validation
• 2018 IEEE Micro’s “Top Picks from Computer Architecture Conferences” - FireSim:
FPGA-accelerated cycle-exact scale-out system simulation in the public cloud
Interested Positions: Academic Research,
Academic Teaching, Industry Research, Industry
Product, Postdoc
Research interests: Hardware Acceleration,
Compiler Optimizations, Design Methodology with
High-Level Synthesis (HLS), Machine Learning for
Hardware Design
Email: [email protected] Website: https://hqjenny.github.io/
Subhankar Pal
Bio: Subhankar Pal is a 5th year PhD student advised by Prof. Ronald G. Dreslinski at the
University of Michigan, Ann Arbor, where he received his MS degree in 2018. He currently works
on researching reconfigurable hardware that deliver high efficiencies while retaining CPU-like
programmability. He received a BE degree in Electrical and Electronics Engineering from BITS-
Pilani, India, following which he was with NVIDIA, Bangalore where he worked on pre-silicon
verification and bring-up of multiple GPUs. His current research interests are in the area of
hardware accelerators, hardware-software co-design, memory systems and emerging
technologies.
Honors/Awards:
• NVIDIA top contributor
• DAAD-WISE scholar (undergrad)
• Angiras "Best Student" awardee (undergrad)
• Merit-cum-need scholar (undergrad)
Interested Positions: Industry Research,
Postdoc
Research interests: Computer architecture,
hardware accelerators, memory systems,
hardware-software co-design, emerging
technologies
Email: [email protected] Website: https://subhankarpal.com/
Tae Jun Ham
Bio: Tae Jun is currently a postdoctoral researcher at Seoul National University. Tae Jun received
his B.S.E degree from Duke University and received his masters and Ph.D. in Electrical
Engineering from Princeton University under the supervision of Professor Margaret Martonosi. His
main research area includes hardware-software co-design for emerging applications and data
access optimizations across systems and architectures. He is the recipient of Best Paper Award
in MICRO-49, IEEE Micro Top Picks Honorable Mention in 2016, and Best Paper Award
Nomination in ISPASS 2020. He is also the recipient of the Samsung Scholarship 2012-2017.
Honors/Awards:
• Best Paper Award Nominee (ISPASS 2020)
• Best Paper Award (MICRO-49)
• IEEE Micro Top Picks Honorable Mention (2016)
• Samsung Fellowship (2012-2017)
Interested Positions: Academic Research, Industry Research Research interests: Software-Hardware Co-design, Accelerators, Machine Learning
Email: [email protected] Website: https://taejunham.github.io
Wen Wang
Bio: I am Wen Wang, a final-year Ph.D. student in the Department of Electrical
Engineering at Yale University, working with Prof. Jakub Szefer. I am interested in post-quantum
cryptography and hardware security. My research focuses on designing secure, flexible and
efficient hardware/software architectures for different families of post-quantum cryptography
targeting new-generation heterogeneous computing platforms.
Honors/Awards:
• Selected as Barlow Fellow with Fellowship by Yale Graduate School in 2016
• Yale Sheffield Fellowship in 2015, National Scholarship of China in 2014
Interested Positions: Academic Research, Industry Research, Postdoc Research interests: hardware security, cryptographic engineering, post-quantum cryptography, computer architecture
Email: [email protected] Website: https://caslab.csl.yale.edu/~wen/
Wenjie Xiong
Bio: Wenjie Xiong is currently a postdoctoral researcher at Facebook AI Research (FAIR) SysML.
She received her Ph.D. degree in the Department of Electrical Engineering at Yale University,
advised by Prof. Jakub Szefer. She received her B.S. degrees in Microelectronics and Psychology
from Peking University and her M.S. degree in Electrical Engineering from Yale University. She
works on hardware security. She proposed run-time DRAM Physically Unclonable Functions
(PUFs) for device authentication, key storage, and software protection. She also explores new
cache timing channels and their formal models.
Honors/Awards:
• She was awarded Microsoft Research Graduate Women's Scholars in 2015 and selected
as a participant in the third Heidelberg Laureate Forum
• Her work on run-time accessible DRAM PUFs was selected as Top Picks in Hardware and
Embedded Security 2019
• One of her work was selected as Best Student Paper Finalist in HOST 2017
Interested Positions: Academic Research Research interests: Hardware security, Computer architecture, cache-based side and covert channels, Physically Unclonable Functions (PUFs)
Email: [email protected] Website: https://caslab.csl.yale.edu/~wenjie/
Xingyao Zhang
Bio: Xingyao Zhang received the Ph.D degree in electrical and computer engineering from
University of Houston, Houston, TX, 2020. And he received the B.S. degree in electronic
information engineering from University of Electronic Science and Technology of China,
Chengdu, China, in 2014. His current research interest lies
in high performance computing, especially the computer architecture design for machine
learning accelerations.
Honors/Awards:
• Zhang, Xingyao, et al. "Enabling Highly Efficient Capsule Networks Processing
Through A PIM-Based Architecture Design." 2020 IEEE International Symposium on
High Performance Computer Architecture (HPCA). IEEE, 2020
• Zhang, Xingyao, et al. "Towards memory friendly long-short term memory networks
(LSTMs) on mobile GPUs." 2018 51st Annual IEEE/ACM International Symposium on
Microarchitecture (MICRO). IEEE, 2018
Interested Positions: Academic Research, Industry Research, Industry Product Research interests: Neural Network Acceleration
Email: [email protected]
Yuan Zeng
Bio: I am a fourth year PhD student at Lehigh University, I am interested in spiking neural network
algorithm design and its implementations; energy efficient architecture designs; and cache-
memory data movement optimization.
Interested Positions: Academic Research, Industry Research, Postdoc Research interests: Neuromorphic algorithm and hardware, energy efficient computer architecture, cache and memory optimization
Email: [email protected] Website: https://wordpress.lehigh.edu/yuz615/