-COMERCIAL E INDUST RIAL l rDA

Av_ Engenhe"o lUII Cados Se, ,,", , 80 1 ( 0"1 11111 '11 . 8,001!!;n Novo CE P.0 4 57' . fone (PAU IS)!- 9355 · Tele. (O I!) 53-'188 FAX ISs . nI 61-J770 -SP

DESIGN APPUCATIONS

ElECTRONIC DESIGN EXClUSIVE

Fasf modem designs benefit from DSP chip's versatility John Roesgen Analog Devlces Inc .. Two Technolooy Woy. Norwood. MA 02062·0280: (617) 3294700.

This is lhe las! il1 a series Df fa lir arfirles de­lailill~ a J1(!W digira I signol processor wilh mOl1y

applicGrioll.'i. Previolls ar/ides iJ1lrodllced lhe ADSP-2100 (FeiJ. 20. [I. 131 ). covered irs ver­sotility in imaging aI/ri 11Iochine visioll syslems (Marclr 20. 1'. 135). alld slrolVed Ir OIV ir .\'IIcceeds in linear prediclive codillg ono/ysi.'i for sreech (A[lril 17. [I. 153).

To send data at more than 4800 bits/ s over the limi ted bandwidth or telephone lines. modems use

Quadrafure amplitude modulafion is one modem fask fhis DSP chip handles_ Its high densify simplifies de­sign; a dual bus speeds operation.

quadraturc amplitude modu la li on and thu s mandale digital signal processing. As the data rate climbs above 9600 bits /s (as h ig h as 19,200 bits /s in some rec en t modems), the compu ta tiona I dema"ds become particularly sevcrc. For in stance, errar-correcti ng codes

musl bc applicd to lhe data st rcam to maintain ac­ceptable perrorma nce. Furthermore, bidirectional rast transm ission ovcr a singlc phonc linc rcqui rcs cilhcr echo canccl1a tion ar rapid signa l rcversal to 4uickly changc t1i rcction.

Because that levei or complexity cannot be met by currenl s ingle-chip signal proccssors. dcsigners havc turncd to l11ult iplc processar conri gurat ions, bi t-slicc archilCC 1U rc, and cuslOm V LS I. Thosc ave­nucs, howevcr, 1101 only rcquirc longcr and more dif­flcult design cycles than a single-chip processar but also extort a higher cost.

Now, the ADSP-2 100 DSP microprocesso r packs enough horsepower 10 single-handedl y tackle high-speed modem lasks. Its dual-bus architecture, on -chip eache memory. para llel arit hmct ic units, and powcrfu l program scqucnccr combine lo ae­commodate the ma ny required algorithms. In addi­tion, extensive development tools reduce both hard­ware and software dcsign time.

Reprlnted Irom ELECTRONIC OESIGN - Juno 12, 1986

In opcration. externai program mcmory supplies instructions lo lhe processor and stores cocfficicnls ror lhe vurious riltcrs. whi lc lhe ex ter na i data memory holds interna i processing variables. sa mple burrers, and fIIter dclay lines (Fig. I). The large ad­dress range of the chip gives plenty ar slOrage space in bOlh l11emori es.

The digita l interrace section ties the modem to the termin al or compute r equ ipment. A se rial transm itterj receivcr maps int o lhe processor's data-mcmory address spacc as a peripheral dcvicc, as does a receivcr trackcr, which kceps lhe recciver bil clock synchronized lO the transminer ai lhe fa r­end modem. The transmitter tracker establishes timing ror the local transmitter, and both tracker ci rcuils generalc processo r intcrrupts to synchro­ni ze the sortware. Those interrupts are serviced by lhe chip with almost no overhead.

The teleph one line connects to t he modem through an analog interrace, with three devices in that sect ion memory-mapped to the processar. A digitally programmed automalic ga in control (agc) circui t normalizes the incoming signal to a prede­termined leveI. Arter fIItering, an analog-Io-digital converter gcnera les sa mples af lhe receivcd signal and passes them lo the processar. On lhe transmit­ting side. a d-a converter takes samples rrom the processor and ge nerates an analog output signal , which is then flltered and coupled to the transmit­ting line.

Depcnding on the complexity or lhe nonDSP tasks (rront panel displays and network-conlrol rea­tures, ror example), a host microprocessor may be desi rable, connected most simply through the pro­gram mcmory interrace. With the bus request and gra nt signals on the chip, the host ga ins direct ac­ceS$ to lhe program memory. Consequently, it can down load processor programs and control their exe­culion . Thc interrace ca n also accammodate data excha nges between lhe two processor5 .

While the heart ar a modem lies in its signa l­processing sortwa re. modem performance depends

Copyrlghl 1986 Hayden Publlshlng Co., Inc.

DESIGN APPLlCATIONS • DSP chip in a modem

on lhe proccssor's ability to execute a va riety af software tasks in real time. Genera lly, those tasks rall in to two ma­jor groups: tasks lhat pcrform lhe transmittcr funct ion and tasks lhat pcrfofm the rcccivcr function.

SCRAM BlED DATA

Thc transmillcr scct ion (Fig. 2) converts lhe incomi ng digital bit sLrca l11 to :t il analog form compa l iblt.: with lhe telephone channel. First it scramblcs the data in a pscudo­random rashion, making the spectrum or the transmittcr OUlput rcscmblc whitc noisc lo use lhe channel bandwidth more cflicicnt ly. Thc opcratioll cases lhe rccQvery af lhe carrier and timing signal a1 the rccciving cnd.

Arter "'whitcning" lhe outpul spcclrul11, lhe transmit­ter converts lhe scramblcd serial bit slrcalll jn ta parallcl multi bi t words callcd symbols. The num bcr or sy mbols depends on the mod ulation structure. At 9600 bits/s, rour bits deli ne a symbol, and 16 symbols are used. The symbol rate is thcrerore one-rourt h or the dat a ra te, or 2400 symbols/s . Highe r da ta rates req uire more symbols to keep the symbol rate lower than the cha nnel bandwidt h.

Theencoder maps each symbol into a particular combi­nalion af carrier amplitude and phasc. I f an crror-cor-

rccting code is uscd , the red undant bits are compuled and added to the output ai this point. Since the phase inrorma­tion is usually cncodcd dirre rentially, each symbol gener­ales a ehange fram lhe previous phasc rathcr th an gcn­erating ao absolu te phasc. Thc rcsu lt is a complcx numbcr representi ng the desi red amplitude and phase or the car­rier for each symbol inlerval.

The multiplier un i! Illodu lales lhe eneodcr oulpu l bya complcx carrier lO COllvcrt lhe frequency spect rulll in to thcchanncl's pass bando An interpolati ngdigital lilter re­ccivcs lhe modulaled ca rricr, incrcases lhe sample ra le. and removcs som c of lhe repclit ions within lhe speetru ll1. A o-a converter changcs lhe real OUlpUl of lhat liltcr to analog rorm, which becolllcs lhe modcm's aud io outpU l.

The receiver seclion (Fig. 3), which recovers lhe lrans­mit ted data , is noL as straightrorward as lhe tra nsmi tter. Since lhe channel loss is unpred ictable, it fi rsl normalizes lhe incoming signal through an age circuil. Art cr con­verting the norma lizcd signal to di gi lal rorm , li phasc­splitting fi lt cr rccovers lhe imag illury parl and rcduces the sa mple rrcq uency to the symbol rate.

Ir the chann cl were perreet, the out put or the phase­splitt ing li lter would be idcntical to the input ort he trans-

program memory data bus

Data momory Data memory

~ program memory

14 PMA OMA (address) (address)

ADSP-2 100

PMO OSP OMO

2' (data) (data)

program memory oddress bus Interrupt

request

program program momory momory

bos bus roquosl granl

data bus address bus

111 . li!

14 14

-y

' 6

I- Tronsmitter ~ tracker

Data mcmory

Decoder

TInI I I To perlpheral devlces

. Digitai lnlerlaco

Transmit clock

Tronsmlt doia

Rocolvo

-To dotn tormlnol

oqulpmenl

i - I t I ~ Recoivor I data

Recelve

I H"" I . l I memory ,

-~ ' I I I I I-I I ' 6

I~ I I I I

I I I - I

tracker r I 1

~ t-B-1 Au'oma1l' ~ ADC Filler gnln conlrol

. .g..

clock -

f--o Analog f--o

Interlace

Recelvo

TO telephono

line - --- _ -!

~ f--o I Hosl I I processor OAC Filler f--o

Transmlt

L _ J--- - - - - - -'

1. lhe ASDP-2100's dual bus slruclure speeds operCllon oy cllowlng tne D$P microprocessor lo felch instruc-1I0ns ond dolo sIm uItoneously. l he d igItal Inlerloce connecls lhe modem wilh lhe dolo lermino I equipmenl or lo lhe compuler. Wilh d-o ond o-d converlers, lhe onolog Inlerfoce lIes lhe modem lo lhe phone line.

mittcr's in terpola ling digi lal fi lter, and lhe rccciver caulel sil11ply dClllodulalc lhe signal lo recove r lhe da la. H ow~

ever, lhe channcl amplitude and phasc characterislics are not un iforl11. T hey vary widely froll1 channel to cha nnel and l11ay also changc over lime on a single channcl. Since lhe carrier amplitude Hnd phase contain lhe informal ion, cq uatizalion must compcnsale for any distorl ion. Fu r ~

lhcrmore, beca use lhe eq ua lizer is adapli ve, it ca n adjust lo any channcl and lrack any changcs.

Multiplicalion by a local carrier dClllodulales lhe equali zer OUlpUt. AI Ih is point, since lhe signat may still be corrupled by noisc or s ho r l ~l erm channcl dislu rba nccs thtH lhe equa lizer C:l nnOI track , its am plitude anel phase may /101 exact ly ma tch tlmt of lhe origina l transJ11 itted signaJ. Fortu nalely, as lhe rccciver has been programmed fo r the allolVable ampl itude and phase eombinations, it decides IVhich of these is closest lO the reccived signal , usuall y by choos ing the reference cOl11bina lion with lhe sma llest Euclidean distance (in real-im aginary space) lO

lhe received signa l. H owever, i f convolu l ional er ror­correcting codes are used, a fa r more complcx sca rch al~ gorilh ll1 ll1ust make lhe dccision.

Serial bi t slrea m

Analog slgnal

Auloma lic gain-control

circuil

Aeal _

Scramblor

ADC

Timlng­recovery algorilhm

Phase­splitting

Iilter

5erl;lI-IO­pamllel

convert er

Equalizer lillBr

Encoder

In ci t her case, a n error compula t ion campa rcs lhe dcci­sion OUlpUI lo th!! recc ivcd signal and calculatcs an errar vcctor. As long as the dccision is corrccl, lhe errar vector ind icates haw far the rcce ivcd signa l dev iates from its ideal ampli tu de and phase. A second multip li er re ­modulates lhe error vccWr inlo the.: p'ISS ba nd nnd drives the equali zer coefficient upda te algorith m. The errar al­gorit hrn fccds back the r hase component of the errar to lhe loca l ea rricr ge.:ncra lor, kce ping the rt!ccivt!d carrier synchronized to lhe tra nsrni ucd'carrier.

DESCRAMBLED DATA

Til !! rccc ivt!f's I:lst th rec blocks in vc rt th!! opera tions pcr formcd by the fi rs t th rec blocksol" the transmitter. The dccodcr ma ps lhe recc ived amplitude and phnse in lo a muttibi l symbol and converts il lO a serial bit strcam. Dc~

scrambli ng lhe slream reCQve rs lhe original data. Though ali lhe fu nct ions gencratc a subslant ial quan~

tity of softwa re, a fe lV critical lasks produce most of the processing burde n and limil modem performance. The modem recei vcr's adapt ive equal izer accounts for lhe la rgest ra rt of t he tota I rrocessi ng demando I t consists of a

(a)

Carrlar genernlor

Inlerpolat lng digitai Imer

Mul!ipller

Mul llpUer

Declslon algorllhm Oceoder

DAC

,

Parallel­Ia- serial

converter

1---.. Analog slgnal

Digitai oulpUI

De­scrambler

Complex Car rier

generator

Compute­error

algorithm

51gna1 quallty

Indlcation

Aemodulated "'===...: error veclor JiI

Multlpller

~E:mo=_DII Error vector

(b)

2. By converl lng lhe rece lved dlgllol signo I Inlo onolog form, lhe Ironsmltter sectlon enobles dlgllol equlp­menl lo send ils Informoflon over onolog le lephone tin es. To do Ihls, flrsl 11 "whllens" lhe speclrum of lhe slg­nol In lhe scrambl er, Ihus eosing recovery of lhe corri,,, ond l iming signo I 01 lhe receivlng end. To confrol precislon ond repeolobtlily, lhe Ironsmitter performs 011 IIs fun,:llons dlgllolly (a). Becouse lhe recelver se c­lion (b) conlolns mosl oI lhe processlng funclions, 11 occounls for mosl of lhe signol-processlng demond. Thol resulls from signol degrodol lon on a le lephone tine . Since lhe chonnel Is Imperfecl, equatlzoflon com­pensate s for d lstorllo n, and a declsion algorilhm corrects for added nolse.

DESIGN APPLlCATIONS • DSP chip in a modem

filter routine and a coefficient adaptation algorithm. The equalize r filter uses a finite-impulse-response structure, while the coefficient adaptation employs a least-mean­squared algorithm. They are coded into subroutines and called from an executive programo

A subroutine for the filtering portion of the equalizer demonstrates the microprocessor's efficiency in dealing with complex numbers (Fig. 4, left). Both the samples and the coefficients have real and imaginary parts, which are kept in separate buffers to simplify access. Goefficients are stored in the program memory and samples in data memory, enabling them to be fetched simultaneously.

Input and output variables pass through internai regis­ters. Each time the subroutine is called, it processes an in­put sample and produces an output sample. Index regis-

. ters are set up with pointers to the filter sample buffer (delay line) and coefficient storage area. Preloading the length registers with the filter order triggers the modulo­addressing capability, ensuring that the pointers will be confined to their respective buffers .

• },Io" ...... .

The filter code contains two Do ... Untilloops, both without overhead cycles. The first computes the real part of the output using only two instructionso One instruction accumulates the products of thc rcal cocfficicnts and thc real samples; the other subtracts the products of the imag­inary coefficients and the imaginary sampleso The second Do o o o Untilloop computes the imaginary output byac­cumulating the cross terms (real X imaginary and imag­inary X real), again using two instructionso

The Do o o o Until structure imposes no penalty for loop sequencingo Fetching of samples and coefficients parallels thc computationo Even though the cocfficients arc fctched from program memory, the program flows without inter­ference beca use the internai cache memory supplies the loop instructions after the first passo

The modem accomplishes other major filtering oper­ations with similar routincs. For inslance, as in lhe equal­izer the transmit filter also uses complex inputs and com­plex coefficients to compute the real output. Similarly, lhe phase-splitting filter produces a complex output from real

,~'.~ ..... '.~ .. ;. . . . . . . . . . . . . . . . . . . . ................................. .

.; .. ' . -. ';.

.. '

.

Equalizer Filter Subroutine

l-i Algorithm: Vr (N) .. SUM ( Hr (K) • Xr (N - K) - HI (K) • XI (N - K) )

K-O

l-i Vi (N) - SUM ( Hr (K) • Xi (N - K) + HI (K) • Xr (N - K) )

K-O

lnput: AXO contalns reallnput Xr. AX1 comains imaglnary Input XI. 10 points to starting place In real deloy Une 11 polnts to starting place In Imaginary delay Une 14 points to real coeftlclents 15 points to Imaginary coefflcients LO contains filter arder L 1 contains filter order L4 contains filter order L5 contains fUter order MO contains 1 M4 contains 1

Output: SR1 contains real output Vr. MR1 contains imaginary output Vi

E~ecut!Qn Cycles: (4· L) + 24 where L Is the fUter order

• ".a •• , a .••.•• a, .•.•••••••• '-0_ ....................................... .

CMPXFIR:

REALLOOP:

DM (10. MO) "'" AXO; . . DM (11. MO) - AX1:

AVO - LO; AR - AVO-1: .' . CNTR .. AR: MR coa 00 MXO - DM (11. MO). MVO ... PM (IS. M4); DO REALLOOP UNTIL CE:

MR Clt MR - MXO • MVO. MXO - DM (10. MO). MVO ... PM (14. M4): MR - MR + MXO • MVO. MXO - DM (11. MO). MVO - PM (15. M4):

. MR - MR - MXO • MVO. MXO - DM (10. MO). MVO - PM (14. M4); MR - MR + MXO • MVO (RND): SR1 c;o MR1: . CNTR - AR:

:X~~1?';':~~~~1ª ~~~.;~;;;;;~; ~~: ~~ ~~: ~l: .. -:. ... : ~.... " '. :. MR ~ MR + MXO • MVO. MXO ':"'" DM (11. MO). MVO - PM (14. M4):

MR = MR + MXO • MVO (RND): : RTS;

I Store Xr in delay line I Store XI In delay line I Subtract 1 from fllter order I

I Lood loop counter I Clear MR. Get XI. Get Hi I

I Xi • HI. Get Xr. Get Hr I Xr • Hr. Get XI, Get Hi I XI • HI. Get Xr. Get Hr Xr.Hrl Sove Vr I lood loop counter I Clear MR. GetXr. Get Hi I

. Xr • Hi. Get XI, Get Hr I XI • Hr.,Get Xr, Get Hi Xr • Hi. Get XI. Get Ht XI • Hr I

.. ;e j z:zz

inputs and complex coefficients. requiring only minor al­terations to the equalizer filter code.

Sample rate changes through filters are also easily done by adjusting the two M register values. Those values modify the coefficient and data pointers after each memory access. The ratio of the M register values deter­mines the input-to-output sampIe ratio. To effect a sam­pIe rate increase of four. the data pointer would be moved by one. but the coefficient pointer would be moved by four. Or moving the data pointer by four and the coeffi­dent pointer by one yields a sample rate decrease of four.

The program adapts the equalizer filter coefficients in small steps. Each time a new error vcctor becomcs nvail­able, the coefficients get c\oser to their ideal values. A subroutine for the adaptation aIgorithm updates each complex coefficient in only six cycles (Fig. 4. right). In­puts to the routine include pointers to the sample and co­efficient buffers, pointer modification values. and the er­ror vector. The output is a set of updated coefficients. Combining arithmetic operations with a memory access, the six instruclions in a single Do ... Untilloop perform

alI the work. That loop updates the real and imaginary parts of each coefficient, based on the corresponding sam­pIe in the filter delay line and the error vector. Sharing the computational load. the multiplier-accumulator com­putes the update terms and the ALU adds them to the co­efficient. The processor then writes the new coefficient back into program memory and can proceed to the next filtering operation.

Another time-consuming task is the received signal decision. In the simplest method, the processor compares each received sample to ali the possible transmitted val­ues, and chooses the nearest one. One comparison mea­sure is Euclideun distancc in the real-imaginary plane. with lhe best choice being the point at the least distance from the received sample.

Assembly code for the received signal decision executes this task in just nine cycles per comparison. Inputs to the routine are the received sample. the total number of refer­ence points, and a pointer to the memory buffer contain­ing the reference coordinates. The reference points repre­sent the allowable transmitted signal values. one ofwhich

Equallzer Fllter Coefflclent Adaptatlon Subroutlne

Algorlthm: Hr (K) - Hr (K) - Er • Xr (N-K) + EI • XI (N-K) HI (K) - HI (K) - Er • XI (N-K) - EI • Xr (N-K)

Input: 10 polnts to Xr buffer. 11 polnts to XI buffer 14 points to Hr buffer 15 polnts to Hi buffer LO contalns mer order Li contalns f~ter order MO contalns 1

.. :.

.. :~~ M4 contalns o . . M5 contalns 1 MXO contalns Er MX 1 contalns EI CNTR contalns number of complex coefflclents

Output: Coefflclents updated In coefflclent buffers

Executlon Cycles: (6· N) + 8 where N Is the number of complex coeftIclents

• • • • • • •.••••••••••••••••••••••••••••••••••••••••••.••.•••.•. ; •. ,. ,e ".' . .," ~:. :' .. ~ .,:,:~~(} .. ~::"

UPDATE:

COEFLOOP:

ENDMOD:

MVO => DM (10. MO): MR c::o MXO • MVO. MV1 ... DM(l1. MO); 00 COEFLOOP UNITL CE;

MR - MR - MX 1 • MV 1 (RND). AVO - PM (14. M4): AR c::o AVO - MR1. AVi"" PM (15. M4): PM (14. MS) - AR. MR - MXO • MV1; MR ... MR + MX 1 • MVO (RND). MVO .... DM (10. MO); AR - AVi - MR1. MV1 - DM (11. MO); PM (15. MS) - AR. MR - MXO • MVO;

RTS:

4. In lhe equallzer flller subroullne (Ieft), lhe mlcroprocessor deals wllh complex numbers. Separale buffers contaln lhe real and Imaglnary parts of bolh thesamples and the coeffl­clenls. The equallzer fIIler coefflclenl adaptatlon subroutlne (rlghl) updales each complex coefflclenl In slx cycles, produclng a set of updated coefflclenls.

.. li

DESIGN APPLlCATIONS • DSP chip in a modem

will be returned to the calling program as the receive deci­sion.

The parallel arrangement of arithmetic units permils tlexible opcration sequencing in loop instruclions, for ex­ample. Computalion of Euclidean distance req uires a sum of squares of differences; that is, two subtraclions fol­lowed by two muJtiplications followed by an addition. This nonstandard succession generates much data­shuftling overhead in a serially organized machine.

The remainder of the loop compares each new distance with the previously found minimum distance. If the new one is smaller, it becomes the minimum. and lhe loop counter value is saved as an indexo After ali the distances are computed and compared, the subroutine returns lhe minimum distance and the corresponding reference index to the calling programo The program interprets the refer­ence index as the received signal decision, and the min­imum distance is the squared length or the error vector.

The software routines that have been described ac­count for a large portion of lhe lotai processing Joad in a high-speed modem. The chip's performance for these tasks can be calculated using the execution cycle formulas given in the subroutine headers. A standard 9600 bil/S modem will be assumed. A 40-lap equalizer needs 184 cy­cles for the filtering operalion and 248 cycles to update

the coefficients. Because the lransmit filter has no imag­inary oulput, and the phase splitting has no imaginary in­pul, lhey execute twice as fast as the equalizer. If both of these filtcrs have 30 taps, they require 72 cycles each. A receive signal decision with 16 reference points uses 148 cycles, yielding a total of 724 cycles.

Since each routine runs 2400 times/s, 1,737,600 pro­cessor cycles are used every second. Since lhe chip exe­cules 8 million cyc1es/s, the loading on the processor is 22%. This rclatively small number for such a major por­tion or the modem indicates an ability to handle even more sophisticated algorithms and higher data rates than indicated here. O

Jolm Roesgell. a slaff ellgilleer aI Analog Devices and lhe prillcipal architecl of lhe 2/00. joilled lhe Digital Sigllal Processing Divisioll in J 982. Roesgen has a BSEEfrom lhe Ulliversity ofColllleclicul.

Q'QaWWi!QlL· 11

..