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Circuit Diagram

CE Amplifier with Fixed Bias

Pin Diagram

Bottom view of BC107

E

B

C

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Ex no 1 COMMON EMITTER AMPLIFIER WITH FIXED BIAS

Date

Aim

To design and construct BJT Common Emitter Amplifier using fixed bias

To measure the gain and to plot the frequency response and to determine the GainBandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 51 KΩ 3MΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Fixed Bias with Emitter Resistor

The fixed bias circuit is modified by attaching an external resistor to the emitter This

resistor introduces negative feedback that stabilizes the Q-point From Kirchhoffs voltage law

the voltage across the base resistor is

VRb = VCC - IeRe - Vbe

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Tabulation

Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

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From Ohms law the base current is

Ib = VRb Rb

The way feedback controls the bias point is as follows If Vbe is held constant and

temperature increases emitter current increases However a larger Ie increases the emitter

voltage Ve = IeRe which in turn reduces the voltage VRb across the base resistor A lower base-resistor voltage drop reduces the base current which results in less collector current because Ic =

szlig IB Collector current and emitter current are related by Ic = α Ie with α asymp 1 so increase in emitter

current with temperature is opposed and operating point is kept stable

Similarly if the transistor is replaced by another there may be a change in I C

(corresponding to change in β-value for example) By similar process as above the change is

negated and operating point kept stable

For the given circuit

IB = (VCC - Vbe)(RB + (β+1)RE)

Merits

The circuit has the tendency to stabilize operating point against changes in temperature and β-

value

Demerits

In this circuit to keep IC independent of β the following condition must be met

which is approximately the case if ( β + 1 )RE gtgt RB

bull As β-value is fixed for a given transistor this relation can be satisfied either by keeping

RE very large or making RB very low

bull If RE is of large value high VCC is necessary This increases cost as well as precautions

necessary while handling

bull If RB is low a separate low voltage supply should be used in the base circuit Using two

supplies of different voltages is impracticalbull In addition to the above RE causes ac feedback which reduces the voltage gain of the

amplifier

Usage The feedback also increases the input impedance of the amplifier when seen from the

base which can be advantageous Due to the above disadvantages this type of biasing circuit is

used only with careful consideration of the trade-offs involved

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Design

Choose β = 250 VCC = 12V IC = 1 mA

By applying KVL to output side

VCC ndash ICRC ndash VCE = 0

VCC = ICRC ndash VCE

Assume equal drops across RC and VCE VRC = VCE = 6V ICRC = 6V

RC = 6V10-3

= 6KΩ

Choosing a standard value for RC as 51Ω

By applying KVL to the input side

VCC ndash IBRB ndash VBE = 0

IB = IC β = 1mA250 = 4microA

RB = (VCC ndash VBE) IB

= (12 ndash 07)4x10-6

= 2825M Ω

asymp 3M Ω

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Calculation

Bandwidth = f H - f L

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Procedure

1) Connect the circuit as per the circuit diagram

2) Set Vin = 50mV in the signal generator Keeping input voltage constant vary the

frequency from 1Hz to 1MHzin regular steps

3) Note down the corresponding output voltage

4) Plot the graph Gain in dB Vs Frequency in Hz

5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3)

The high frequency point is called the upper 3dB point4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

the frequency response curve is plotted

The bandwidth is found to be __________________

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Ex no 1 COMMON EMITTER AMPLIFIER WITH FIXED BIAS

Date

Aim

To design and construct BJT Common Emitter Amplifier using fixed bias

To measure the gain and to plot the frequency response and to determine the GainBandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 51 KΩ 3MΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Fixed Bias with Emitter Resistor

The fixed bias circuit is modified by attaching an external resistor to the emitter This

resistor introduces negative feedback that stabilizes the Q-point From Kirchhoffs voltage law

the voltage across the base resistor is

VRb = VCC - IeRe - Vbe

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Tabulation

Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

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From Ohms law the base current is

Ib = VRb Rb

The way feedback controls the bias point is as follows If Vbe is held constant and

temperature increases emitter current increases However a larger Ie increases the emitter

voltage Ve = IeRe which in turn reduces the voltage VRb across the base resistor A lower base-resistor voltage drop reduces the base current which results in less collector current because Ic =

szlig IB Collector current and emitter current are related by Ic = α Ie with α asymp 1 so increase in emitter

current with temperature is opposed and operating point is kept stable

Similarly if the transistor is replaced by another there may be a change in I C

(corresponding to change in β-value for example) By similar process as above the change is

negated and operating point kept stable

For the given circuit

IB = (VCC - Vbe)(RB + (β+1)RE)

Merits

The circuit has the tendency to stabilize operating point against changes in temperature and β-

value

Demerits

In this circuit to keep IC independent of β the following condition must be met

which is approximately the case if ( β + 1 )RE gtgt RB

bull As β-value is fixed for a given transistor this relation can be satisfied either by keeping

RE very large or making RB very low

bull If RE is of large value high VCC is necessary This increases cost as well as precautions

necessary while handling

bull If RB is low a separate low voltage supply should be used in the base circuit Using two

supplies of different voltages is impracticalbull In addition to the above RE causes ac feedback which reduces the voltage gain of the

amplifier

Usage The feedback also increases the input impedance of the amplifier when seen from the

base which can be advantageous Due to the above disadvantages this type of biasing circuit is

used only with careful consideration of the trade-offs involved

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Design

Choose β = 250 VCC = 12V IC = 1 mA

By applying KVL to output side

VCC ndash ICRC ndash VCE = 0

VCC = ICRC ndash VCE

Assume equal drops across RC and VCE VRC = VCE = 6V ICRC = 6V

RC = 6V10-3

= 6KΩ

Choosing a standard value for RC as 51Ω

By applying KVL to the input side

VCC ndash IBRB ndash VBE = 0

IB = IC β = 1mA250 = 4microA

RB = (VCC ndash VBE) IB

= (12 ndash 07)4x10-6

= 2825M Ω

asymp 3M Ω

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Calculation

Bandwidth = f H - f L

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Procedure

1) Connect the circuit as per the circuit diagram

2) Set Vin = 50mV in the signal generator Keeping input voltage constant vary the

frequency from 1Hz to 1MHzin regular steps

3) Note down the corresponding output voltage

4) Plot the graph Gain in dB Vs Frequency in Hz

5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3)

The high frequency point is called the upper 3dB point4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

the frequency response curve is plotted

The bandwidth is found to be __________________

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Tabulation

Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

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From Ohms law the base current is

Ib = VRb Rb

The way feedback controls the bias point is as follows If Vbe is held constant and

temperature increases emitter current increases However a larger Ie increases the emitter

voltage Ve = IeRe which in turn reduces the voltage VRb across the base resistor A lower base-resistor voltage drop reduces the base current which results in less collector current because Ic =

szlig IB Collector current and emitter current are related by Ic = α Ie with α asymp 1 so increase in emitter

current with temperature is opposed and operating point is kept stable

Similarly if the transistor is replaced by another there may be a change in I C

(corresponding to change in β-value for example) By similar process as above the change is

negated and operating point kept stable

For the given circuit

IB = (VCC - Vbe)(RB + (β+1)RE)

Merits

The circuit has the tendency to stabilize operating point against changes in temperature and β-

value

Demerits

In this circuit to keep IC independent of β the following condition must be met

which is approximately the case if ( β + 1 )RE gtgt RB

bull As β-value is fixed for a given transistor this relation can be satisfied either by keeping

RE very large or making RB very low

bull If RE is of large value high VCC is necessary This increases cost as well as precautions

necessary while handling

bull If RB is low a separate low voltage supply should be used in the base circuit Using two

supplies of different voltages is impracticalbull In addition to the above RE causes ac feedback which reduces the voltage gain of the

amplifier

Usage The feedback also increases the input impedance of the amplifier when seen from the

base which can be advantageous Due to the above disadvantages this type of biasing circuit is

used only with careful consideration of the trade-offs involved

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Design

Choose β = 250 VCC = 12V IC = 1 mA

By applying KVL to output side

VCC ndash ICRC ndash VCE = 0

VCC = ICRC ndash VCE

Assume equal drops across RC and VCE VRC = VCE = 6V ICRC = 6V

RC = 6V10-3

= 6KΩ

Choosing a standard value for RC as 51Ω

By applying KVL to the input side

VCC ndash IBRB ndash VBE = 0

IB = IC β = 1mA250 = 4microA

RB = (VCC ndash VBE) IB

= (12 ndash 07)4x10-6

= 2825M Ω

asymp 3M Ω

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Calculation

Bandwidth = f H - f L

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Procedure

1) Connect the circuit as per the circuit diagram

2) Set Vin = 50mV in the signal generator Keeping input voltage constant vary the

frequency from 1Hz to 1MHzin regular steps

3) Note down the corresponding output voltage

4) Plot the graph Gain in dB Vs Frequency in Hz

5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3)

The high frequency point is called the upper 3dB point4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

the frequency response curve is plotted

The bandwidth is found to be __________________

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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From Ohms law the base current is

Ib = VRb Rb

The way feedback controls the bias point is as follows If Vbe is held constant and

temperature increases emitter current increases However a larger Ie increases the emitter

voltage Ve = IeRe which in turn reduces the voltage VRb across the base resistor A lower base-resistor voltage drop reduces the base current which results in less collector current because Ic =

szlig IB Collector current and emitter current are related by Ic = α Ie with α asymp 1 so increase in emitter

current with temperature is opposed and operating point is kept stable

Similarly if the transistor is replaced by another there may be a change in I C

(corresponding to change in β-value for example) By similar process as above the change is

negated and operating point kept stable

For the given circuit

IB = (VCC - Vbe)(RB + (β+1)RE)

Merits

The circuit has the tendency to stabilize operating point against changes in temperature and β-

value

Demerits

In this circuit to keep IC independent of β the following condition must be met

which is approximately the case if ( β + 1 )RE gtgt RB

bull As β-value is fixed for a given transistor this relation can be satisfied either by keeping

RE very large or making RB very low

bull If RE is of large value high VCC is necessary This increases cost as well as precautions

necessary while handling

bull If RB is low a separate low voltage supply should be used in the base circuit Using two

supplies of different voltages is impracticalbull In addition to the above RE causes ac feedback which reduces the voltage gain of the

amplifier

Usage The feedback also increases the input impedance of the amplifier when seen from the

base which can be advantageous Due to the above disadvantages this type of biasing circuit is

used only with careful consideration of the trade-offs involved

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Design

Choose β = 250 VCC = 12V IC = 1 mA

By applying KVL to output side

VCC ndash ICRC ndash VCE = 0

VCC = ICRC ndash VCE

Assume equal drops across RC and VCE VRC = VCE = 6V ICRC = 6V

RC = 6V10-3

= 6KΩ

Choosing a standard value for RC as 51Ω

By applying KVL to the input side

VCC ndash IBRB ndash VBE = 0

IB = IC β = 1mA250 = 4microA

RB = (VCC ndash VBE) IB

= (12 ndash 07)4x10-6

= 2825M Ω

asymp 3M Ω

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Calculation

Bandwidth = f H - f L

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Procedure

1) Connect the circuit as per the circuit diagram

2) Set Vin = 50mV in the signal generator Keeping input voltage constant vary the

frequency from 1Hz to 1MHzin regular steps

3) Note down the corresponding output voltage

4) Plot the graph Gain in dB Vs Frequency in Hz

5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3)

The high frequency point is called the upper 3dB point4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

the frequency response curve is plotted

The bandwidth is found to be __________________

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Design

Choose β = 250 VCC = 12V IC = 1 mA

By applying KVL to output side

VCC ndash ICRC ndash VCE = 0

VCC = ICRC ndash VCE

Assume equal drops across RC and VCE VRC = VCE = 6V ICRC = 6V

RC = 6V10-3

= 6KΩ

Choosing a standard value for RC as 51Ω

By applying KVL to the input side

VCC ndash IBRB ndash VBE = 0

IB = IC β = 1mA250 = 4microA

RB = (VCC ndash VBE) IB

= (12 ndash 07)4x10-6

= 2825M Ω

asymp 3M Ω

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Calculation

Bandwidth = f H - f L

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Procedure

1) Connect the circuit as per the circuit diagram

2) Set Vin = 50mV in the signal generator Keeping input voltage constant vary the

frequency from 1Hz to 1MHzin regular steps

3) Note down the corresponding output voltage

4) Plot the graph Gain in dB Vs Frequency in Hz

5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3)

The high frequency point is called the upper 3dB point4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

the frequency response curve is plotted

The bandwidth is found to be __________________

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Procedure

1) Connect the circuit as per the circuit diagram

2) Set Vin = 50mV in the signal generator Keeping input voltage constant vary the

frequency from 1Hz to 1MHzin regular steps

3) Note down the corresponding output voltage

4) Plot the graph Gain in dB Vs Frequency in Hz

5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3)

The high frequency point is called the upper 3dB point4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and

the frequency response curve is plotted

The bandwidth is found to be __________________

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Circuit Diagram

CE Amplifier with Self Bias

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Date

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)

with and without bypassed emitter resistor

To measure the gain and to plot the frequency response and to determine the Gain

Bandwidth product (GBW)

Apparatus Required

SNo Equipments Components Range Details Qty

1 Power Supply (0 ndash 30) V 1

2 Resistor 1KΩ 61KΩ 10KΩ 47KΩ 1

3 Capacitor 1 microF 1

4 Transistor BC 107 1

5 AFO (0 ndash 1) MHz 1

6 CRO (0 ndash 20) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same

time overcome some of the disadvantages of the other two biasing methods One of the most

widely used combination-bias systems is the voltage-divider type The voltage divider is formed

using external resistors R1 and R2 The voltage across R2 forward biases the emitter junction By

proper selection of resistors R1 and R2 the operating point of the transistor can be made

independent of β In this circuit the voltage divider holds the base voltage fixed independent of

base current provided the divider current is large compared to the base current However even

with a fixed base voltage collector current varies with temperature (for example) so an emitter

resistor is added to stabilize the Q-point However to provide long-term or dc thermal stability

and at the same time allow minimal ac signal degeneration the bypass capacitor (Cbp) is placed

across R3 If Cbp is large enough rapid signal variations will not change its charge materially and

no degeneration of the signal will occur

Merits

bull Unlike above circuits only one dc supply is necessary

bull Operating point is almost independent of β variationbull Operating point stabilized against shift in temperature

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

ExNo 2 COMMON EMITTER AMPLIFIER WITH SELF BIAS

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Model Graph

Tabulation

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Drop across RE (VRE) is assumed to be 1V

Drop across VCE with the supply of 12V is given by 12V ndash 1V = 11V

Assume equal drops across ICRC and VCE

So ICRC = VRC = 112 = 55V

Assume IC = 1 mA

Then RC = VRC IC = 55V 1mA = 55 KΩ

Instead of using 55 KΩ we can use a standard value of 47 KΩ

VRE = 1V IE asymp IC = 1mA

RE = VRE IE = 1V1mA = 1KΩ

Design of R1 and R2

Drop across VBE = 07V

Drop across R2 (VR2) = VBE + VRE = 17V

Assume R2 = 10 KΩ

VR2 = VCCR2 (R1+R2)

R1 = (12 X 10) (17 ndash 10) = 605 KΩ

R1 is assumed to be 61 KΩ

Design of input capacitor

F = 12πhieC

Take F = 100Hz and hie = 16 KΩ

C1 = 1 (2π X 16 KΩ X 100) = 09microF asymp 1microF

Design

Calculation

Bandwidth = f - f H L

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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1) The frequency response curve is plotted on a semi-log scale

2) The mid frequency voltage gain is divided by radic2 and these points are marked in the

frequency response curve

3) The high frequency point is called the upper 3dB point

4) The lower frequency point is called the lower 3dB point

5) The difference between the upper 3dB point and the lower 3dB point in the frequency

scale gives the bandwidth of the amplifier

6) From the plotted graph the bandwidth is obtained (ie) Bandwidth = f H - f L

Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

Procedure

To plot the Frequency Response

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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VCC = 12 V

R1

8 KΩ

- +BC 107

47 microF + -

AFO R2 RE 47 microF

5 mV 10 KΩ 6 KΩ VO (CRO)

Circuit diagram

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Ex no 3 COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date

Aim

1 To design and construct BJT Common Collector Amplifier using voltage divider bias

(self-bias)

2 To measure the gain and to plot the frequency response amp to determination of Gain

Bandwidth Product

Apparatus required

1 Transistors - BC107

2 Regulated Power Supply

3 Audio Frequency Oscillator

4 Resistors - 6KΩ 8KΩ 10KΩ (all are frac14 W)

5 Capacitors - 47microF

6 CRO

Design

Since voltage amplification is done in the transistor amplifier circuit we assume equal

drops across VCE and Emitter Resistance RE VRE = 6V The quiescent current of 1mA is

assumed We assume a standard supply of Vcc = 12V

Drop across RE is assumed to be VRE =6V

Drop across VCE is VCC ndashVRE =6V

We know that ICQ =IE

Now RE = VRE = 6V = 6KΩ IE 1X 10-3

Design of R1 amp R2

Drop across RE is 6V

Drop across VBE is 06V

Drop across the resistance R2 is VR2 = VBE + VRE =66V

Assume R2 =10KΩ

VCC R2

= 66 V

R1 + R2

12 X 10 X 103

= 66V

R1 + 10 X 103

120 X 103

= R1 + 10 X 103

66

1818 X 103 = R1 + 10 X 10

3

R1 = 8 KΩ (33 K + 47 K)

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Tabular column

Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax

3dB Line

f L f H frequency (Hz)

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

Thus a BJT Common Collector Amplifier is designed and implemented and the frequency

response curve is plotted

Bandwidth =

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Circuit diagram

VCC = 12 V

R1 RC

47 KΩ 47 KΩ

+ -

47 microF

- +BC 107 BC 107

47 microF VO (CRO)

AFO R2 RE1 RE + CE

5 mV 10 KΩ 47 KΩ 1 KΩ - 100 microF

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Ex no 4 DARLINGTON COMMON EMITTER AMPLIFIER

Date

Aim

1 To design a Darlington amplifier using BJT and to measure the gain and input resistance

2 To plot the frequency response and to calculate the Gain Bandwidth Product (GBW)

Apparatus required

1 Transistors - BC 107

2 Resistors - 1KΩ 47KΩ 47KΩ 10KΩ (all are frac14 W)

3 Capacitors - 47microF 100microF

4 CRO

5 AFO

6 RPS

7 Connecting wires amp Breadboard

Design

Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base

current for the 2nd

stage Hence the 2nd

stage IE current will be IE = (β+1)2ICO

For silicon transistor ICBO is the order of 10nA at room temperature β = 100

Now

IE = (101)2 X 10 nA

IE cong 105 nA cong 01mA

This current will get double with every 100 rise in temperature So to reduce the effect of

ICBO the 1st stage ICBO flowing through the emitter of the 1

st stage is not allowing to enter the 2

nd

stage by paralleling a resistor between B amp E of the 2nd

stage T2 So the ICBO(β+1) will flow

through this resistance and a part of this current might flow through hie + βdcRE This shunting

resistance will be the range of 1 to 47 KΩ

Biasing Design

Assume R2 = 10KΩ and Ic = 1mA

Since voltage amplification is done in the Darlington transistor amplifier circuit we

assume equal drops across VCE and load resistance RC The ICQ = 1mA is assumed We assume

standard supply of 12V

Drop across Re is assumed to be 1V The drop across VCE with a supply of 12 V is given

by 12 ndash 1 = 1VIt is equal to VRC amp VCE = 55V

RC = VRC = 55 KΩ (47 KΩ)IC

Design of R1 amp R2

Drop across RE is 1V

Drop across VBE1 amp VBE2 is 06V

Drop across the resistance R2 is VRE + VBE1 + VBE2

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Vs =

Frequency

(Hz)

VO

(Volts)

Gain = VO VS Gain = 20 log (VO VS)

(dB)

Model graph (frequency response)

Gain

dB

Amax3dB Line

f L f H frequency (Hz)

Tabular column

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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= 1 + 06 + 06

VR2 = 22V

R2 is assumed to be 10 KΩ

VCC R2

= 22V

R1 + R2

12 X 10 X 103

= 22

R1 + 10 X 103

120 X 103 = R1 + 10 X 10

3

22

545 X 103 = R1+ 10 X 10

3

R1 = 545 X 103 ndash 10 X 10

3

R1 = 445 X 103Ω

R1 is rounded to be 47 KΩ

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS = 5 mV using AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

1 The frequency response curve is plotted on a log scale

2 From the graph the bandwidth is obtained

Bandwidth = f H - f L =

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Pin Details

Circuit diagram

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Date

Aim

To design a common drain amplifier and to measure the gain input resistance and output

resistance with and without Bootstrapping

Apparatus required

1 Transistor - BC-107

2 Regulated Power supply

3 Audio Frequency Oscillator

4 Resistors - 47KΩ 27KΩ 1MΩ

5 Capacitor - 1micro F

6 CRO

7 Bread board and connecting wires

Bias design

VDD = 12 V IDSS = 95mA ID = 1mA VP = -4V Ci = 1microF

VGS = ID RS ID = IDSS1-(VGS VP)2

RS = 27KΩ Voltage drop across R S = 27V

VRD + VDS = VDD-VRS

= 12-27=93V

Assume equal drops across VRD amp VDS

VRD = VDS = 465V

RD = VRD ID = 465KΩ

Instead of 465KΩ we can select standard value = 47KΩ

FET input is always reverse bias So choose the value of resistance RG very large with in

The range of 1MΩ to 10MΩ

Theory

Here input is applied between gate and source amp output between source and Drain Here

Vs = VG + VGS When a signal is applied to JFET gate via CinVG varies with the signal As VGS

is fairly constant and Vs varies with Vi Here output voltage follows the change in the signal

voltage applied to the gate the circuit is also called as Source follower

ExNo 5 COMMON DRAIN AMPLIFIER

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Model Graph

Frequency (Hz) Vo (V) Gain = Vo Vs Gain = 20log(VoVs)dB

Tabulation

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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1 Connect the circuit as shown in the circuit diagram

2 Set Vs= 50 mv in AFO

3 Keeping the input voltage constant vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage

4 Plot the graph gain Vs Frequency

5 Calculate the bandwidth from the Graph

Result

Thus a common drain amplifier is designed and the gain input resistance and output

resistance are calculated using the measured parameters

Procedure

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Common mode Configuration

Differential mode Configuration

Circuit Diagram ndash Differential Amplifier

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Date

Aim

To construct the Differential Amplifier in

a) Common mode and

b) Differential mode and to find the common mode rejection ratio (CMRR)

Apparatus required

1 Power Supply

2 CRO

3 Function Generator

4 Transistors - BC107 -1 no

5 Resistors - 1KΩ - 2 nos

470Ω -1 no

Formula

CMRR = Ad Ac

CMRR in dB = 20 log Ad Ac

Ad = Differential mode gain

Ac = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals

Hence it is called differential amplifierV1 and V2 are input voltages Vo is proportional to

difference between two input signals

If we apply two input voltages equal in all respects then in ideal case output should be

zero But output voltage depends on the average common level of the inputs Such an average

level of two input signals is called common mode signal

Higher the value of CMRR better the performance of the differential amplifier To

improve CMRR we have to increase differential mode gain and decrease common mode

gain

ExNo 6 DIFFERENTIAL AMPLIFIER

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Model Calculation

For common mode signal

Gain Ac = Vo Vi

Ac =

For differential mode signal

Gain Ad = Vo Vi

Ad =

CMRR = 20 log (Ad Ac)

=

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Procedure

1 Connections are given as per the circuit diagram

2 Set Vi=5mV and note down Vo in both differential mode amp common mode

3 Calculate the gain for both the modes

4 Calculate CMRR

Formulae

For common mode signal Gain Ac = Vo Vi

For differential mode signal Gain Ad = Vo Vi

Common Mode Rejection Ratio CMRR = 20 log (Ad Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode

and the corresponding gains are obtained and the CMRR is calculated

CMRR =

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Circuit diagram

Vcc=12V

Rc = 47KΩ

R1 = 61KΩ

1microF

- +

CRO

Vi= R2= 10KΩ +

10mv ` RE 100microF

1KΩ -

Pin Diagram

Bottom view of BC 107

E

B

C

3-d view

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Ex no 7 CLASS - A AMPLIFIER

Date

Aim

To design and construct a Class ndash A power amplifier To observe the output waveform

and to measure the maximum power output and to determine the efficiency

Apparatus required

1 Transistor - BC107 - 1

2 Resistors - 1KΩ47KΩ61KΩ10KΩ(all are frac14 watts)

3 Capacitors - 1microf100microf(all are electrolytic)

4 CRO - (0-20MHz)

5 AFO - (0-1MHz)

6 Regulated Power Supply

7 Breadboard amp Connecting Wires

Bias design

Since voltage amplification is done in the transistor amplifier circuit We as equal drops

across VCE amp load resistance RE The quiescent current of 1mA is assumed we assume a

standard supply of 12V

Drop across RE is assumed to be 1Vthe drop across VCE with a supply of 12V is given by 12V-

1V=11V

It is equal to 112=55V

Now the voltage across the resistance RE is 55V

VCE = 55V

VC = 55V

IC = 1mA

RC = 55V1mA = 55KΩ

Instead of using 55KΩ We can use a standard value of 47KΩ

It is assumed that RBB (βdc+1) = RE 10

Hence RBB (βdc+1) is neglected when compared RE

Hence VBB = IERE+VBE

Hence VBE is neglected when compared to IERE

Hence IE = VBB RE

DESIGN OF R1 amp R2

Voltage drop across RE = VRE = 1V

Drop across VBE = 07V

Drop across the resistance R2 = VBE +VRE = VR2

VR2=17V R2 is assumed to be 10KΩ

VCCR2 (R1 + R2 ) = VR2

1012KΩ (R1+10KΩ)=17V

R1=605Vcong61KΩ

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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gain (dB)

A

0707 A

f L f h f (Hz)

Tabular column

VI =

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

Model graph

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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983166 983091983092 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Theory

The Power amplifier is said to be class-A amplifier if the Q-point amp the input signal are

selected such that the output signal is obtained for a full input cycle For this position of the Q-

point is approximately at the midpoint of the load line

For all the values of input signal the transistor remains in the active region ampnever enters into

cut-off or saturation region When an ac input signal is applied the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally The collector current flows for

360deg(full cycle)of the input signal In other words the angle of the collector current flow is 360deg ie one full cycle

Procedure

1 Connect the circuit as per the circuit diagram

2 Set VS=10mV using AFO

3 Keeping the input voltage constant vary the frequency from few Hz to 1MHz in regular steps

amp note down the correspondingly output voltage

4 Plot the graph gain Vs frequency

5 Calculate bandwidth from the graph

Result

The class-A amplifier is designed constructed and the output waveform is observed The

maximum power output and the efficiency are determined

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983166 983091983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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983166 983091983092 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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983166 983091983094 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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Circuit diagram

Pin Diagram

Bottom view of BC 107 BC 178

E

B

C

3-d view

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Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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983166 983091983094 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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7182019 Electronic Circuit 1 manual

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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983166 983091983092 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Date

Aim To design and construct a Class ndash B (complementary symmetry) power amplifierTo

observe the output waveform with crossover Distortion and to measure the maximum power

output and to determine the efficiency

Apparatus required

1 Power Supply - (0 ndash 30) V

2 CRO - (0 ndash 20) MHz

3 Function Generator - (0 ndash 1) MHz

4 Resistor - 47 KΩ - 1No

1 KΩ - 1No

5 Transistors - BC 107 - 1No

BC 178 - 1No

Theory The figure illustrates a Class ndash B Power Amplifier which employs one PNP and one

NPN transistor and require no transformed This type of amplifier uses complementary

symmetry ie the two transistor have identical characteristics but one is PNP and the other

NPN

Its operation can be explained by referring to the figure When the signal voltage is

positive T1 (the NPN transistor) conducts while T2 (the PNP transistor) is cut off When the

signal voltage is negative T2 conducts while T1 is cut off The load current is

iL = ic1 ndash ic2

some advantages of the circuit are that the transformer less operation saves on weight and

cost and balanced push ndash pull input signals are not required The disadvantage is obtaining pause

of transistor matched closely enough to achieve low distortion

Procedure

1 Connect the circuit as per the diagram

2 Set VS = 50mV(say) using the signal generator

3 Keeping the input voltage constant vary the frequency from 0Hz to 1MHz In regular

steps Note down the corresponding output voltage

4 Plot the graph ie gain (dB) Vs frequency (on a semi ndash log graph)

ExNo 8 CLASS ndash B POWER AMPLIFIER

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Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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983166 983091983094 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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7182019 Electronic Circuit 1 manual

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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7182019 Electronic Circuit 1 manual

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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983166 983091983093 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

Tabular column

VI = 50 mV I = 1 mA

Frequency

(KHz)

V0

(mV)

Gain = V0 Vi Gain (dB) = 20 log V0 Vi dB

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7182019 Electronic Circuit 1 manual

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983166 983091983094 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 3744

983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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983166 983091983096 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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7182019 Electronic Circuit 1 manual

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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7182019 Electronic Circuit 1 manual

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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7182019 Electronic Circuit 1 manual

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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7182019 Electronic Circuit 1 manual

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(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983091983094 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Formulae

minusΠ

=Vcc

V Efficiency

min1

4η

Π=

2

2

2

1

L R

VccPowergain

Result

Thus a Class ndash B (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 3744

983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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7182019 Electronic Circuit 1 manual

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983166 983091983096 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 3944

983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4044

983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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7182019 Electronic Circuit 1 manual

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4344

983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983091983095 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Half Wave Rectifier without filter

12

1N 4007 + +

500Ω -100 micromicromicromicroF 25V

230 V 0 R Vdc - Vac

12

Half Wave Rectifier with filter

12

1N 4007 +

500Ω 100 micromicromicromicroF CRO

230 V 0 R - 25 V

Vac

12

Circuit diagram

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7182019 Electronic Circuit 1 manual

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983166 983091983096 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 3944

983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4044

983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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7182019 Electronic Circuit 1 manual

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4344

983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

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7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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983166 983091983096 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 9 HALF WAVE RECTIFIER

Date

Aim

1 To design a Half wave rectifier with simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer

2 Connect the half wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both AC amp DC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4344

983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983091983097 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo (V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4044

983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

wwwVidyarthipluscom

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7182019 Electronic Circuit 1 manual

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4244

983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4344

983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983092983088 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

(ii) With capacitor

1 Connect the half wave rectifier with filter circuit as shown in fig

2 Assume r= 10 of ripple peak-to-peak voltage for R= 500Ω Calculate C using the

formula r = 12radic3fRC

3 Connect CRO across load

4 Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the

X-axis

5 Switch the CRO into DC mode and observe the waveform

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30)1A

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7182019 Electronic Circuit 1 manual

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983092983089 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Circuit diagram

Full Wave Rectifier without filter

12V

D1 D2

230 V 1N 4007 +

D3 D4 R + 100 micromicromicromicroF

500Ω Vdc - 25 V

-

Vac

Full Wave Rectifier with filter

12V

D1 D2

230 V 1N 4007

D3 D4 + 100 micromicromicromicroF CRO

R - 25 V

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wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4344

983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983092983090 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Ex no 10 FULL WAVE RECTIFIER

Date

Aim

1 To design a Full wave rectifier with and without simple capacitor filter

2 To measure the DC voltage under load and ripple factor and to compare with calculated

values

Apparatus Required

1 CRO - (0-20 MHz)

2 Multimeter -

3 Diode - 1N4007

4 Transformer - 230V 12 ndash 0- 12v 200 mA

5 Resistor - 500Ω-14W(carbon film resistors)

6 Capacitor - 100microF 25V7 Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor

1 Test your transformer Give 230v 50Hz source to the primary coil of the transformer

and observe the AC waveform of rated value without any distortion at the secondary of

the transformer

2 Connect the full wave rectifier as shown in figure

3 Measure the Vdc amp Vac using DC and AC Voltmeters

4 Calculate the Ripple factor r = Vac

Vdc

Note The rectifier output consists of both ACampDC components To block DC component

100microf (Electrolytic) Condenser is used

5 Compare the theoretical ripple factor with the practical ripple factor

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4344

983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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7182019 Electronic Circuit 1 manual

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983166 983092983091 983166 983109983107983090983090983088983096 983085 983109983148983141983139983156983154983151983150983145983139 983107983145983154983139983157983145983156983155 991251 983113 983116983105983106

Model graph

VI(v)

t (m sec)

Input Wave Form

VO (V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output

wwwVidyarthipluscom

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

wwwVidyarthipluscom

7182019 Electronic Circuit 1 manual

httpslidepdfcomreaderfullelectronic-circuit-1-manual 4444

(ii) With capacitor

1 To plot ripple peak-to-peak voltage Vs Idc to choose C a ripple factor of 015 is assumed

2 To get a variable load resistance a number of 500Ω 5W of resistance are to be connected

in parallel Hence Idc = Vdc ( N X 500) Where N is number of 500Ω resistances

connected in parallel

3 Plot the graph Idc Vs ripple peak to peak

4 The above steps are repeated for the various values of capacitance

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values

Ripple Factor

Theoretical Practical

Specifications

1 Diode 1N4007 (700V- PIV Idc = 1A)

2 RPS (0-30) 1A

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