electromechanical diode cell scaling for high-density ... · of the memory array and thereby lowers...

1382 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 5, MAY 2014

Electromechanical Diode Cell Scaling forHigh-Density Nonvolatile Memory

Louis Hutin, Member, IEEE, Wookhyun Kwon, Member, IEEE, Chuang Qian,and Tsu-Jae King Liu, Fellow, IEEE

Abstract— A simple electromechanical diode nonvolatile mem-ory (NVM) cell design was recently proposed and demonstratedto be well suited for implementation in a cross-point memoryarray architecture. In this paper, a scaling methodology for thisnew NVM technology is developed with the aid of a calibratedanalytical model. A nanoelectromechanical NVM cell (with20-nm minimum feature size) is projected to operate with voltagesbelow 2 V and sub-1-ns programming time.

Index Terms— Microelectromechanical devices, nonvolatilememory.

I. INTRODUCTION

CROSS-POINT memory technology is a potential suc-cessor to flash memory technology for high-density

nonvolatile information storage applications [1], since it pro-vides for a compact cell layout area of 4F2 (where F isthe minimum half-pitch) and can be more amenable to 3-Dintegration. Programmable resistance devices, such as phase-change memory [2] and resistive RAM [3], have been exploredfor cross-point memory application. However, unless a selectordevice with rectifying behavior is incorporated at each cross-point, sneak leakage paths through unselected cells during aRead operation can reduce the sensing margin between highresistance state and low resistance state. This limits the sizeof the memory array and thereby lowers the memory areaefficiency [4], [5].

Recently, a nonvolatile electromechanical diode memorycell design was proposed to eliminate the need to separatelyincorporate selector devices within a cross-point memory array[6], [7]. In this paper, the Set voltage of the electromechanicaldiode cell is modeled analytically, design requirements fornonvolatile operation are discussed, and a methodology forscaling the cell to nanometer-scale dimensions while main-taining a reasonable operating voltage is developed.

II. ELECTROMECHANICAL DIODE

MEMORY CELL CONCEPT

Fig. 1 shows the operating principle of this device, which isan electrostatic gap-closing actuator consisting of a movable

Manuscript received December 6, 2013; revised February 22, 2014;accepted March 13, 2014. Date of current version April 18, 2014. This workwas supported by NSF under Award 0939514 and Award EEC-0832819. Thereview of this paper was arranged by Editor Y.-H. Shih.

L. Hutin is with CEA-Leti, Grenoble 38054, France (e-mail:[email protected]).

W. Kwon is with Samsung Electronics, Seoul 442-373, Korea (e-mail:[email protected]).

C. Qian and T.-J. K. Liu are with the Department of Electrical Engineeringand Computer Sciences, University of California at Berkeley, Berkeley,CA 94720 USA (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2014.2312612

Fig. 1. Conceptual cross-sectional illustrations of the electromechanicaldiode memory cell structure and its I–V characteristics. (a) Reset state, Setoperation. (b) Set state, Hold operation. (c) Set state, Reset operation. (d) Tosense the state of the cell, a small forward-bias Read voltage (VRead) isapplied; no current flows if the cell is Reset (blue line), whereas significantcurrent flows if the cell is Set (red line).

element of the word line (WL) suspended over a fixed bit line(BL); the WL and BL comprise materials of different workfunctions (e.g., high-work function p-type semiconductor andlow-work function n-type semiconductor). As fabricated, anair gap separates the WL from the BL so that no current canflow through the cell [Fig. 1(a)].

In order to program the cell into the Set state [Fig. 1(b)],a reverse-bias voltage pulse (VSet) greater than the beam pull-in voltage (Vpull−in) is applied between the WL and BL toinduce an attractive electrostatic force that actuates the WLinto contact with the BL. It should be noted that, since it isan applied voltage (and not current) that is required to actuatethe WL, a current-limiting scheme can be used to reduce theenergy consumed during the Set operation [6].

Due to their work function difference, charge is transferredand a built-in electric field is locally established when theWL comes into contact with the BL. If the electrostaticforce (Felec) due to this built-in electric field, together withthe surface adhesive force (Fadh), is greater than the springrestoring force (Fres) of the deformed beam, then the WL will

0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

HUTIN et al.: ELECTROMECHANICAL DIODE CELL 1383

Fig. 2. Circuit schematic for an electromechanical NVM diode array. Thecross-point cell between WL’ and BL’ is selected.

remain in contact with the BL when the applied voltage iszero [Fig. 1(b)], i.e., the cell has two stable states. Ideally, toreset the cell to its initial state, a forward-bias voltage pulse(VReset) is applied between the WL and BL to counteract thebuilt-in electrostatic force of the p-n diode [Fig. 1(c)] so thatFres > Felec + Fadh and therefore, the WL beam is actuatedout of contact with the BL.

Fig. 1(d) shows exemplary current versus voltage (I–V )curves corresponding to the two states of the electromechanicaldiode memory cell. In the Reset state, ideally no currentflows through the cell since the WL and BL are separatedby an air gap (in practice, some nonzero leakage currentcan flow along the surface or through the isolation dielectricbetween the WL and BL). In the Set state, the cell exhibits therectifying behavior of a diode. To read the state of the cell,a small forward-bias voltage (VRead)—smaller than the beamrelease voltage (VReset)—is applied; significant read current isindicative of a cell in the Set state, whereas (nearly) zero readcurrent is indicative of a cell in the Reset state.

The circuit schematic of an electromechanical diode mem-ory array is shown in Fig. 2. The cell in the dashed circle isin the Set state (stuck-down WL), so that it comprises a p-ndiode, whereas the other cells are in the open-circuit Resetstate (suspended WLs). As fabricated, all of the cells are inthe open-circuit Reset state.

III. PROTOTYPE ELECTROMECHANICAL

DIODE MEMORY CELL

The process used to fabricate the first prototype electro-mechanical memory array is detailed in the following. Keyfabrication steps are: 1) phosphorus in situ doped poly-Sideposition at 550 °C (100 nm, 85 �/�) onto the insulatingsubstrate (a silicon wafer coated with 100-nm Al2O3) followedby sacrificial oxide [30-nm Low-temperature oxide (LTO)]deposition at 450 °C; 2) BL formation (lithography and reac-tive ion etch, RIE); 3) silicon-nitride [Plasma-enhanced chem-ical vapor deposition (PECVD) SiNx ] deposition; 4) SiNx

spacer formation (RIE)—thinning the LTO due to overetch;5) boron in situ doped poly-Si0.4Ge0.6 deposition at 450 °C(100 nm, 300 �/�) and WL formation; and 6) selectiveremoval of sacrificial oxide using Hydrofluoric acid (HF)vapor. Scanning electron microscopy (SEM) images of the fab-ricated cells comprising 4-μm × 4-μm WL beams are shownin Fig. 3. The thickness of the sacrificial LTO layer between

Fig. 3. Left: Bird’s-eye SEM view of the fabricated electromechanical NVMdiode array. Right: cross-sectional scanning electron micrograph of a cellbefore removal of the sacrificial oxide [7].

Fig. 4. Measured current versus BL voltage characteristics of a prototypeelectromechanical diode memory cell.

Fig. 5. WL beam of an electromechanical diode memory cell can be modeledas a stiff parallel-plate capacitor suspended by two fixed-guided cantileverbeams.

the BL (n-type poly-Si) and WL (p-type poly-Si0.4Ge0.6)is ∼13 nm.

Fig. 4 shows measured current versus applied BL voltage(VBL) characteristics of a prototype electromechanical diodecell in the Set and Reset states [7].

As reported in [7], the Set time is ∼2 μs for the prototypecell, which is in good agreement with a simple estimation ofthe beam pull-in time as the quarter-period of the fundamentalmode of oscillation.

IV. SET VOLTAGE MODELING

The WL beam can be modeled as a stiff plate of length ld

and width w suspended by two fixed-guided cantilever beamsof length l and width w [8], as shown in Fig. 5. The effective


Fig. 6. Comparison of predicted (filled circles) and measured (open circles)values of the WL beam pull-in voltage. FEM-extracted beam profiles for theSet state (not shown) indicate a ratio L/ld = 6. The analytical model (solidline) offers a good fit to FEM simulations (diamonds) with α = 4. Stress-induced buckling of the SiGe WL beam results in an actuation gap thickerthan the sacrificial oxide thickness.

spring constant of the cantilever beams is

km = 2Ewt3/ l3 (1)

where E is the Young’s modulus and t is the thickness of thecantilever beams. The pull-in voltage (Vpull−in) represents theminimum value of VSet

Vpull−in = 2g

3

√km

1.5C0 · α (2)

where g is the thickness of the actuation gap, C0 = ld · w ·ε0/g is the parallel-plate capacitance of the stiff plate, and αis an empirical constant compensating the underestimation ofboth C0 and km for the beam displacement at which pull-inoccurs (g/3).

As shown in Fig. 6, the predicted values of VSet assumingan actuation gap thickness ∼13 nm (equal to the thickness ofthe sacrificial LTO) do not match the experimentally measuredvalues. This discrepancy is explained by upward buckling ofthe WL beam upon release, due to residual compressive stresswithin the poly-Si0.4Ge0.6 [9]. By comparing the measuredversus predicted values of Vpi as a function of actuation gapthickness g, the buckling distance can be estimated to 26 nm.The simple analytical model given by (2) can reasonably fitthe experimental results, using the parameter values α = 4,l = 1.67 μm, and ld = 0.67 μm (i.e., total length of themovable WL L = 4 μm and L/ ld = 6), and well matches3-D finite element method (FEM) simulation results [10].

V. NONVOLATILITY AND RESET OPERATION

In this section, we consider the influence of the beam designparameters on the electrostatic, spring, and adhesive forcesin the Set state (Felec, Fres, and Fadh, respectively). For anelectromechanical diode to function as shown in Fig. 1

Fadh < Fres < Fadh + Felec. (3)

Fig. 7. (a) εmax as a function of the active dopant concentration (assumedto be symmetrical about the contact interface) for various interfacial SiO2thickness values (0, 1, and 2 nm). (b) Decay of the electrostatic force per unitarea as a function of surface separation, for various dopant concentrations.

The right-hand side inequality is the condition that allows thebeam to remain in the Set state without an applied voltage[i.e., for nonvolatile memory (NVM)], while the left-hand sideinequality is the condition that allows the position of the beamto be Reset by applying a (relatively large) forward bias

Fres = km · g. (4)

In the case of the prototype cell and assuming L/ ld = 6(derived from FEM simulation), (1) and (4) yieldFres = 9.4 μN. To reasonably estimate Felec and Fadh,it is useful to distinguish between the apparent contact area(Atot), which is equal to w · ld for the diode cell, and thereal contact area (Ac) which is cumulative across all of thecontacting asperities

Felec,contact = Ac ·∫

depletion regionρ(x)ε(x)dx (5)

where ρ(x) is the charge density and ε(x) is the electric fieldwithin the depletion region of the p-n diode. Assuming thatthe dopant concentrations within the WL and BL are uniformand that the WL and BL are not fully depleted, (5) can besimplified to

Felec,contact

Ac= εS · ε2

max (6)

where εs is the dielectric permittivity of the semiconduc-tor, and εmax is the peak electric field at the junction.|εmax| = qNDxn/εs = q NAxp/εs where ND (or NA) is thedonor (or acceptor) concentration and xn (or xp) is the widthof the depletion region on the n-side (or p-side). Fig. 7(a)shows that εmax is <4 MV/cm with zero applied voltage, foractive dopant concentrations below 1020 cm−3, and it is evenlower if the contacting surfaces are covered by a thin nativeoxide.

Fig. 7(b) shows how the built-in field-generated electrostaticforce per unit area decreases with increasing air-gap separationbetween the contacting surfaces. For very heavily doped films(N = 2 × 1020 cm−3), the pressure drops by almost two


Fig. 8. Attractive forces versus Ac /Atot ratio using the dimensions of theprototype cell, assuming active dopant concentration N = 2 × 1020 cm−3,contacting surface roughness Davg = 2 nm, and no native oxide.

orders of magnitude at 2-nm separation. Roughly speaking,this means that if the separation in the noncontacting regionsof the diode in the Set state is 2 nm on average due tosurface roughness, Felec,noncontact becomes predominant forAc/Atot < 0.01.

We consider that the van der Waals force is dominant forestimating Fadh

Fadh = H · Atot

6 · π · (D + D0)3 (7)

where H is the Hamaker constant (H = 250 zJ for Si [11]),D is the contact separation, and D0 = 0.165 nm is an effectivecutoff distance in the continuum approximation including thecontacting limit case [12]. We decompose (7) into two terms,introducing Davg as the average separation in the noncontact-ing regions

Fadh = FvdW,contact + FvdW,non−contact

= H · Ac

6 · π · D30

+ H.(Atot − Ac)

6 · π · (Davg + D0)3 . (8)

For illustration purposes, Fig. 8 plots the attractive forces asa function of the Ac/Atot ratio, using the dimensions of theprototype cell, assuming no interfacial oxide, an active dopantconcentration of 2 × 1020 cm−3 on each side of the junction,and Davg = 2 nm. The area ratios corresponding to the desiredrange of operation can be identified graphically as 5–8×10−4.

VI. CELL SCALING CONSIDERATIONS

Memory cell miniaturization is necessary to achieve highstorage density. Therefore, a methodology for scaling anelectromechanical diode NVM cell to nanometer-scale beamdimensions with reasonably low Set voltage is developed inthis section.

A. Cell Design for Nonvolatile Operation at the Nanoscale

As the lateral dimensions and thickness of the WL beam arereduced, Ac/Atot will increase toward unity so that attractiveforces in the contacting regions will become the dominantcomponent of Fadh and Felec. In this regime, Felec will bea small fraction of Fadh (see Fig. 8 for Ac/Atot > 0.01).

This implies that Fadh must be within ∼1% of Fres to achievenonvolatile operation (i.e., for Felec + Fadh > Fres). Thiswould require a precise manufacturing process to achievehighly uniform beams with tightly controlled effective springconstant and as-fabricated air-gap thickness, and reproduciblecontacting surface properties (roughness, Hamaker constant).Furthermore, extremely high active dopant concentrations(necessary to achieve large Felec) can result in significantreverse-bias diode current due to (trap-assisted) band-to-bandtunneling, which degrades the rectifying behavior of the cellin the Set state. Thus, it may be more practical to engineer thecell such that Fadh > Fres to achieve nonvolatile operation, andto use a separate overlying counter-electrode (e.g., a conduc-tive microshell similar to the cap in [13]) to apply electrostaticforce in the same direction as the spring restoring force inorder to Reset the cell. This would eliminate the requirementfor the built-in electric field of the diode in the Set state to bevery large, providing more design flexibility to achieve a largerectification ratio and allowing the electromechanical diodememory cell concept to be extended to Schottky junctions sothat a metallic beam material with lower stiffness can be usedto achieve lower Set voltage as well as lower parasitic cell-access resistance. It would also eliminate direct current flowduring a Reset operation, for lower power consumption.

B. Cell Scaling Guidelines

As the lateral dimensions of the cell are scaled down, thevertical dimensions (i.e., the beam thickness t and actuationgap thickness g) also must be reduced to maintain a low Setvoltage, as can be deduced from (1) and (2). If Felec and Fadheach scale with the apparent contact area (w · ld) [17], [18],then the ratio of counteracting forces in the Set state is

Felec + Fadh

Fres∝

(l

t

)3

· ld

2E · g. (9)

Note that this ratio is nominally independent of the beamwidth (w).

From (9) it can be seen that, as the cantilever beam length (l)and diode length (ld) are scaled down together, the thicknessesof the cantilever beams (t) and actuation gap (g) should bescaled down proportionately in order to maintain this ratio.

In consideration of manufacturability and the depletiondepth (∼4 nm), a reasonable lower limit for the beam thicknessis ∼5 nm. Due to practical limits for thickness scaling,then, a reduction in Young’s modulus (E) eventually will benecessary to enable beam-length scaling to well below 100 nm.Quantum-mechanical tunneling (resulting in undesirable cur-rent flow through a cell in the Reset state) sets a lower limitfor the gap thickness, to ∼2 nm.

If the beam thickness and/or gap thickness are no longerscaled down together with the length, the peak strain withinthe beam will increase and hence the material strain limit of theWL will become another practical consideration. Fig. 9 showsthat the longitudinal displacement profile of a doubly clampedbeam in the Set state can be reasonably well mimicked by asimple cosine function

z(x) = g

2

(1 + cos

(2πx

L

)). (10)


Fig. 9. (a) 3-D FEM simulation of an aggressively scaled memory cell inthe Set state. (b) Comparison between the longitudinal displacement profileobtained from FEM simulation and the simple modified cosine approximationgiven in (10).

The strain is maximal at the surface of the beam

εsurface(x) = t

2·∣∣∣∣ d2z

dx2

∣∣∣∣ =∣∣∣∣∣ t

2· g

2

(2π

L

)2

cos

(2πx

L

)∣∣∣∣∣ (11)

εsurface,max = t · g

4

(2π

L

)2

. (12)

The minimum beam length can be expressed as a functionof the vertical dimensions and the maximum allowable strainbefore plastic deformation occurs

Lmin = π

√t · g

εlim. (13)

For a 5-nm-thick polycrystalline-silicon beam (with a strainlimit of 0.93%), the minimum WL beam length is ∼105 nm foran actuation gap of 2 nm [16] (Table I). Alternative structuralmaterials such as TiNi with superior yield strain will be neededto scale the beams to shorter length. Although seeminglyinteresting due to a relatively high compliance (E = 77 GPa)and ease of integration, Al beams should not be scaled below235 nm due to a particularly low tolerance to strain.

The usefulness of the simple analytical model describedby (2) is once again demonstrated in Fig. 10, which plotsVSet as a function of the actuation gap thickness, for variousWL beam designs. It can be seen that the analytical modelcompares well against FEM simulation results.

The calibrated analytical model can be used to project theperformance characteristics of an ultimately scaled electro-mechanical diode memory cell. Since neither them minimumvalue of VSet (2) nor the strain limit (13) nor the fundamentaloscillation period depend on w, w can be made as small as

TABLE I

WL BEAM MATERIAL PARAMETERS

Fig. 10. Projected VSet versus actuation gap size (g) for three WL beamdesigns reported in Table I. The analytical model (2) matches FEM simulationresults for selected gap values, with α = 4 and L/ ld = 6 (same parametersas for Fig. 6).

TABLE II

ELECTROMECHANICAL CELL DESIGN PARAMETERS AND PROJECTED

PERFORMANCE IN 20-nm TECHNOLOGY

possible to maximize integration density. The sole possibledownside of scaling w too aggressively is a high cell-accessresistance. Table II summarizes the performance of a unit cellemploying 5-nm-thick TiNi as the WL material; the beam hasa width w = 20 nm (minimum lithographic feature size) andtotal beam length L = 50 nm.

The analytically derived VSet is matched by FEMsimulations as shown in Fig. 10. The Set time is estimated tobe the quarter-period of the fundamental mode of oscillation.These findings indicate that a scaled electromechanical diodecell can be operated with lower voltage and faster speed thana comparably sized flash memory cell.


VII. CONCLUSION

The electromechanical diode cell design can be scaled to20-nm minimum lateral dimension by following an appropriatescaling methodology in consideration of various practicaland fundamental limits. Low-voltage (<2 V) and high-speed(subnanosecond) operation are projected using a calibratedanalytical model as well as 3-D FEM simulations. Thesefindings indicate that electromechanical diode technology ispromising for high density storage beyond the limits of con-ventional flash memory technology.

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Louis Hutin (M’11) received the Joint Interna-tional M.S. degree in micro and nanotechnologiesfrom the Grenoble Institute of Technology, Greno-ble, France, Politecnico di Torino, Torino, Italy,and École Polytechnique Fédérale de Lausanne,Lausanne, Switzerland, and the Ph.D. degree inmicro and nanoelectronics from the Grenoble Insti-tute of Technology.

He is currently a Device Integration Engineer forBeyond CMOS applications at CEA-Leti, Grenoble.

Wookhyun Kwon (S’95–M’97) received the M.S.and Ph.D. degrees in electrical engineering fromthe Pohang University of Science and Technology,Pohang, Korea, and the University of California,Berkeley, CA, USA, respectively.

He is currently a Principal Engineer with theSemiconductor Research and Development Center,Samsung Electronics, Ltd., Suwon, Korea.

Chuang Qian received the B.E. degree in electronicscience and technology from Southeast University,Nanjing, China, and the M.S. degree in microelec-tronics from Peking University, Beijing, China. Heis currently pursuing the Ph.D. degree in electri-cal engineering with the University of California,Berkeley, CA, USA.

Tsu-Jae King Liu (SM’00–F’07) received the B.S.,M.S., and Ph.D. degrees in electrical engineeringfrom Stanford University, Stanford, CA, USA.

She is currently a Conexant Systems Distin-guished Professor with the Department of ElectricalEngineering and Computer Sciences, University ofCalifornia, Berkeley, CA, USA.

electromechanical diode cell scaling for high-density ... · of the memory array and thereby lowers...

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