Received: 3 September 2015 Revised: 20 July 2016 Accepted: 29 August 2016

DOI 10.1002/dac.3202

R E S E A R C H A R T I C L E

Electrical and optical clock and data recovery in optical accessnetworks: a comparative study

Esraa Abd El-Khaleq1 Yasmine El-Sayed2 Tawfik Ismail2* Hassan Mostafa1

1Department of Electronics and Communication,

Faculty of Engineering, Cairo University, Giza,

Egypt2Department of Engineering Applications of Laser,

National Institute of Laser Enhanced Science,

Cairo University, Giza, Egypt

CorrespondenceTawfik Ismail, Department of Electronics and

Communication, Faculty of Engineering, Cairo

University, Giza, Egypt.

Email: tismail@niles.cu.edu.eg

Funding InformationNational Telecommunication Regulatory

Authority,

SummaryClock and data recovery (CDR) is an essential part in high-speed telecommunication

systems. The CDR is used to extract the clock and re-time the received data, which

allows a synchronous operation to recover the transmitted signal. In optical access

networks, electrical CDR or optical CDR implementations can be used. However,

there are no clear guidelines or recommendations on which CDR implementation

should be adopted for better performance. These missing clear recommendations are

because the electrical CDR requires electronics design expertise whereas the opti-

cal CDR requires optical design expertise. Consequently, in this paper, an all-digital

CDR, designed and implemented on the field-programmable gate array platform,

and an optical CDR, developed by using fiber Bragg grating technology on the

OptiSystem platform, are presented. Furthermore, the integration of these 2 CDR

implementations with the optical access network is implemented, and their perfor-

mance is evaluated for various transmission rates and communication distances.

Finally, a comparative study in terms of the bit error rate between the all-digital CDR

and the optical CDR is presented.

KEYWORDS

clock and data recovery, fiber Bragg grating, field-programmable gate array, optical

access network

1 INTRODUCTION

Optical access communication networks either passive or

active are the future networks that will support the continu-

ously growing bandwidth high demand. In the next few years,

the predictable traffic on demand per subscriber will reach up

to 64 EB/mo (1 EB = 1018 bytes), which is the quadruple of

the current traffic demand.1

One of the main figures of merits of the optical com-

munication access networks is the transmission rate, which

mainly depends on the transmission distance.2,3 As the

transmission distance is increased, the signal to noise ratio

(SNR) degrades. This SNR degradation is due to several

reasons such as deduction in the signal power, shifting in

the system clock, and fiber dispersion.4 Moreover, this SNR

degradation is exponentially related to the transmission dis-

tance, which imposes some limitations on the communication

distance. Therefore, to increase the distance and accordingly

the transmission rate, the SNR degradation reasons should be

addressed, investigated, and resolved.5

Clock and data recovery (CDR) solution is considered as

one of the best techniques to increase the transmission dis-

tance and, correspondingly, the transmission rate. The CDR

is capable of synchronizing and reshaping (regenerating) the

data along the transmission line. This helps to significantly

expand the communication distance as well as boost the trans-

mission rate, achieving acceptable bit error rate (BER) values

at the receiver end.

Figure 1 shows the traditional analog CDR, which con-

sists of a voltage controlled oscillator (VCO), an analog

loop filter, and a charge pump.6,7 The design space of these

components occupies large silicon area and requires high

power consumption, which represents a large overhead on the

transceiver design.

Int. J. Commun. Syst. 2016; 1–10 wileyonlinelibrary.com/journal/dac Copyright © 2016 John Wiley & Sons, Ltd. 1

2 ABD EL-KHALEQ ET AL.

FIGURE 1 Block diagram of the analog clock and data recovery6

The loop gain (LG) of the analog CDR is as follows:

LG(s) = K𝑉 𝐶𝑂K𝑃𝐷(RCs + 1)s2C

, (1)

where KVCO is the oscillator gain and KPD is the combined

gain of the charge pump and the phase detector. For system

stability, wz = 1

RCshould be less than the loop gain cross-over

frequency to ensure that the loop transmission is 0.

An undesirable artifact of this compensation scheme is the

inevitably ineluctable peaking in the jitter transfer function

given below.8

JTF(s) = K𝑉 𝐶𝑂K𝑃𝐷(RCs + 1)s2C + K𝑉 𝐶𝑂K𝑃𝐷RCs + K𝑉 𝐶𝑂K𝑃𝐷

(2)

Assessing zeros and poles of the jitter transfer function

exposes that the closed-loop 0 always happens in the lowest

frequency of the first closed-loop pole, wp1. Therefore, the

jitter transfer function exhibits unavoidable peaking whose

magnitude is approximately equal to the ratio of wz and wp1,

and jitter peaking is equal to9,10

Jitter peaking [dB] ≈ 8.686

K𝑉 𝐶𝑂KPDCR2. (3)

In practice, the CDR must be designed to have a heavily

overdamped response, to meet stringent jitter peaking require-

ments. For the jitter peaking to be less than 0.1dB, the damp-

ing factor must be greater than 4.7. In order to achieve this

stringent small jitter peaking requirement, the clock and data

recovery circuit uses a large loop capacitor in the circuit. This

large capacitor is either implemented on-chip and occupies

a large Silicon area which is very expensive or implemented

off-chip by using a passive capacitor.8

Most of the digital CDR circuits are designed to imi-

tate the actions of analog CDRs through the use of digital

circuits. The digital CDRs can be implemented by using

application-specific integrated circuit or field-programmable

gate array (FPGA). On the other hand, all-digital CDR

(ADCDR) has better portability (i.e., migrating to other

scaled complementary metal-oxide-semiconductor technolo-

gies) and programmability compared with the analog

CDRs as the digital circuits can be synthesized from

hardware-description languages, and the design can be mod-

ified without replacing the hardware. There are 3 basic

types of CDRs: phase-locked loops–based,11 optical,12 and

oversampling-based13 CDRs. The phase-locked loops–based

CDRs depend mainly on the phase detector, which samples

the input sequence. The optical CDRs (OCDRs) can operate

at high speeds, but it can only be used over optical fiber trans-

mission. The oversampling CDRs, in which, the incoming

data is sampled at a multiple frequency of the bit rate then

the sample that most likely to be the correct data is selected

among its group of samples. Once the group of samples of

the received signal is collected, the samples that most reliably

represent each bit will be determined by a phase detection

logic which is pure digital logic. However, this type of CDRs

requires higher hardware cost than recovering the received

clock timing first and then sampling only at specific time

instants. This type of CDRs is appropriate for instantaneous

burst-mode CDR.14

Optical CDR is one of the promising techniques to be used

in the next-generation optical access networks. The OCDR

processes the received signal in the optical domain and does

not suffer from the speed limitations of the electrical domain.

The OCDR is implemented by using 2 different techniques,

self-pulsating (SP) using distributed Bragg reflector laser

(DBRL) and filtering using fiber Bragg grating (FBG). These

2 techniques provide the best performance compared with

other OCDR techniques.15,16

In this paper, the ADCDR and the OCDR are designed and

implemented. Subsequently, each CDR is integrated with the

optical access network using OptiSystem and Matlab sim-

ulation tools to study the network performance for various

distances and transmission rates. Finally, a comparative study

between the 2 CDRs’ performance is presented in the context

of the BER versus the transmission rate and the transmission

distance.

The paper is organized as follows. Section 2 presents

the proposed ADCDR architecture. The development of the

OCDR is implemented in Section 3. Section 4 presents the

simulation results and discussions of the developed designs

when integrated with the optical access network with vari-

able transmission rate and transmission distance. Finally, the

conclusions are drawn in Section 5.

2 PROPOSED ALL-DIGITAL CLOCK ANDDATA RECOVERY ARCHITECTURE

In this section, the ADCDR is designed by using the Mat-

lab Simulink simulation tool. The optical access network is

developed by using the OptiSystem simulation tool. Then,

the ADCDR is integrated with the optical access network

by calling the Matlab design in the OptiSystem platform.

OptiSystem is an optical communication system simulation

package platform. OptiSystem facilitates the processes of

designing, testing, and optimizing any type of optical links in

the physical layer of modern optical networks.17

2.1 ADCDR design

The block diagram of the proposed ADCDR architecture

is shown in Figure 2. The architecture consists of 5 main

parts—phase detector, controller, counter, delay line, and

phase selector—as shown in Figure 3. The phase detector

ABD EL-KHALEQ ET AL. 3

FIGURE 2 The proposed all-digital clock and data recovery Matlab Simulink block diagram

FIGURE 3 The all-digital clock and data recovery architecture

(PDe) is a key block in the design of the CDR, which decides

whether the clock leads or lags the data and produces early and

late signals. The used phase detector in the proposed design

is Alexander PDe. However, Alexander PDe has nonlinear

transfer characteristic compared with Hogge PDe, but it is dif-

ficult to interface the Hogge PDe with the digital path.18,19

There is an approach to connect an analog to digital con-

verter to the Hogge PDe for generating a digital output,20

but the analog to digital converter increases the complexity

of the design. The controller uses the early and late signals

and provides the control signals. The control signals deter-

mine whether the counter will count up, count down, or not

change. The delay line uses a reference clock and generates

delayed versions (different phases) of this reference clock.

The up-down counter takes the control signals from the con-

troller and generates the selection lines for the phase selector.

The phase selector selects one of the clock phases depending

on the selection lines from the counter. The recovered clock

is fed back to the phase detector to compare it with the input

data, and this operation is repeated until phase locking occurs.

The phase detector (PD) is designed by using the Alexander

phase detector.18,19 This method uses 3 data samples taken by

3 consecutive clock edges (namely, S1, S2, and S3). The PDe

determines whether a data transition is present, and whether

the clock leads or lags the data depending on the 3 samples.

FIGURE 4 The phase detector digital implementation

If there are no data transitions, the 3 samples are equal and

no action is taken. If the clock leads (early), the first sample,

S1, is unequal to the last 2 samples. Conversely, if the clock

lags (late), the first 2 samples, S1 and S2, are equal and differ-

ent from the third sample, S3. The early and late signals are

produced by using the digital circuit displayed in Figure 4.

The delay line, which consists of several delay units, gener-

ates different clock phases. The number of clock phases can

be increased by increasing the number of the delay units. If the

number of phases is increased, the locking error between the

selected phase and the data correct phase is decreased. How-

ever, there is a trade-off between the number of phases and the

locking time (i.e., as the number of phases is increased, the

locking time becomes longer). The number of clock phases

used in the proposed architecture is 16. The phase selection is

FIGURE 5 The control circuit block diagram

4 ABD EL-KHALEQ ET AL.

conducted by using a 16 × 1 multiplexer. The phase selector

block selects one of the generated clock phases depending on

the output of the counter. In the first cycle, if the clock leads

the data, the phase selector selects the first phase, while in the

next cycle, if the clock still leads the data, the phase selector

selects the second phase.

The control unit consists of an up-down counter and a con-

trol logic as shown in Figure 5. The control logic circuit takes

on the early-late signals from the phase detector and generates

2 signals. The first signal is denoted by Up_not_down signal

while the second signal is denoted by Update_not_mem sig-

nal. If the Up_not_down signal is “1,” the counter counts up,

and if it is “0,” the counter counts down. Similarly for the

Update_not_mem signal, the up-down counter takes the 2 out-

puts of the control logic and generates the selection lines for

the phase selector (16 × 1 multiplexer).

The ADCDR has been tested by applying various test vec-

tors of the data (i.e., data with different transmission rates and

phases) and ensuring that the locking occurs in each test vec-

tor case. The number of phases has been varied from 4 to 32,

and the locking error and the looking time have been calcu-

lated. The trade-off between the locking error and the locking

time is verified by varying the number of phases. In addition,

the ADCDR design has been verified on the Xilinx Vertix 5

FPGA platform. However, the interest of this work is to cal-

culate the performance of the ADCDR in the optical access

network and compare this performance to that of the OCDR.

Therefore, simulation results of the individual ADCDR are

not included in this work.

2.2 ADCDR in the optical access network

The optical link using the ADCDR is implemented by using

OptiSystem as shown in Figure 6. The receiver consists of 2

optical sources with wavelengths of 1330 and 1550 nm. The

2 signals represent the data and the clock, respectively. The

2 wavelengths are multiplexed and forwarded to an optical

fiber cable.

At the receiver end, the signals are demultiplexed. The

clock and data optical signals are converted into electrical

signals by using the photo detector (PD). Subsequently, the

electrical signals are converted to individual samples and are

sent to the ADCDR, which is designed and implemented

using Matlab Simulink simulation tool. Finally, the recovered

signal is evaluated by using the BER analyzer provided by

OptiSystem.

The implementation of the optical network is performed

by using a laser source of wavelength of 1550 nm for the

data and a laser source of wavelength of 1330 nm for the

clock. The electrical data generator and clock generator mod-

ulate the optical laser sources of wavelengths of 1550 and

1330 nm, respectively, by using the Mach-Zehnder modulator

(MZM). The MZM is controlling the output optical signal by

the applied electrical signal. For instance, if the electrical sig-

nal is logic “1,” the MZM passes the optical signal whereas

when the electrical signal is logic “0,” the MZM blocks the

optical signal and the MZM optical output power is 0. These

2 optical signals (data and clock) are multiplexed by using the

wavelength division multiplexing techniques.

Subsequently, the multiplexed signal is transmitted through

an optical fiber link of a variable length. At the receiver

end, the multiplexed signal is demultiplexed by using the

wavelength division multiplexer and converted back to the

electrical domain. The electrical data and clock signals are

applied to the ADCDR block implemented by the Matlab

Simulink. The recovered data and clock signals are applied to

the BER analyzer for performance evaluation.

3 PROPOSED OPTICAL CLOCKAND DATA RECOVERY ARCHITECTURES

In this section, 2 different designs for the OCDR are proposed

and demonstrated. The designs are based on optical filter

and SP lasers. Analysis and performance evaluation of the

2 proposed designs are performed by using the OptiSystem

simulation platform. It should be noted that the parameters

of each OCDR design are optimized to achieve the best per-

FIGURE 7 Structure of the fiber Bragg grating optical filter

FIGURE 6 The optical link with ADCDR. ADCDR indicates all-digital clock and data recovery; LPF, low-pass filter; MZM, Mach-Zehnder modulator;

OBPF, optical band-pass filter; OSC, oscilloscope; WDM, wavelength division multiplexing

ABD EL-KHALEQ ET AL. 5

formance metrics such as higher transmission rate, higher

transmission distance, shorter locking time, and lower BER.

There are many techniques that have been proposed for

implementing the OCDR, quantum dash lasers,18 SP lasers,

and filter-based techniques.19,20 In this section, we pro-

pose and develop 2 techniques for OCDR: SP using DBRL

and filtering using FBG. These methods exhibit excellent

performance and lower implementation cost compared with

those of the other OCDR methods.20

3.1 OCDR using FBG filter

The FBG filter shown in Figure 7 consists of a distributed

Bragg reflector constructed in a small part of the optical

fiber with 3 layers of refractive index, n1, n2, and n3, which

represent fiber core, cladding, and buffer, respectively. It is

designed to reflect particular wavelengths of light and allows

the rest of the wavelengths. This is done by creating a peri-

odic variation in the refractive index in the core of the fiber.

Therefore, the FBG acts as an optical filter and rejects a

certain wavelength or as a wavelength-specific reflector and

reflect it.21,22

The reflected wavelength Λ = 2neffΛ, where neff is the

effective refractive index in the fiber core and Λ is the refrac-

tive index grating period. The bandwidth of the Bragg filter

𝛥Λ is defined as the spacing between the first 2 nulls around

the reflected wavelength Λ and given by

ΔΛ =2Λ𝜂𝛿n0

𝜋, (4)

where 𝛿n0= n2 − n3 and 𝜂 is the power fraction in the

fiber core.

Figure 8 shows the block diagram of the OCDR-based FBG

filter. It consists of laser sources with wavelengths Λ1 and

Λ2 at 1550 and 1530 nm, respectively. The electrical signal

and the first laser source are forwarded to a MZM, in which

intensity modulates the laser beam according to the electrical

signal. At the same time, the second laser beam carries the

transmission clock, which is generated by a random bit gener-

ator. Therefore, the 2 optical signals are combined by using a

double wavelength division multiplexer and then inserted into

the fiber cable.

At the receiver, the multiplexed optical signals are divided

into 2 branches. One branch sends directly to photo detector

(PD) through an optical band-pass filter (OBPF) and then to

the oscilloscope (OSC1) after it passed through a low-pass

filter (LPF). The latter forwards to the OCDR, which is

composed of dispersion compensation fiber, 2 FBG filters,

circulator, and OBPF, and then the signal output of the OCDR

directs to PD, to LPF, and then finally to the oscilloscope

(OSC2) and the BER analyzer so as to measure the system

performance.

3.2 OCDR using DBRL

Distributed Bragg reflector laser is shown in Figure 9. It

consists of 2 FBGs that are separated by an erbium-doped

fiber. The FBG has a periodic structure of multiple layers

with varying refractive index to reflect a desired wavelength.

The erbium-doped fiber is pumped with a laser source and

operates as an amplification medium.23

The block diagram of the OCDR using DBRL based on SP

is shown in Figure 10. In this design, the MZM intensity mod-

ulates the received optical beam, which is generated by the

laser source at wavelength of 1550 nm with an electric signal

generated by the random bit generator. The modulated output

is forwarded to a single mode optical fiber. On the other end,

FIGURE 9 Structure of distributed Bragg reflector laser. FBG indicates

fiber Bragg grating

FIGURE 8 OCDR architecture using FBG filter. DCF indicates dispersion compensation fiber; FBG, fiber Bragg grating; LPF, low-pass filter; MZM,

Mach-Zehnder modulator; OBPF, optical band-pass filter; OCDR, optical clock and data recovery; OSC, oscilloscope

6 ABD EL-KHALEQ ET AL.

FIGURE 10 OCDR filter-based architecture using DBRL self-pulsating. DBRL indicates distributed Bragg reflector laser; DCF, dispersion compensation

fiber; FBG, fiber Bragg grating; LPF, low-pass filter; MZM, Mach-Zehnder modulator; OBPF, optical band-pass filter; OCDR, optical clock and data

recovery; OSC, oscilloscope

the incoming optical signal is split by using a 50:50 splitter.

One part sends to PD through OBPF, which converts the opti-

cal signal to corresponding electrical signal. The converted

signal is filtered by using LPF that has a bandwidth equal

to 0.75 bit rate and then forwards to the OSC1. The other

part directs to the OCDR that consists of CD, 2 FBG filters,

and erbium-doped fiber, which is pumped by a laser source

at 980 nm and 1-MW optical power. The recovered optical

signal sends to the OSC2 after it passes through PD and LPF.

4 SIMULATION RESULTSAND DISCUSSIONS

In this section, the performance evaluation of the optical link

without CDR, and with the proposed 3 types of CDR (i.e.,

ADCDR, FBG-based OCDR, and DBRL-based OCDR), is

conducted. The performance evaluation is provided in terms

of the BER for various transmission rates and transmission

distances. All the key system parameters are listed in Table 1.

4.1 Simulation setup

In the following simulations, the BER is measured by obtain-

ing the eye diagram of the received signal for the non-CDR,

FBG-based OCDR, DBRL-based OCDR, and ADCDR cases.

Figure 11 displays the resulting eye diagram for a transmis-

sion rate of 1 Gbps for the 4 cases at a distance of 150 km.

It is obvious from this figure that the ADCDR is exhibit-

ing the best eye diagram performance and hence the best

BER value. The non-CDR case shows an unacceptable per-

formance with a BER close to unity (i.e., all the received data

will be in error). The DBRL-based OCDR introduces bet-

ter eye diagram performance and BER than the FBG-based

OCDR. Accordingly, in the following simulations, this eye

diagram has been computed for (1) fixed transmission rate and

variable transmission distance and (2) fixed transmission dis-

tance and variable transmission rate. Subsequently, the BER

TABLE 1 System parameters

Parameter Value

Wavelength 1550 nm

Data rate 1-40 Gbps

Tx power 1 mW

Modulation OOK

Fiber length 1-100 km

Dispersion 16.75 ps/nm·km

Attenuation 0.2 dB/km

Detector threshold 0.4

Shot noise 2 × 10 − 8

Thermal noise 10 − 7

Medium noise 10 − 7

Background noise 10 − 7

Abbreviations: OOK, on-off keying; Tx, transmission.

has been calculated to perform the comparative study between

the non-CDR, FBG-based OCDR, DBRL-based OCDR, and

ADCDR cases. Once again, it should be highlighted that the

eye diagram is computed for each individual set of transmis-

sion rate and transmission distance and is not shown in the

following sections for space limitations and because the BER

is enough to describe the system performance.

4.2 Performance evaluation at constant rateand variable transmission distance

To evaluate the performance of the proposed CDRs, we study

the impact of changing the transmission distance while fix-

ing the data rate to 10 Gbps. Figure 12 plots the BER versus

the distance (10-70 km) at 10-Gbps transmission rate. In

this case, the transmission distance cannot be varied above

70 km because the BER reaches 1 (i.e., all data are received

in error). As expected, for a given BER, the 3 CDR designs

provide much better performance than the non-CDR case.

ABD EL-KHALEQ ET AL. 7

(A) (B)

(C) (D)

FIGURE 11 The resulting eye diagram of the received signal at 1-Gbps transmission rate and distance of 150 km for the case of (A) non-CDR, (B)

FBG-based OCDR, (C) DBRL-based OCDR, and (D) ADCDR. ADCDR indicates all-digital clock and data recovery; CDR, clock and data recovery; DBRL,

distributed Bragg reflector laser; FBG, fiber Bragg grating; OCDR, optical clock and data recovery

FIGURE 12 BER versus the distance at a constant transmission rate that equals 10 Gbps. ADCDR indicates all-digital clock and data recovery; BER, bit

error rate; CDR, clock and data recovery; DBRL, distributed Bragg reflector laser; FBG, fiber Bragg grating; OCDR, optical clock and data recovery

The DBRL-based OCDR exhibits better performance than the

FBG-based OCDR. For example, the maximum transmission

distance for the minimum BER in the case of DBRL-based

OCDR is improved by a factor of 2X compared with the

FBG-based OCDR case. This transmission distance improve-

ment at higher transmission rates is caused by the fact that

the DBRL-based OCDR uses 2 FBG modules around the

erbium-doped fiber.

8 ABD EL-KHALEQ ET AL.

It is interesting to figure out that the ADCDR provides

much higher transmission distance improvement at 10 Gbps

by factors of 5 and 2.5 compared with the FBG-based OCDR

and the DBRL-based OCDR, respectively. This shows that

using the ADCDR is very promising at higher transmission

rates compared with the 2 OCDR designs. Moreover, in the

non-CDR case, the link is not working, and accordingly, at

such a large transmission rate (10 Gbps), the use of the CDR

is not optional.

4.3 Performance evaluation at constant transmissiondistance and variable rate

Figure 13 represents the BER versus the transmission rate

when it is varied from 1 to 10 Gbps and maintains the trans-

mission distance at 50 km. At this fixed distance of 50 km,

the non-CDR, FBG-based OCDR, and DBRL-based OCDR

show approximately the same BER performance up to a

transmission rate of 6 Gbps. At transmission rates higher

than 6 Gbps, the FBG-based OCDR exhibits slightly bet-

ter performance compared with the non-CDR case whereas

the DBRL-based OCDR exhibits better performance than

the non-CDR and FBG-based OCDR cases. However, the 3

cases (i.e., non-CDR, FBG-based OCDR, and DBRL-based

OCDR) have very poor BER compared with the ADCDR case

when the transmission rate exceeds 6 Gbps. The ADCDR

shows an excellent performance up to 9 Gbps at a fixed

distance of 50 km. Additionally, Figure 14 shows the BER

versus the transmission rate (1-10 Gbps) at transmission dis-

tance that equals 100 km.

Zooming in more on Figure 14 shows that the ADCDR

performance is actually slightly worse than that for both

the OCDR cases and non-CDR cases. This is because the

ADCDR is unable to recover the data at this high transmis-

sion rate when the data are highly attenuated. Therefore, the

ADCDR should be designed carefully when integrated with

high-speed optical access networks of large distances. How-

ever, the ADCDR speed can be enhanced by using several

ADCDR blocks working in parallel. This design allows the

data to be divided into several parallel paths at lower transmis-

sion rates (i.e., a 10-Gbps data can be divided into 10 parallel

CDRs, each with a transmission rate of 1 Gbps). This can

be performed by using the programmability advantage of the

FPGA in the case of the ADCDR. It should be noted that this

parallel solution is more expensive if applied to the OCDR.

FIGURE 13 BER versus transmission rate for transmission length that equals 50 km. ADCDR indicates all-digital clock and data recovery; BER, bit error

rate; CDR, clock and data recovery; DBRL, distributed Bragg reflector laser; FBG, fiber Bragg grating; OCDR, optical clock and data recovery

FIGURE 14 BER versus transmission rate transmission length that equals 100 km. ADCDR indicates all-digital clock and data recovery; BER, bit error rate;

CDR, clock and data recovery; DBRL, distributed Bragg reflector laser; FBG, fiber Bragg grating; OCDR, optical clock and data recovery

ABD EL-KHALEQ ET AL. 9

TABLE 2 The maximum allowable transmission distance at transmission rates of 10, 25, and 40 Gbps for afixed BER of 10 − 2.00

Tx Rate, Gbps ADCDR, km FBG-OCDR, km DBRL-OCDR, km Non-CDR, km

10 58 18 30 12

25 0 4 8 3

40 0 1 5 1

Abbreviations: ADCDR, all-digital clock and data recovery; BER, bit error rate; CDR, clock and data recovery; DBRL,

distributed Bragg reflector laser; FBG, fiber Bragg grating; OCDR, optical clock and data recovery; Tx, transmission.

Quantitatively, the comparative study between the 4 cases

(i.e., ADCDR, FBG-based OCDR, DBRL-based OCDR, and

non-CDR) showing the maximum allowable transmission

distance at specific transmission rate is summarized in Table

reftable:TI. These results emphasize the following design

insights:

1. For a transmission rate of 10 Gbps, the 3 CDR types

improve the transmission distance and the ADCDR

is superior compared with the 2 OCDR types. The

DBRL-based OCDR provides better performance com-

pared with the FBG-based OCDR.

2. When the transmission rate is increased to 25 and 40 Gbps,

the ADCDR fails to provide the required recovery, and

accordingly, several parallel ADCDR designs should be

used. These parallel ADCDR blocks can be performed

by the FPGA programmability feature and can be even

configured depending on the link transmission rate.

3. At high transmission rates of 25 and 40 Gbps, the

DBRL-based OCDR and the FBG-based OCDR are still

improving the transmission distance compared with the

non-CDR case.

4. The main recommendation of this work is to use the

ADCDR for links with transmission rates lower than

10 Gbps and the OCDR for higher speeds. In case the

ADCDR is to be used at higher transmission rates, par-

allel paths of the ADCDR should be used. These parallel

paths solution is more expensive in the OCDR case com-

pared with the programmable FPGA implementation of

the ADCDR.

5. To increase the transmission rate by using ADCDR, a

SerDes technique is used.24 We successfully implemented

10 ADCDR using Vertex-7 with data rate 1 Gbps per CDR.

5 CONCLUSIONS

In this paper, we have designed and implemented 2 types of

CDRs, electrical and optical. The electrical CDR is imple-

mented by using Vertex-7 FPGA while the OCDR is imple-

mented using DBRL and FBG. The 2 designs are tested by

embedding them with single mode optical fiber, and then

we studied the performance of the ADCDR and OCDR with

data rates up to 40 Gbps over transmission distances of up to

100 km. The simulation and practical results show that the

system performance is significantly improved by using the

proposed ADCDR compared with the OCDR in transmission

rates lower than 10 Gbps. However, by increasing the data

rate to more than 10 Gbps, the OCDR is given a better perfor-

mance than ADCDR. Otherwise, it is possible to use a parallel

set of ADCDRs to increase the overall system data rate. In

this case, 10-Gbps data transmission is implemented by using

10 parallel links. Each link uses a separate CDR with data

rate of 1 Gbps. This parallel ADCDR is achieved by using

the programmability advantage of the Vertex-7 FPGA. The

future work includes implementing the proposed ADCDR

with SerDes using Vertix-7 FPGA with 32 channels and

1.25-GHz speed. This work can be used for high-speed optical

access network with 40-Gbps transmission rate.

ACKNOWLEDGMENTS

This work was funded and supported by the National

Telecommunication Regulatory Authority of Egypt and Cairo

University.

REFERENCES

1. Cisco Global Cloud Index: Forecast and Methodology, 2013-2018, Cisco

Analysis; 2015.

2. Forzati M, Gavler A. Flexible next-generation optical access. 15th Inter-national Conference on Transparent Optical Networks (ICTON); 2013;

Cartagena, Spain:1–8.

3. Wang Z, Wang M, He K, Chen X. Implementation of EPON Systems

Supporting Accurate Time Synchronization. Third International Confer-ence on Communications and Mobile Computing (CMC); 2011; Qingdao,

China:210–212.

4. Ramirez J, Nespola A, Straullu S, Savio P, Abrate S, Gaudino R. Hybrid clock

recovery for a gigabit POF transceiver implemented on FPGA. J LightwaveTechnol.. 2013;31(18):2988–2993.

5. Banjac Z, Orlic V, Peric M, Milicevic S. Securing data on fiber optic

transmission lines. Telecommunications Forum (TELFOR). 2012:935–938.

6. Walker RC. Designing bang-bang PLLs for clock and data recovery in serial

data transmission systems. Phase-Locking in High Performance Systems,IEEE Press. 2003;34:34–45.

7. Razavi B. Design of monolithic phase-locked loops and clock recovery cir-

cuits: A tutorial. In: Razavi, B.ed. Monolithic Phase-Locked Loops and ClockRecovery Circuits. Theory and Design. New York: IEEE Press; 1996. 1–39.

8. Talegaonkar M, Inti R, Hanumolu PK. Digital clock and data recovery

circuit design: challenges and tradeoffs. IEEE Custom Integrated CircuitsConference (CICC); September 2011; San Jose, California USA: 1–8.

9. Devito L. A versatile clock recovery architecture and monolithic implemen-

tation. Monolithic Phase-Locked Loops and Clock Recovery Circuits. New

York, USA: Wiley-IEEE Press; 1996:405–420.

10. Razavi B. Design of Integrated Circuits for Optical Communications. New

York: McGraw-Hill; 2002.

11. Gardner MF. Phaselock Techniques. 3rd Ed. New Jersey: John Wiley & Sons

Inc; 2005.

12. Jeon MY, Leem YA, Kim DC, Sim E, Kim S, Ko H, Yee D, Park KH. 40 Gbps

all-optical 3R regeneration and format conversion with related InP-based

semiconductor devices. ETRI Journal. 2007;29(5):633–640.

10 ABD EL-KHALEQ ET AL.

13. Sawyer N. Data to Clock Phase Alignment, Xilinx Application Note

XAPP225 (v1.2); 2007.

14. Kim J, Jeong D-K. Multi-gigabit-rate clock and data recovery based on blind

oversampling. IEEE Communications Mag. 2003; 41(12):68–74.

15. Elsayed Y, Wageeh A, Ismail T, Mostafa H. All-optical clock and data

recovery using self-pulsating lasers for high-speed optical networks. ICEAC;

March 2015: 2015; Cairo, Egypt: 1–4.

16. El-Sayed Y, Ismail T, Mostafa H. A wide FBG-based optical clock and data

recovery for optical access networks. ICTON. July 2015:2015.

17. (Available from: www.optiwave.com); May 2015. Accessed September

2016.

18. Luo Jun, Parra-Cetina J, Landais Pascal, Dorren HarmenJS, Calabretta

Nicola. 40G burst mode optical clock recovery after 52 km transmission

enabled by a dynamically switched quantum dash mode-locked laser. OpticalCommunication (ECOC 2013), 39th European Conference and Exhibitionon; September 2013; London, UK :1–3.

19. Maram R, Kong D, Galili M, Oxenlowe KL, Azana J. Ultrafast all-optical

clock recovery based on phase-only linear optical filtering. Optical FiberCommunications Conference and Exhibition (OFC), ppt. 2014;1:3.

20. von Lerber T, Honkanen S, Tervonen A, Ludvigsen H, Küppers

F. Optical clock recovery methods: review. Optical Fiber Technol.2009;15(4):363–372.

21. Kenneth O, Meltz G. Fiber Bragg grating technology fundamentals and

overview. Lightwave Technol. 1997;15(8):1263–1276.

22. Doyle C. Fibre Bragg Grating Sensors: An Introduction to Bragg Gratingsand Interrogation Techniques. Bracknell, England UK: Smart Fibres Ltd;

2003.

23. Tang XF, Cartledge JC, Shen A, Frederic VD, Duan GH. All-optical

clock recovery for 40-Gb/s MZM-generated NRZDPSK signals using a

self-pulsating DBR laser. IEEE Photon Technol Lett. 2008;20:1443–1445.

24. Ismail K, Ismail T, Mostafa H. Design and implementation of CDR

and SerDes for high-speed optical communication networks using FPGA.

ICTON; July 2016:2016; Trento, Italy: 1–3.

How to cite this article: Abd El-Khaleq, E.,

El-Sayed, Y., Ismail, T., and Mostafa, H. (2016), Elec-

trical and optical clock and data recovery in optical

access networks: a comparative study. Int. J. Commun.Syst., doi: 10.1002/dac.3202