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DIGITAL SYSTEM A digital system takes in a set of discrete information inputs and discrete internal

information (system state) and generates a set of discrete information outputs. There

are three main types of digital systems:

Combinational Logical System: a system which has no system state present and

hence Synchronous Sequential System: a system which has a system state that is updated

at discrete intervals. Asynchronous Sequential System: a system which has a system state that is

updated continuously or at any time. For both sequential systems the output may

be a function of the state alone, or both the state and input: An example of a sequential digital system would be a digital counter. It’s input could be

“Reset ” and to “ Count Up ”, it’s output could be a binary sequence representing a

number and it’s state could be the “value” of the currently dis played digit.

Other examples include the computer and other embedded systems found in mobiles,

video games, tvs, GPSs etc .

REPRESENTING INFORMATION In the natural world, information is represented by physical quantities and is often

continuous. In digital systems, the variables take on discrete values – most notably a

binary value. Binary values are represented abstractly by:

Digits 0 and 1Words False (F) and True (T)Words Low (L) and High (H)Words On and Off

When we are dealing with signals, we use voltages. We may represent it as shown. The

regions for an output high and low are smaller than the regions for input high and low to

compensate for noise and errors.

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NUMBER SYSTEMS Number systems are usually represented by a positive radix (base) and relies heavily on

the position of the numbers. A number with radix r can be represented as:

Where and . is the radix point.

BINARY NUMBERS Binary numbers (base 2) are widely used in digital systems and are represented with 0

and 1s. The binary numbers are called bits from Binary Dig its . A binary number is aweighted number:

The rightmost bit is the least significant bit (LSB) The leftmost bit is the most significant bit (MSB)

Fractional numbers can also be represented in binary by placing bits to the right of the

binary point. The left most bit (MSB) in the fractional mantissa has a weight of

. The fractional weights decrease from left to right by a negative power of twoi.e .

There are several special powers of 2:

is Kilo (K) is Mega (M) is Giga (G) is Tera (T)

Find the decimal value of the number , given in base 5.

Find the decimal equivalent of

Find the decimal equivalent of

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CONVERSION OF DECIMAL INTEGERS TO BINARY 1. Repeatedly divide integers by 2 to obtain the quotient and remainder

until a 0 quotient is obtained.

2. Read the remainders in reverse order (the last remainder is the MSB and

the first is the LSB).

CONVERSION OF DECIMAL FRACTIONS TO BINARY 1. Repeatedly multiply fractions by 2 to obtain integer product and fraction

until the fractional mantissa is 0

2. Read integer products in order

An issue arises if we try to convert to a binary number since

will continue forever. The solution to this is to specify a set

number of bits to the right of the radix point and to round or truncate to this number.

Convert to binary

So

Convert to binary

So

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CONVERSIONS BETWEEN BASES In general, to convert between bases, you need to convert (the integer and fraction

from original base) to decimal first, and then from decimal to the target base.

Converting from a decimal integer to any other base can be performed as following:

1. Repeatedly divide the number by the new radix and save the remainders. Stopwhen the quotient is 0

2. The digits for the new radix are the remainders in the reverse order of their

computation.

3. If the new radix is greater than 10, you will need to convert digits larger than 9 to

alphanumeric characters: A, B, C….. For example in hexadecimal, if the remainder is

14, then we can expressed this as E.

Converting from a decimal fraction to any other base can be performed by:

1. Repeatedly multiplying the fraction component by the new radix and saving the

integer digits that result. Stop when the fractional mantissa is 0

2. The digits for the new radix are the integer digits in the order of their computation

3. If the new radix is greater than 10, you will need to convert all integers greater than

9 to alphanumeric characters.

HEXADECIMAL The hexadecimal number system has 16 digits/alphanumeric characters as suggested by

its base. It is a convenient system since most digital systems process binary data in

multiples of 4 bits. For digits greater than 9, the numbers are assigned alphabetic

characters as shown in the table. Hexadecimal numbers usually have the prefix 0x to

indicate that it is a hexadecimal eg. 0xA5.

Decimal Binary Octal Hexadecimal00 0000 00 001 0001 01 102 0010 02 203 0011 03 304 0100 04 405 0101 05 506 0110 06 607 0111 07 708 1000 10 809 1001 11 910 1010 12 A11 1011 13 B12 1100 14 C13 1101 15 D14 1110 16 E15 1111 17 F

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OCTAL The octal number system is composed of 8 digits: 0,1,2,3,4,5,6,7. Sometimes an octal

number has a suffix Q or o. The octal number system for the first 15 numbers are

summarized on the previous table.

Octal to Binary Conversion : Each digit is translated into its corresponding 3 bit

representation and is strung together. Hexadecimal to Binary : Each hexadecimal digit is translated into its

corresponding 4 bit representation and is strung together. Binary to Hexadecimal : Group the bits into 4 bit groups starting at the radix

point and going both ways, padding with zeros as needed to make the groups

of four. Convert each group of four into a hexadecimal digit. Binary to Octal : Group the bits into 3 bit groups starting at the radix point and

going both ways, again padding with zeros as needed to make the groups of

three. Convert each group of three into an octal digit.

NON-NUMERIC BINARY CODES Any binary combination (called a word) can be assigned to any data as long as data is

uniquely encoded. We note that:

As an example, to represent the decimal digits, we need at least 4 bits –

so . Although we can arbitrarily assign codes to decimal digits or data, two

useful ways of assigning decimal digits/data into binary are binary coded decimal (BCD)

and gray code.

Convert to decimal and binary:

We will need to restate each hexadecimal digit as the corresponding four bitsstarting at the radix and going both ways:

Convert the octal number to binary and therefore to hexadecimal

Given n bits, a binary code is a mapping from a set of M elements to a subset of

binary numbers where .

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BINARY LOGIC Binary logic details with binary variables which take on two discrete values, and with the

operations of mathematical logic applied to these variables. Variables are usually

identified by letters of the alphabet: A, B, C, X,Y,Z etc but can also be represents by

strings of letters, numbers and special letters: X1, Cin RESET, CLK, En etc.

LOGICAL OPERATORS Associated with the binary variables are three basic logical operations:

AND represented by a dot ( ) or by the absence of an operator: OR represented by +: NOT represented by as:

We can define these three operations on the values 0 and 1 and present them using a

truth table:

X Y Z X Y Z X Z0 0 0 0 0 0 0 10 1 0 0 1 1 1 01 0 0 1 0 11 1 1 1 1 1

We can also represent them as a waveform:

But for the purposes of implementing them or showing them in a logic diagram, we use

the following symbols:

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REPRESENTING FUNCTIONS For the following function we see that the Boolean equation, truth table and logic

diagram represent the same function – truth tables are unique to the particular function

but expressions and logic diagrams can be manipulated so that they appear different.

Consider the function . The associated truth table and logic diagram are

shown:

X Y Z 0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 1

BOOLEAN ALGEBRA The order of evaluation in a Boolean expression is:

1. Parentheses

2. NOT

3. AND

4. OR

There are a several basic identities and properties in Boolean Algebra:

Identity Null Idempotence Complementarity

Involution

Commutativity

Associativity DistributivityAny expression can be substituted for the variables in the identities – set then .

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DUALITY Note how the identities were expressed in pairs, this is due to duality. The dual of an

algebraic expression is obtained by interchanging + and and interchanging 0’s and

1’s . The duality is not a way to manipulate expressions but rather a statement about

theorems and hence an expression cannot usually be replaced by its dual. However, any

Boolean theorem that can be proven is thus also proven for its dual due to duality.

There are also a few theorems that will be useful in the process of minimization:

Absorption Minimisation Simplification Consensus DeMorgan’s We can prove the minimization and simplification rule algebraically using the identitiesstated previously:

Then by using duality, we prove it for its dual. The consensus theorem can also be

proven, but we must make use of a trick noting that

The consensus theorem tells us that we can remove the term corresponding to the two

variables which were present in the terms with the third variable in its complemented

and un-complemented form.

DeMorgan’s theorem can be extended to any number of terms:

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STANDARD FORMS Standard forms are ways of expressing an algebraic expression in a desirable form such

that it facilities the simplification procedures for these expressions and frequently result

in more desirable logic circuit.

SUM OF P RODUCTS

The sum of products form is an equation written as an OR of AND terms. This form isuseful for a two-level circuit implementation. An example would be .A more specific SOP is the sum of minterms that have a value of 1 for the function andall the variables must be present in each minterm in its complemented or non

complemented form.

P RODUCT OF SUMS The product of sums is an equation written as an AND of OR terms and is also useful for

a two-level circuit implementation. Take for example . Amore specific POS is the product of maxterms – each maxterm present has a value of 0

for the function and contains all the input variables in its complemented or non

complemented form.

Prove

Prove

Simplify the Boolean expression

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MINTERMS Minterms are AND terms with every variable present once (in each minterm) in either

its true or complement form. For a function of n variables there are minterms –

hence every combination in a truth table has a corresponding minterm.

It’s defining characteristic is that the minterm is 1 for that combination and 0 for allothers. Hence a variable is complemented for 0 and is not complemented for 1. This is

illustrated in the following table.

X Y Z Minterm Symbol0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0

1 1 1 SUM OF MINTERMS A Boolean function can be represented algebraically from a given truth table by forming

the logical sum of all the minterms that produce a 1 in the function. Consider the

following function: To make the sum of minterms expression, we take all the combinations of inputs for

which F=1, complement the variable inputs which are 0 and sum the minterms:

MAXTERMS Maxterms are OR terms (logical sums of its variables) with every variable present once

in its complemented form if the variable input is 1 and not complemented if the input is

0. Again for n inputs, there are maxterms.

X Y Z Maxterm Symbol

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

X Y Z F0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

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P RODUCT OF MAXTERMS The product of maxterms is a function expressed as a logical product of all maxterms

where the function value is 0. For the previous function then, we have:

MINTERM -MAXTERM RELATIONSHIP From Demorgan’s theorem and the tables of the minterms and maxterms we find that

Take for example and : so if we complement it then:

FUNCTION COMPLEMENTS The complement of a function expressed as a sum of minterms is constructed by

selecting the minterms missing in the expression. Due to the minterm-maxterm

relationship described above, we can also expressed the complement of a function

originally expressed as a sum of minterms as a product of maxterms with the same

indices.

Consider the function

Then:

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K-MAPS (C IRCUIT OPTIMISATION )Finding a minimal sum of products or product of sums is difficult using Boolean algebra.

A more systematic and graphical representation of a Boolean function is the use of

Karnaugh maps or k-maps.

A k-map is a collection of squares where each squares represents a minterm. For n number of variables there are squares. Adjacent squares differ in the value of one variable (application of gray code) Alternative algebraic expressions for the same function are derived by

recognizing patterns of squares. It is essentially another way of arranging the truth table values.

A 2, 3 and 4 variable k-map is shown on the side.

COST CRITERIA There is a need to measure the complexity and performance of a logic circuit. The gate-

input cost method measures the number of inputs to the gates in a particular

implementation and is a measure of “space” since the number of inputs is roughly

proportional to the number of transistors. Consider

The has 2 inputs, has 1 input, has 2 inputs, has 2 inputs andthe logical sum of both terms has 2 inputs,making a gate input cost of 9. We can verify

this by counting the inputs in the

corresponding logic diagram.

Another method is to use a literal cost which counts the number of literals in a Boolean

expression. However it does not represent circuit complexity accurately in all cases.

Consider , it has a literal cost of 5.

SIMPLIFICATION APPROACH 1. Fill in the function values in the map

2. Form rectangular (including squared) groups o f 1’s until all 1’s have been covered.

These groups can wrap around – bottom to top and right to left. These groups must

have some multiple of 2 squares and should be made as large as possible

3. Sum together the terms corresponding to the groups in order to create a simplified

expression. This creates a sum of products solution.

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When we group terms together we are essentially finding the product of all the literals

that are common to the entire group. We are simply taking advantage of the Boolean

theorem How we should group and sum up the rectangles matter. A systematic approach allows

us to optimize the function. Consider the three variable k-map shown for the function

. We find that not all groups are needed – the less groupsthe better! We could say . We need to identifyspecific types of groups before proceeding

D E F I N I T I O N S

Implicant : A product term for which the function has the value 1 for all

minterms in the product term. Prime implicant : The largest implicant that can be formed on a k-map

governed by the rule that the number of squares must be a multiple of 2. Essential prime implicant : A prime implicant that contains at least 1 minterm

which cannot be covered by any other prime implicant.

1. Is an implicant because the group contains all 1s however it is not a prime implicant

because it can be extended to include the 1s satisfied by .2. Is a prime implicant because i t cannot be enlarged further, but is not essentialbecause all of its minterms can be covered by other prime implicants: 3. Is an essential prime implicant because the top left 1 cannot be covered by anyother prime implicant.

OPTIMISATION ALGORITHM Armed with the simplification process stated previously and with the definitions ofimplicants, prime and essential prime implicants we can optimize a Boolean function by:

1. Finding all prime implicants

2. Including all essential prime implicants in the solution (in the sum)

3. Include other prime implicants to cover all minterms not yet covered

4. Minimize the overlap between the prime implicants

A rectangle with 2 squares

represents a product of 3

literals. A rectangle with 4 squares is a

product of 2 literals A rectangle with 8 squares is a

product of one literal A rectangle of 16 squares is

always equal to logic 1

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P RODUCT OF SUMS OPTIMISATION 1. Find a SOP expression for the complement of the function by grouping the 0’s

instead of 1’s.

2. Invert the function back and apply DeMorgan’s theorem.

Find a simplified Boolean expression for the given k-map.

Essential prime implicants: Prime implicants:

Simply into POS

Collecting all the 0’s and identifying the essential prime implicants and primeimplicants:

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INCOMPLETELY SPECIFIED FUNCTIONS – DON ’ TCARES In some applications, the output of a function may not be specified for certain

combinations of input variables. These functions are refered to incompletely specified

functions .An unspecified output of a function is called a don’t care condition . This is marked with

an X on both the truth table and k- map. In the process of optimization, these X’s can be

treated as 1’s or 0’s depending on whether it is convenient to do so.

Similarly we can find an optimized POS with don’t cares in the function by grouping

together the 0’s, and where convenient the X’s can be treated as 0s.

Simply

Where convenient, we treat the X’s as 1’s. There are 2 possible groupings thatresult in 2 functions – the function values will be the same for the combinations ofinputs we care about, but will differ for the don’t cares.

Find a simplified POS with reference to the k-map.

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MULTI -LEVEL OPTIMISATION Multiple level circuits are circuits with more than two gate levels. Although these

circuits may have reduced gate inputs costs compared to two level circuits, they tend to

have longer propagation delay. A balance must be struck between gate input costs and

propagation delay.

Optimisation on multilevel circuits are performed by applying transformations to

circuits:

Factoring : finding a factored form from either a SOP or POS expression for a

function Decomposition : expression of a function as a set of new functions

Reduce the Gate Input Cost (GIC) function byfactoring.

Initial gate input cost was 17, final gate input cost is 9.

Reduce the Gate Input Cost (GIC) function by factoring and then use decomposition.Initial GIC=26. Factoring:

Decomposition: express G with a set of new functions Performing GIC:

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SUMMARY OF GATE TYPES

We shall focus our explanations on the NAND, NOR, XOR gates and 3 state buffers.

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NANDThe NAND represents Not- AND. It’s output is the inverse of AND. By applying

DeMorgan’s theorem, we can find an equivalent logic design of a NAND gate:

We can extend this for any number of inputs. Since NAND is a universal gate- a gate type

that can implement any Boolean function, we find that it is the natural implementation

for CMOS technology in terms of chip area and speed.

NOR

NOR (NOT OR) is another universal gate. We find that we can build an equivalent NORcircuit using inverted inputs to an AND gate as suggested by DeMorgans theorem:

This holds for any number of inputs.

EXCLUSIVE-OR (XOR)

The XOR gate outputs a 1 if one of its inputs are 1, but not both. The XOR operation isdenoted with :

EXCLUSIVE-N OR(XNOR)XNOR (equivalence) outputs a 1 if both of its inputs are 0, or both 1. I t is defined as:

There are several identities that apply to XOR and XNOR:

The XOR operation is commutative and associative :

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CASCADING XOR GATES (O DD FUNCTION )A XOR gate can only have two inputs. A XOR operation on three or more variables is

known as an odd function. It’s implementation is shown below.

Similarly, XNOR operations can have three or more variables and is known as an even

function. It is implemented by adding an inverter to the output of the odd function.

BUFFER A buffer is a gate with the function . It acts as an electrical amplifier used to

improve circuit voltage levels and increase the speed of circuit operation.

3-S TATE BUFFER 3-State buffer adds a third logic value – high impedance denoted as Hi-Z or Z. The input

EN (enable) acts as the control line for the buffer. A Hi-Z value behaves as an open

circuit i.e. the output appears to be disconnected. Consider the 2 three state buffers

shown.

We find that two or more Hi-Z capable gates can be connected to the output line, but

for the last two truth values, the output line will cause an electric clash – electrical

current flowing from one buffer output that is 1 will flow into the buffer output that is

at 0. This current is often large enough to cause heating and destroy the circuit.

To ensure no electric clashes occur in the circuit, we can invert one of the enable

signals. This circuit will then act as a multiplexer with control input S (select).

EN1 EN0 IN1 IN0 OL0 0 X X Z0 1 X 0 00 1 X 1 11 0 0 X 01 0 1 X 11 1 0 0 01 1 1 1 11 1 0 1 1 1 1 0

IN1 IN0 OLX 0 0X 1 10 X 01 X 1

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DESIGN P ROCEDURES 1. Specification : Write a specification for the circuit

2. Formulation : Define the inputs and output signals and derive truth tables relating

the two.

3. Optimisation : Apply two level and multilevel optimization and draw the logic

diagram

4. Technology mapping : Transform the logic diagram according to the implementation

technology.

5. Verification : Verify the correctness of the final design.

TECHNOLOGY MAPPING For the purpose of implementation we are usually required to implement various gates

using NANDs or NORs since they are the natural implementation for CMOS technology

in terms of chip area and speed. We shall see how the process of conversion to NAND

gates:

The trick is to use involution - add bubbles to the AND gates, and bubbles to the inputs

that come from the outputs of the original AND gates. Note also for an OR gate with

inverted inputs, using DeMorgan’s theorem we find this is a NAND gate:

VERIFICATION We need to find a way to check that a circuit design fulfils the specifications exactly. For

simple circuits, we can usually work backwards to derive the Boolean equations from

the circuit and hence the truth table. However, this is tedious for complex circuits. In

these circumstances, computer simulations are employed to test all possible input

combinations and verify the output correctness.

Implement the following function using NAND gates only:

Add the bubbles to the outputs of the AND gates and input of the OR gates. We findthat we no longer need the top inverter.

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BCD TO EXCESS 3 EXAMPLE SPECIFICATION We are going to design a BCD to excess 3 converter. The excess 3 code for a decimal

digit is the binary combination corresponding to the decimal digit plus 3.

FORMULATION We define the inputs to be A, B, C, D and outputs to be W, X, Y, Z since 9 can only be

represented with 4 bits and the corresponding excess 3 code is 12, which can only be

represented by 4 bits. The following is the truth table for the converter.

DecimalDigit

Input BCD Output Excess 3

0 0 0 0 0 0 0 1 11 0 0 0 1 0 1 0 02 0 0 1 0 0 1 0 13 0 0 1 1 0 1 1 04 0 1 0 0 0 1 1 15 0 1 0 1 1 0 0 06 0 1 1 0 1 0 0 17 0 1 1 1 1 0 1 08 1 0 0 0 1 0 1 19 1 0 0 1 1 1 0 0

OPTIMISATION The best way to optimize this circuit is to try two level optimization first using k-maps

then seeing if we can perform multilevel optimization.

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Notice for the Y, X and W functions we have the terms and , we can factor

and decompose:

We now draw the logic diagram corresponding to the four functions:

TECHNOLOGY MAPPING Again we use the trick with adding bubbles at the outputs of the ANDS and at the inputs

to the other gates.

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H IERARCHICAL DESIGN For large and complex designs, we use a module

approach by breaking the circuit into sub-functions.

We do this by enclosing the sub functions in blocks

and define an interface for them that specifies the

input and output signals to the block and its function.

For example we could have done a hierarchical

design for the BCD to excess-3 function as shown.

4- BIT EQUALITY COMPARATOR EXAMPLE DEFINE Using a hierarchical design, design a 4 bit equality comparator that takes two 4 bit

numbers: and outputs a one bit result E. E is 1 if all correspondingbits from A and B are equal to each other, otherwise the output from E is 0.FORMULATION & OPTIMISATION There are 8 inputs – which would mean

a row truth table. Alternatively, we

could use a hierarchical design where

we only ever compare the

corresponding bits together, so we get

a truth table of 2 inputs, and hence 4

output combinations. We when repeat

this hierarchical design for every other

corresponding two bits and combinethe results. The logic diagram is shown.

For the MX blocks, we can define the output to correspond to when the

inputs , and for all other cases . This is a XOR function:

Since E=1 when then weshould implement a NOR gate since ifany of the inputs are not equal, MX will

yield a 1 and hence, ME will yield a 0.

The only case ME will yield a 1 is whenall the inputs are 0:

Note that we could have implemented the MX sub function using XNOR since that

would yield a 1 if the inputs were equal and 0 otherwise. ME would then have to be an

AND gate.

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RUDIMENTARY LOGIC FUNCTIONS

Consider the 0-value fixing function. We can use this in the implementation of an

inverter using a NOR gate.

BUSES A group of single bit variables that are used together can be gathered into a bus – a

vector signal. We can express input signals such as those in the 4 bit equality

comparator as . Traditionally, buses are represented graphically usingthicker lines and an integer to specify their size.Intuitively, we can see how buses can make circuits clearer to read and significantly

simplify design and simulation in software. Look at how we can represent the 4 bit

equality comparator.

ENABLING FUNCTION Enabling permits an input signal to pass through to an output. We saw this with a buffer

which outputs a Hi-Z when enable is 0. With other gates, when enable is disabled, we

can also replace the output with a fixed value as shown.

EN F0 11 A

EN F0 01 A

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DECODER Decoders are circuits that convert n-bit input code to an m-bit output code with

such that each valid code word produces a unique output code-the

decoder generates or fewer minterms. Functional blocks for decoding are called to n-

to-m decoders.

We can create decoders from using inverters and AND gates as shown.

A 1- TO -2 DECODER

A 2- TO -4 DECODER

We can already see that larger decoders get far more complex since we can cascade

decoders using only 2-input AND gates:

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An algorithm exists in which we can construct a n-to- line decoder using 2-input AND

gates and inverters only.

1. Let be the number of inputs

2. 3. For each decoder resulting in step 2, repeat step 2 with equal to the valuesobtained in step 2 until k=1. For k=1, we use a 1-to-2 decoder which only consists of

an inverter.

4. The number of inverters is equal to

DECODER WITH ENABLE/M ULTIPLEXERS A decoder with enable allows all outputs to be 0 when disabled. In essence, the enable

signal adds another set of AND gate layer to the end – the same number as in the

previous layer. The inputs are the enable signal and the outputs from the previous AND

gates.

How many AND gates and inverters do we need to build a 5-to-32 decoder?

We need 5 inverters since for each signal it can be in 2 possible states.

Hence, we need, AND gates. We need 32 AND gates in thelast cascade, 32 in the second last….and 4 in the first.

X X 0 0 0 00 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

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DECODER BASED COMBINATIONAL CIRCUITS The benefit of a decoder is that any Boolean function can be implemented with a

decoder and additional OR gates. Consider a 1 bit binary adder which outputs a carry

out and sum signal – we add the three bits noting that in binary addition

Hence we can derive a truth table:

X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 1

1 0 1 1 01 1 0 1 01 1 1 1 1

From this we can find the sum of minterms for the corresponding output signals:

Since there are 8 possible input entries, a 3-to-8 decoder can be used to generate

unique outputs based on each valid code word. We can then use 2 OR gates to create

the C and S output signals since only one possible minterm part of the carry and sumfunctions can be 1 at any one time.

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ENCODERS Encoders perform the inverse operation to decoders- it takes in or fewer inputs and

has n output lines. The output generates a binary code corresponding to the input

value; typically only one of the inputs is 1 at any one time.

OCTAL-TO-B INARY ENCODER

The problem with this particular encoder design is that we have no output combination

available for the case when all the inputs are 0. Moreover, what happens if more than

one input is 1? To solve this problem we use priority encoders.

P RIORITY ENCODERS Priority encoders solve the restriction that only one input can be 1 at any time. It

outputs the binary value corresponding to the most significant input equal to 1. It also

solves the ambiguity between all inputs equal 0 and by adding a valid output.

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MULTIPLEXERS (MUX)A multiplexer selects information from one of many input lines and directs it to the

output line. A typical multiplexer has n selection inputs and information

inputs . A typical multiplexer is often simplified to a block diagram.

Y0 0 0 1 1 0 1 1

We can actually implement a multiplexer, such as a 4-to-1 multiplexer using a decoder,

2-input AND gates and a multiple-input OR gate.

To build larger multiplexers, we can cascade smaller multiplexers. For example, we can

build an 8-to-1 multiplexer: there are 8 information inputs, so we need 3 selection

inputs. We can use 2 4-to-1 multiplexers that which will choose 2 signals out of 8, then

we implement a 2-to-1 multiplexer that will choose the correct output signal.

Consider the selection input to be 110. The 4-to-1 Mux will pick and

since it must match the pattern *10. The 2-to-1 Mux will look at the MSB and determine

which input has a 1 and directs it to the output i.e . The order of S in this

circumstance allows us to easily number the inputs in order. For any other combination

of S in the multiplexers, we would need to feed in different inputs to each block.

4-to-1 multiplexer

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DEMULTIPLEXERS Demultiplexers direct information from a single input line to one of output lines and

is controlled by n control lines denoted as S.

0 0 I0 1 I1 0 I1 1 I

Demultiplexers can be implemented using a decoder with enable. The enable signal

becomes the input signal, while the inputs A become the control lines S, and the outputs

D becomes the outputs denoted Y.

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SEQUENTIAL CIRCUITS In sequential circuits, storage elements allow us to output values which are functions of

the current state and possibly even its inputs. The next state – the binary information to

be stored at the next instance is also shown to be a function of the inputs and the

present state. This is opposed to the combinational circuits we have been dealing with

that are only dependent on the current inputs.

There are two types of sequential circuits:

Mealy: Moore:

We see that a sequential circuit is specified by a time sequence of inputs, internal states

and outputs. The timing sequence may be either synchronous – the behavior is defined

from the knowledge of its signals at discrete time instances or asynchronous – the

behavior depends upon the inputs at any instant of time and the order in continuous

time in which the inputs change.

THE BASIC STORAGE ELEMENT The most basic storage element is created by using a buffer (cascading two inverters)

which exhibit a total time delay of . At time we shall define the input to the first

inverter to be 1. At it will output a 0, and the second inverter will output at

at 1, which feeds backs to the first inverter – creating a loop which maintains the

state infinitely. We find however, that there is no way to change the information in this

loop. The solution is to use NOR or NAND gates.

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SR LATCH By rearranging the previous circuit and replacing the ground signals with signals S (for

set) and R (for reset) we create a SR latch. When S=1, R=0, Q is set: Q=1, and when S=0,

R=1, Q is reset Q=0. When S=R=0, then we have a keep state, and the outputs remain

unchanged.

1 0 1 0

Set State0 0 1 0

0 1 0 1Reset State0 0 0 1

1 1 0 0 Undefined

Note that when both S and R are both 1, we have an undefined state, since it violates

the requirement that the outputs be complements of each other.

A simulation shows that a transition from the undefined state (which outputs both 0s)to the ‘keep’ state will lead to the waveforms of the output set midway between 0 and

1. This is because a race condition occurs.

The race condition describes a situation in which the output is dependent on the time

sequence of the circuit elements. Suppose the propagation delay is shorter for the

upper NOR gate, then the transition from (1,1) to (0,0) will let it output a 0, and the

second NOR gate will then output a 1. But suppose the propagation delay is shorter for

the lower NOR gate, then the lower NOR gate will first output a 1 and will cause the

upper NOR gate to output a 0. We see that the output is actually unpredictable.

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LATCH The (active low) latch is a cross coupled NAND gate. It maintains the state if theinputs are 1, and for variations in the input, the state is changed.

0 1 1 0 Set State1 1 1 01 0 0 1 Reset State1 1 0 10 0 1 1 Undefined

SR LATCH WITH CONTROL INPUT We previously designed the SR-latch with nor gates. We shall now build it with NAND

gates and add a control input which will either enable the circuit to read inputs or

disable it. Notice that the first NAND gates act as inverters and the special condition is

that when C=0, then the output from those NANDS will always be 1 – hence the

latch

following it will hold its state.

The function table of the SR latch with control is thus what was previously seen, but we

now add an extra possibility of when C=0

0 X X Q1 0 0 Q1 0 1 01 1 0 11 1 1 Forbidden state 1

D LATCH Note that the undefined state is undesirable, and a way to ensure that the inputs S and

R are never equal to 1 simultaneously is to have 1 input D and to feed it to S and feed

the complement to R. This will create a D-latch – the output will follow the input D when

C=1.

0 X Q1 0 01 1 1

1 Violates the logical equation . When transitioning from a restricted state, arace condition will result. Check http://www.faqs.org/docs/electric/Digital/DIGI_10.html

Negative Edge SR flip flop

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FLIP FLOPS Note that the latches are transparent – as soon as an input changes, shortly thereafter

the corresponding output changes to match it. Consider the D-latch connected to a

combinational circuit as shown.

We recall that the output follows D. While the clock is high, the D latch will read theinput, and output the next state. But now, an inverter from the output connects it back

to D, creating the output Y to oscillate whenever the clock is high.

Flip flops are designed to output a state based upon its preceding state and do not go

through multiple changes of state in one clock pulse. There are two ways that latches

are combined to form a flip-flop:

Master Slave: the state of the flip flop changes only when a clock pulse is not

high Edge triggered: the state of the flip flop changes on a transition from 0 to 1

(positive edge) or 1 to 0 (negative edge).

SR MASTER SLAVE F LIP F LOP By cascading 2 SR latches with controls, and inverting the clock signal for the signal SR

latch, we design a master slave flip flop. When the clock is high (C=1), the master latch

will operate and the new states propagate to Y. When the clock is low (C=0), the master

latch is disabled and the slave is enabled – and hence any changes in the SR inputs do

not affect the state of the flip flop now. The output Q from the slave latch will be

determined based upon the Y and value stored by the master latch.

The simulation shows the 1s catching behavior of the SR master slave flip flop at 125ns.

A narrow pulse to 1 occurs on S initially, and the master latch responds by changing Y to

1. Then S=0 and R=1; the master latch responds by setting Y=0 and . During this

clock cycle, the master latch “caught” both the 1 on S and on R, but since R=1 wa s

caught last, this stored state was Q=0. The simulation also shows an unknown state of Q

when SR=(1,1) which causes which then propagates to the slave.

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N EGATIVE EDG E T RIGGERED D F LIP F LOP The correct operation is for the flip flop to change states at the falling edge of the clock

(negative edge triggered) . This is achieved by replacing the master SR latch with a

master D latch.

When C=1, the master D latch is enabled and its output follows D, but when C changes

from 1 to 0, the master latch is disabled and stores the last value seen at D, and this

value is seen by the slave SR latch and changes its state accordingly. Note that any

changes to the input signal D do not propagate through until the negative edge of the

clock.

P OSITIVE E D G E T RIGGERED D F LIP F LOP Inverting the clock signal means that the last valued to be stored by the master latch will

occur on a transition of C from 0 to 1. When C=1, the master latch will be disabled, the

slave latch will be enabled and respond accordingly such that Q follows D at the rising

edge of the clock.

When we need to force a value to the output of a flip flop independent of the clock

(such as when we want to initialize a circuit to known values at start up), we use

asynchronous set and reset inputs. The following active low set and reset (to set, ,reset ) positive edge D flip flop will have these asynchronous signals fed into the

last lot of latch that makes up the slave SR latch.

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SEQUENTIAL CIRCUIT ANALYSIS In a sequential circuit, the outputs and the next state are a function of the inputs and

the present state. The following sequential circuit contains 2 D flip-flops, allowing 4

possible states: 00, 01, 10 and 11.

By convention, the current state is denoted by q, while the next state as, Q. We find that

the next state Q will be the input to D in the above circuit. From a state transition table that tells us the relationship between the inputs, outputs and the states :

Current State Next State Output

Y Y0 0 0 0 0 1 0 00 1 0 0 1 1 1 01 0 0 0 1 0 1 01 1 0 0 1 0 1 0

By looking at the next state for both X=1 and X=0, we determine the input to

(using sum of minterms):

We find that since Y is dependent on both the current state and on inputs, then it is a

Mealy model. If the outputs only depend on the states, then only 1 column for output

would suffice, resulting in a Moore model circuit.

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STATE D IAGRAMS State diagrams are diagrammatic representations of a sequential circuit. For a mealy

model , we find that each state is represented with a circuit. Each possible transition

combination is indicated with connecting arrows and are labeled in the form of

INPUTS/OUTPUTS. Then for the previous circuit, we have:

We find that the number of arrows going out from each state corresponds to the total

number of possible input combinations that can be achieved. In this case, there is 1

input X that can be 0 or 1.

For a Moore model , each state is represented with a circle and is labeled as

STATE/OUTPUT, since the output in a Moore machine is only dependent on its current

state. Transitions are represented using arrows and are labeled according to its input

combination.

Current State Next State OutputXY=00 XY=01 XY=10 XY=11

q Q Q Q Q Z0 0 1 1 0 01 1 0 0 1 1

We find that , Z=q and that there are 2 states and the output is

only dependent on the current state. So the Moore state diagram will be:

SEQUENTIAL CIRCUIT DESIGN 1. Specification: Write out what the circuit does.

2. Formulation: Draw up a state diagram or state table

3. State Assignment: Assign binary codes (try gray code)

4. Minimise the states

5. Derive the flip flop input equation bearing in mind the type of flip flop used

6. Optimise the equations

7. Technology mapping

8. Verification

At state 00, if the input is 0, goback to state 00 and output 0. Oninput 1, output 0 and go to state01.

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SEQUENCE RECOGNIZER E XAMPLE S p e c i f i c a t i o n

Design a circuit that recognizes the occurrence of the sequence 1101 at the input X

(which is read at every clock cycle). The circuit is to output Z=1 every time the last 1 of

the 1101 is detected and Z=0 otherwise.

We first recognize we need a Mealy model circuit since the output is dependent not just

on the state, but also on the input – the last “1” of 1101 causes the output Z=1.

Moreover, the circuit needs to remember what the previous inputs were.

F O R M U L A T I O N

Note that since we do not know the number of states yet, we use generic names for the

state e.g A, B, C…

1. A: Circuit initializes & has not seen anything yet:

2. B: Saw a 1 that is possible for 1101

3. C: Saw a 1 that is possible for 1101

4. D: Saw a 0 that is possible for 1101

5. ?E: Saw a 1 that is possible for 1101 or 1101

Note that we don’t actually need state E since it could also be the first 1 in the next

sequence of 1101, so in actual fact we can loop back to state B.

Consider at state A, if input is 0, then we get 0/0. At state B, if we get an input 0, then

we transit back to A. At C, if the input is 1, it could be the 2 nd 1 in the sequence e.g

11101, so we transit back to 1. At D, if the input is 0 then we need to transit back to A.

We note that the number of arrows coming out of each state is 2 – the maximum

number of input combinations.

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CurrentState

Next State Output ZX=0 X=1 X=0 X=1

A A B 0 0B A C 0 0C D C 0 0D A B 0 1

S T A T E A S S I G N M E N T

We can either assign a counting binary code, gray code or one hot (only one 1 in each

sequence with the rest being 0). We shall choose gray code for convenience: A=00,

B=01, C=11, D=10. The state transition table can then be illustrated as:

CurrentState

Next State, Output ZX=0 X=1

, Z , Z00 00, 0 01, 0

01 00, 0 11, 011 10, 0 11, 010 00, 0 01, 1

We could have alternatively used another 2 columns for the output Z as in the first state

table. If we chose to use a one hot code: A=0001, B=0010, C=0100, D=1000, then we

would need 4 D flip flops – and this tends to be more costly and some states go unused.

D E R I V I N G E Q U A T I O N S

Look at the column corresponding to we develop a k-map and optimize the result.

Similarly:

T E C H N O L O G Y M A P P I N G

Since there were 4 states, a minimum of 2 D flip flops are required.

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DESIGNING WITH UNUSED STATES There are 2 approaches that can be used to manage unused states in sequential circuits.

Consider the state transition table shown. The next states for the unused states are

labeled X and like we did previously with unused states, we group them as either a 1or a 0, depending on convenience :

Alternatively, we can label these unused states as a valid initialization next state . For

example, send all unused states back to 001.

The approach best to take depends on the situation. Although both circuits perform the

same function for the valid inputs, they will differ at the unused states. If we can be

certain that the machine will never enter an undefined state, then we can use don ’t

cares.

By fixing the next state for unused state generally results in a more complex circuit but

assures that if we do end up in an undefined state, it will transit back to a valid one.

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MEALY & MOORE CONVERSION MO O R E TO ME A LY

The trick with the conversion of a state diagram is to pull the outputs back in all

incoming transitions.

We modify the state transition table by representing the NEXT STATE/OUTPUT in two

columns. Note that the output should correspond to the next state . Consider the

following Moore to Mealy example. We pull the outputs to the incoming transitions for

the state diagram and shift the outputs in the state transition table to the next state/output columns.

T

h

e

r

The functionality of both the Moore and Mealy function is the same and only differs in

the implementation. This could result in the timing of transitions to be different.

Current State Next State Output Z Current State Next State, Output ZX=0 X=1 X=0 X=1

A A B 0 A A, 0 B, 0B D B 0 B D, 0 B, 0C D B 1 C D, 0 B, 0D A E 0 D A, 0 E, 0E D C 0 E D, 0 C, 1

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STATE MINIMISATION Using an implication chart – a table with all possible state pairs we can minimize the

number of states.

1. Cross out entries that have unequal outputs for all input combinations

corresponding to each state pair.2. For each of the remaining entries, write the matching next state pairs for

all input combinations

3. Cross out entries that have non-equivalent next state pairs in them (by

identifying state pairs already crossed out). Keep iterating until no more

entries can be crossed out.

4. Two states are equivalent if they have the same output and transition to

the same states for all input combinations – combine these states

together.

Consider the mealy state transition table shown. We shall first cross out all the state

pairs with unequal entries: since for X=1, the outputs are 0 and 1 respectively …We then write the next state pairs in each square.

Notice for the state pair A-C, if these states are to be equal, then states B and D must be

equal, but as we can already see, this is not the case. So we cross the square A-C out.

We continue iterating until no more squares can be crossed out, as shown on the left.

So we end up having:

Rebuilding our state table (taking care that the next states exist) now, we get:

CurrentState

Next state, Output

X=0 X=1A B, 0 A, 0B C, 0 B, 1C A, 0 B, 0

CurrentState

Next state, Output

X=0 X=1A B, 0 A, 0B F, 0 E, 1C D, 0 B, 0D B, 0 A, 0E C, 0 B, 1F A, 0 E, 0G E, 0 G, 0

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OTHER FLIP FLOP TYPES JK F LIP F LOP The JK flip flop has a similar behavior to the SR flip flop with the exception that the input

(1,1) is allowed and complements the current state.

From the characteristic table, we can map the

values to a k-map and derive the characteristic

equation

The excitation table is a table that represents the

relationship between the current and next state and the JK values required. This table

will be useful in designing JK flip flop sequential circuits. This can be derived from the

characteristic equation.

An interesting concept is that we can implement a JK flip flop using a D flip flop, by

noting that D=Q in such a sequential circuit.

T OGGLE F LIP F LOP The T flip flop is equivalent to the JK flip flop with J and K tied

together. When T=0, it stores its state, and complements it

when T=1. The characteristic equation can be derived:

The excitation table will be:

q Q J K0 0 0 X0 1 1 X1 0 X 11 1 X 0

q Q T0 0 00 1 11 0 11 1 0

J K Q0 0 q0 1 01 0 11 1

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IMPLEMENTATIONS USING JK FLIP FLOPS Implement the following circuit using JK flip flops.

We first begin by drawing up the excitation table and identifying the JK inputs for each

Q-input combination. For example, let us consider when x=0:

0 0 0 X0 0 0 X1 1 X 01 0 X 1

We do the same for when X=1 and for . The resulting table can be augmented like

this:

Current State Next State JK Flip Flops X=0 X=1 X=0 X=1

00 00 01 0X 0X 0X 1X01 00 11 0X X1 1X X010 10 11 X0 0X X0 1X11 00 01 X1 X1 X1 X0

We then use k maps to optimize & derive the input equations for in terms of and X since the circuit is a sequential circuit – its next state is dependent on itscurrent state and its input.

CurrentState

Next state

X=0 X=100 00 0101 00 11

10 10 1111 00 01

q Q J K0 0 0 X0 1 1 X1 0 X 11 1 X 0

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IMPLEMENTATION USING T FLIP FLOPS We shall design the same circuit using T flip flops. Again, keeping the T flip flop

excitation table in mind, we augment the state transition table.

By constructing k-maps for each T, we derive the T flip-flop input equations :

The logic diagram of the circuit using T flip flops is thus:

Current State Next State T Flip Flops

X=0 X=1 X=0 X=1

00 00 01 00 0101 00 11 01 1010 10 11 00 0111 00 01 11 10

q Q T0 0 00 1 11 0 11 1 0

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ARITHMETIC CIRCUITS Arithmetic circuits perform arithmetic operations and form the basis for a

microprocessor’s ALU. They typically operate on binary input vectors, and output a

resulting vector.

As it is not practical in developing a truth table for a many bit vector (n bits means 64

inputs, 32 outputs and a row truth table), we use arithmetic blocks or sub-functions

in each bit position. The sub-function blocks are referred to as cells and the overall

implementation is an (iterative) array of cells. The cells in the array are often, but notalways, identical. The above diagram shows an iterative array of cells.

B INARY ADDERS Binary adders add 2 bits together. Notice that the first three operations produce a sum

requiring a one bit representation, but when both the augend and addend are equal to

1, the binary sum requires 2 bits. Hence, the result is always represented by 2 bits – the

carry and the sum.

H ALF ADDER A half adder generates the sum of two binary digits using two inputs and two outputs.

By drawing up the truth table, we can derive the equations for the Sum and the Carry.

From the equations, we can then design the logic circuit:

X Y C S0 0 0 00 1 0 11 0 0 11 1 1 0

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F ULL ADDER A full adder is a combinational circuit that forms the arithmetic sum of three input bits.

X and Y are the two significant bits to be added, while Z represents the carry in. Using

the truth table, and k-maps we derive the sum and carry out equations:

The logic diagram for a full adder will thus be:

B INARY R IPPLE CARRY ADDER A binary ripple carry adder is a n-bit parallel adder formed by cascading n full adders.

Since a 1 carry may appear near the LSB, just as wave ripples outward from a pebble

dropped in a pond, the carry may ripple towards the MSB carry out since the carry

output from one full adder is the carry input of the next.

The problem with ripple carry adders is that in practice they have long circuit delays

since the carry has to propagate through many gates until the final result is obtained.

For example a 16 bit adder has at least 32 gate layers since each full adder is

approximately a 2 level combinational logic circuit. A better estimate is given by .

X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 1

0 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

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CARRY LOOK AHEAD ADDER Carry look ahead adders are combinational circuits that add n bits in parallel and can

calculate all the carry bits straight from the inputs, minimizing the gate delay. We first

define a carry generate – we must generate a carry when the two bits are 1 so:

Next we define a carry propagate : determines whether in that bit position is going topropagate a carry from the right. A carry propagates if only one of the bits is a 1 so:

We can thus express the sum (S) and carry (C) in terms of the generate and propagate

function:

Hence the carry equations for a 4 bit carry look ahead adder will be as shown on theleft. In theory there will be 3 gate delays regardless of the number of bits, at a cost of

more complex logic – 1 to calculate the propagate, 1 for the AND gates and 1 for the OR

gate. The carry look ahead logic is connected to a partial full adder which is the

implementation of and the carry generate.

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UNSIGNED BINARY SUBTRACTION The subtraction of two n digit numbers M-N in base 2 is done by:

Subtracting the subtrahend N from the minuend M If no end borrowing occurs, then and the result is a non negative and

correct If an end borrow occurs, then and the difference is thus:

and we append a minus sign to the result.

Consider in decimal: . We shall reverse the operation and add

append a minus in front to give us -11 which is the solution to 89-100. We just applied

this concept to binary subtraction – a process called taking the 2s complement wherebywe subtract the binary number from .

If we apply such a design to a circuit, our circuit becomes unnecessarily complex since

we need a separate sub function just for subtraction. A better way would be to find a

shared logic for both addition and subtraction by using the complements approach .

COMPLEMENTS There are two types of complmenets:

Diminished radix (( ) complement: is defined as , for some

number N. Radix (r’s) complement: is defined as for some number N

For binary numbers, r=2 and n equals the number of bits in the string. Hence we get the

names binary 1s complements and 2s complement.

1 S COMPLEMENT The 1s complement are easily obtained by inverting all the bits in N. Formally it is

defined as ( . So for N=0111 0011, n=8 and r=2 then:

Then 2 S COMPLEMENT

The 2s complement can be found by taking the 1s complement and adding 1. This idea isthe foundation for subtraction using addition in digital logics. Formally the 2s

complement is .

Consider r=2, N=0111 0011 n=8. Then:

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SUBTRACTING USING 2 S COMPLEMENT The subtraction of two n digit unsigned numbers, M-N, in binary can be done by:

1. Adding the 2s complement of the subtrahend N to the minuend M. Hence we

get:

2. If the sum produces an end carry, . Discard the end carry and takethe result

3. If , the sum does not produce an end carry and is equal to

, , the 2s complement of N-M. We correct the result by taking the 2s

complement of the sum to obtain – .Consider , perform and using 2s complementoperations.

SIGNED BINARY NUMBERS We will now extend this approach to signed numbers, including a further use ofcomplements that eliminates the correction step. Previously, negative numbers were

identified with a minus sign on paper, but there was no digital implementation. For

signed binary numbers we define the most significant bit to be the sign bit:

0 for positive numbers 1 for a negative number

Using signed binary numbers, we can thus represent integers in signed magnitude or

signed complement form.

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S IGNED MAGNITUDE In signed magnitude form, the MSB stands for the sign, while the rest of the bits are

interpreted as a positive magnitude. For example:

The problem that arises with signed magnitude arithmetic is that it becomes very

complex – it is necessary to check the sign of the bits to determine the operation and

the carry out or borrow determines whether a correction step should be applied to the

result.

S IGNED COMPLEMENT In signed complement form, the MSB corresponds to the sign and the positive numbers

are a usual, but for negative numbers, we take the 2s complement of the respective

positive number.

We could choose to use the 1s complement, but the 2s complement allows us to use the

same hardware as for unsigned numbers alone. Suppose we want to represent 7 and -7

using 8 bits (sign extension) instead of 4, then in 2s complement form:

Notice that we extend the MSB at the front of the number when we need to perform

sign extension on signed numbers. For unsigned numbers, we pad the front with 0s.

I N T E R P R E T I N G N E G AT I V E N UMBERS

To convert a signed complement negative binary number to decimal we can either:

Take the 2s complement of the negative number and append a minus sign Convert as usual but subtract the MSB’s value instead of adding

Consider the 8 bit number: 1110 1101. If we take the 2s complement we get:

Then append a minus sign so: 1110 1101=-19Alternatively we convert as usual and subtract the MSB value:

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2 S COMPLEMENT ADDER / SUBTRACTOR We can thus build a 2s complement adder/subtractor to simplify the whole process of

addition and subtraction. The XOR gates are used to take the 2s complement when

needed.

When the selection signal S is 0, the vector B propagates as normal and the carry in is 0;computing A+B. When S=1, the vector B is complemented and the carry in is 1, and

hence we obtain the 2s complement of B; calculating A-B.

OVERFLOW Overflow occurs if n+1 bits are required to contain the result from an n bit addition or

subtraction. Consider for example an 8 bit number. Any 8 bit string can represent any

number between – to ; hence for 8 bits it is -128 to 128. Consider whenwe perform 70+80 and -70-80.

Note that the 8 bit result that should have been positive has a negative sign bit and that

the 8 bit result that should have been negative has a positive sign bit. We say that an

overflow has occurred, since the carry out could be used as the 9 th bit to represent the

answers correctly.

Overflow occurs when the carry in to the MSB is not equal to the carry out from the

MSB. A simple XOR gate that takes the carry in and carry out from the MSB can

determine whether an overflow has occurred:

For unsigned addition, C will detect for overflows. If C=0, no overflow occurs while, C=1

indicates an overflow. For signed addition & subtraction, V=0 indicates no overflow

while V=1 indicates an overflow.

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N,Z,C,V STATUS FLAGS The following status signals provide information from the arithmetic unit in

microprocessors.

N (Negative): 1 if the sum is negative, 0 if positive

Z (Zero): 1 if the sum is zero, 0 if non zero C (Carry): 1 if there is a carry out or overflow for unsigned addition V( oVerflow): 1 if signed overflow is detected.

These flags are implemented as:

Consider the following example:

This means that an overflow occurred (V=1) and the sum is not actually correct since the

flag N is 1, when in fact, the sum should be positive.

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CMOS TECHNOLOGY Digital integrated circuits can be classified according to their implementation

technology. Currently, complementary metal oxide semiconductors (CMOS) technology

dominates due to its high circuit density, high performance and low power

consumption.

There are two main types of CMOS transistors, the NMOS and PMOS.

NMOS LOGIC The NMOS usually has its Source connected to GND and the

Gate to some input X. Note that in order for the NMOS to be

active, then voltage difference between the gate and source

must be greater than some threshold voltage. If the Source

were connected to then this condition could never be

achieved.

PMOS LOGIC A PMOS transistor has its source usually connected to and

the gate to some input X. Note that the voltage across the gate

needs to be less than the threshold voltage for it to be active.

Since we do not deal with negative voltages, then connecting

the source to ground will violate this condition.

INVERTER Combining the two transistors together, we get an inverter.

For any logical value X, there is only one path to either or

GND. If X is high (suppose 5V), then the NMOS is active and

pulls F to GND. But if X is low (suppose 0V), then the PMOS is

active and F is connected to .

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P ULL UP , P ULL DOWN NETWORKS A CMOS gate is usually a combination of a pull up network (PUN) and a Pull Down

Network (PDN).

The PUN is constructed using PMOS transistors with the source connected to . This

connects the output to when a logic 1 is required. Similarly, a PDN is constructedusing NMOS transistors, and connects the output to GND when a logic 0 is required.

The two networks are mutually exclusive such that only one network conducts in steady

state.

CMOS GATE DESIGN To design a CMOS gate, we implement the PDN first using NMOS transistors. The AND

function is achieved by connecting the NMOS devices in series, while the OR function is

created by connecting the NMOS devices in parallel.

The PUN is obtained by taking the dual of the PDN, using PMOS transistors. We replace

the series subnets in the PDN with parallel ones in the PUN and replace the parallel

subnets in the PDN with series one in the PUN.

In CMOS technology, the gates are naturally inverting. Hence, we can implement

functions such as NOT, NAND and NOR in a single stage. To realize non-inverting

Boolean functions such as AND or OR, an additional inverter stage is required at the

end.

NAND GAT E The NAND gate function is defined as: . The PDN

will be constructed using 2 NMOS transistors in series with

X and Y being the gate inputs. The PUN will be the dual of

this, so the PMOS gates are connected in parallel.

To construct a 3 input NAND gate, we use 3 NMOS

transistors in series, and 3 PMOS transistors in parallel.

NOR GATE The NOR gate: is designed by connecting theNMOS gates in parallel and the PMOS gates in series with the

gate inputs being X and Y.

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MORE COMPLEX GATES Consider

Implementing the NMOS first, we connect B and C in parallel and series it with A. This

whole connection is then in parallel to D. The PMOS is the dual of this – B and C will be

in series but A will be parallel to A and B, and D will be in series with the lot.

Consider

We need to parallel Y and Z and series

this with X using NMOS transistors, and

put the two lots in parallel. We take the

dual for the PUN. Since the CMOS

technology is naturally inverting, we

need to invert the output to get F.

TRANSITION GATES A transmission gate is constructed using one NMOS and one PMOS transistor that have

its source and drain connected together.

A transmission gate acts as an electronic switch, blocking or passing signals between

two points in a circuit.

When , one of the transistors will be on (depending on the valueof X) and a path exists between X and Y.

o If the gate voltage is higher than the source, then the NMOS switches

on, if the gate voltage is lower than the source, the PMOS switches on. When both transistors will be off regardless of X, and no path

exists between X and Y.

The schematic shows an implementation of a XOR gate using transmission gates. Note

how when A=B=L, then the upper transmission gate is active, allowing A propagate. But

Edmund Li