elec 2005 elec-2005 electronics in high energy physics spring term: integrated circuits and vlsi...

ELEC 2005

ELEC-2005Electronics in High Energy Physics

Spring term: Integrated circuits and VLSI technology for physics

Basic Analog Design

Giovanni Anelli

15 March 2005

Part II

CERN Technical Training 2005

Giovanni Anelli - CERN 2ELEC 2005

Outline – Part II

• Noise in analog ICs• Matching in analog ICs• Operational Amplifier design examples• Analog design methodology


Thermal noise in passive components

R

2nv

] V [ fkTR4v 22n

2ni

R] A [ f

R

kT4i 22n

There are no sources of noise in ideal capacitors or inductors. In practice, real components have parasitic

resistance that does display thermal noise!

Thermal noise is caused by the random thermally excited vibration of the charge carriers in a conductor.

Power spectral density [ V 2 / Hz ]


Noise sources in MOS transistors

Channel thermal noise: due to the random thermal motion of the carriers in the channel

1/f noise: due to the random trapping and detrapping of mobile carriers in the traps located at the Si-SiO2 interface and within the gate oxide.

Bulk resistance thermal noise: due to the distributed substrate resistance.

Gate resistance thermal noise: due to the resistance of the polysilicon gate and of the interconnections.


Noise in circuits

To be independent from the gain of a given system, we use the concept of input-referred noise. This allows comparing easily the noise

performance of different circuits (with different gains), and calculating easily the Signal-to-Noise Ratio (SNR).

At the input of our linear two-port circuit, we use two noise generator (one noise voltage source and one noise current source) to represent the noise of the system regardless the impedance at the input of the

circuit and of the source driving the circuit.

Noisycircuit

2out,nv Noiseless

circuit2

out,nv2

in,ni

2in,nv


Input-referred voltage noise

ideally varies from 1/2 (w.i.) to 2/3 (s.i.)

Ka = 1/f noise parameter, technology dependent

Usually, the first two terms are the most important

Bulk resistance thermal noise

Channel thermal noise

1/f noiseGate resistance thermal noise

B2m

2mb

G2ox

a

m

2in R

g

gkT4kTR4

f

1

WLC

K

g

1kTn4

f

v

The MOS transistor is represented by its small-signal equivalent circuit. We can refer the noise sources inside the MOS transistor to the input,

obtaining an input-referred voltage noise.


N-channel noise spectra

W = 2 mm, IDS = 0.5 mA, VDS = 0.8 V, VBS = 0 V

1.E-09

1.E-08

1.E-07

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08

Frequency [ Hz ]

No

ise

[ V

/sq

rt(H

z) ]

L = 0.36um

L = 0.5um

L = 0.64um

L = 0.78um

L = 1.2um


Noise in a DP + Active CM

2load2

in_m

2load_m2

in2tot v

g

g2v2v

VDD

2inv 2

inv

2loadv 2

loadv

2outi

2I

VDD

2totv

2outi

2I


Noise in a DP + Active CM

fLK

LK1

f

1

LWC

K2v

2loadinin_a

2inloadload_a

inin2ox

in_a2f/1_tot

VDD

2totv

2I

inloadinin LLLW and big Make

f

LWLW

1

ILW

C2

2kTn4v

inin

loadload

in

inoxin

2th_tot

loadin

Make

L

W

L

W


Outline – Part II



The importance of matching

Yield of an N-bit flash Analog-to-Digital converter as a function of the comparator mismatch


Relative & absolute mismatch

L1

L2

D2

D1

[%]1L2L

1L2L200

L

L

m][ 2D1DD

Mismatch occurs for all IC components (resistors, capacitors, bipolar and MOS transistors)

Absolute mismatchRelative mismatch


Mismatch in MOS transistors

Mismatch in physical parameters (Na, , Tox) and layout dimensions (W, L) gives origin to mismatch in electrical parameters (VT, and therefore ID)

2TGSDS )VV(

n2I

VGS1

IDS1

VGS2

IDS2

Mismatch in Na, , Tox

Mismatch in W and L

+

and TV

D

DGS I

IV

and

Parameter mismatch

I mismatch and V offset


The golden rule: Bigger is better!

Random effects “average out” better if the area is bigger. Therefore, for a given parameter P, we expect something like

L W

APΔP

ΔP

m][1/ WL1/ PA


Expected mismatch

L W

A th

th

VV

L W

A /

AVth / tox ~ 1 mV·m / nm

A ~ 1 to 3 %·m

From the literature

Mismatch can be treated as another source of noise. As in the noise case, different “mismatch” sources can be grouped into one adding

the variances (not the standard deviations)

Usually in a pair of identical transistors the two most important parameter subject to mismatch are the threshold voltage Vth and the

current factor


Differential pair mismatch

The two transistors have the same drain current

2

/m

2VΔV g

Iσ

thGS

2I

I.C.

0

2

4

6

8

10

12

14

16

18

20

22

1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03

]mV[σGSV

%4.1σ /Δ

mV5.4σTV

TVσ

INVERSION COEFFICIENT


Current mirror mismatch

2

Vm2

/ΔI/I thI

gσ

The two transistors have the same gate voltage

I

I.C.

0

2

4

6

8

10

12

14

1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03

[%]σΔI/I %4.1σ /Δ

mV5.4σTV

/σ

INVERSION COEFFICIENT


Offset of a DP + Active CM

VDD

offv

2I

T1 T2

T3 T4

RANDOM OFFSET (WORST CASE)

Vout

Vin

SYSTEMATIC OFFSET

The difference in the drain voltages of T1 and T2 gives origin a difference in the DC currents in the two branches.

“COMMON MODE” OFFSET

Due to mismatches in the transistors, a common mode signal at the input gives a non zero output voltage signal.

4,3T4,3m

4,3

4,3

2,1

2,1

2,1m2,1Toff V

I

g

g

IVv


Outline – Part II

• Noise in analog ICs• Matching in analog ICs• Operational Amplifier design examples

Op Amp application examples Single-Stage Op Amps Two-Stage Op Amps Fully Differential Op Amps Feedback and frequency compensation

• Analog design methodology


The ideal op amp

)vv(A inin0

An op amp is basically a voltage-controlled voltage source

Rin

Vin +

Vin -

Rout

Vout

The op amp is ideal when

A0 = Rin = ∞, Rout = 0


Op amp application examples

Vout = Vin

Vin

R1

Vout

Vin

R2

VoutR1

Vin

R2

NONINVERTING CONFIGURATION

INVERTING CONFIGURATION

BUFFER

The above equations are valid only if the gain A0 of the op amp is very high!

1

2

R

R1G

1

2

R

RG

1G


Single-stage Op AmpVDD

ISS

T1 T2

T7 T8

Vb1 Vb1T3 T4

Vin

Vout

The differential pair + active current mirror scheme we have already seen is a single stage op amp. Several different

solutions can be adopted to make a Single-stage amplifier. If high gains are

needed, we can use, for example, cascode structures.

With single-stage amplifiers it is difficult to obtain at the same time high gain and

voltage excursion, especially when other characteristics are also required,

such as speed and/or precision.

Two-stage configurations in this sense are better, since they decouple the gain

and voltage swing requirements.

T5 T6


Two-stage Op Amp

Vout

VDD

T6 T7

T1 T2

T8

Rb

Vin - Vin +

T3 T4

T5

)r//r(g)r//r(gG 08055m04022m

The second stage is very often a CSS,

since this allows the maximum voltage

swing.The output voltage

swing in this case is VDD - |2VDS_SAT|


Two-stage Op Amp

Vin

VDD

ISS

T1 T2

T3 T4

Vb T6T5

T7 T8

Vout

In this case we kept the differential behavior of

the first stage, and is the current mirror T7-T8

which does the differential-to-single

ended conversion. The output is still a CSS.

)r//r(g)r//r(gG 08066m4,032,012,1m


Fully Differential Op Amp

Vin

VDD

ISS

T1 T2

T3 T4

Vb1 T6T5

T7 T8Vb2

Vout1 Vout2

)r//r(g)r//r(gG 8,076,056,5m4,032,012,1m


Fully Differential Op Amp

T10T9

T11 T12Vb4

Vout1 Vout2

VDD

ISS

T1 T2

T7 T8Vb3 Vb3

T5 T6Vb2 Vb2

Vb1 Vb1T3 T4

Vin

Vb4

To increase the gain, we can again make use, in the

first stage, of cascode structures.

12,01110,0910,9m8,076,056,5mb6,5m2,014,034,3mb4,3m2,1m r//rg )rr)gg(// )rr)gg(g G


Feedback

+ A(s)

F(s)

VoutVin

)s(G1

)s(A

)s(F)s(A1

)s(A

)s(v

)s(v)s(G

loopin

out

• A(s) is the open loop transfer function

• F(s) is the feedback network transfer function

• G(s) is the closed loop transfer function

• A(s)F(s) is the loop gain

• If the feedback is negative, the loop gain is negative

• For |Gloop(s)| >> 1, we have that )s(F

1)s(G


Properties of negative feedback

Negative feedback reduces substantially the gain of a circuit, but it improves several other characteristics:

• Gain desensitization: the open loop transfer function is generally dependent on many varying quantities, given by the active components in the circuit. Using a passive feedback network, we can reduce the dependence of the gain variation on the variations of the open loop transfer function.

• Reduction of nonlinear distortion

• Reduction or increase (depending on the feedback topology) of the input and output impedances by a factor 1-Gloop.

• Increase of the bandwidth

loopG1

1

A

dA

G

dG


Bode diagrams

-60

-40

-20

0

20

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency [rad/s]

20lo

g1

0|H

(s)|

[d

B]

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

Frequency [rad/s]

Ph

ase

[deg

rees

]

Many interesting properties of the frequency behavior of a given circuit can be obtained plotting the module and the phase of the Transfer Function as a

function of the frequency. These plots are called Bode diagrams. In the general case, a transfer function is given by the ratio between two polynomials. The

roots of the numerator polynomial are called zeros, the roots of the denominator polynomials are called poles. For example, in the case of a

low-pass filter with RC = 1 ms, the Bode diagrams look like:


Bandwidth increase with feedback

+ A(s)

- f

VoutVin

|G(s)|

0

0

s1

A)s(A

A0

(1+fA0)

00

0

0

)fA1(s

1

fA1A

)s(Af1

)s(A)s(G

f

1

fA1

A

0

0

GBWP

The gain-bandwidth product does not change with feedback!


Stability Criteria

+ A(s)

- f

VoutVin

|fA(s)|

)s(Af1

)s(A)s(G

fA(s)

- 90- 180

1 1

GREEN: STABLERED: UNSTABLE

Barkhausen’s Criteria

0)s(Af1

|fA(j1)| = 1

fA(j1) = - 180


Phase Margin

We have seen that to ensure stability |fA(s)| must be smaller than 1 before fA(s) reaches - 180. But, in fact, to avoid oscillation and ringing, we

must have a bit more margin.We define phase margin (PM) the quantity 180 + fA(), where is the gain crossover frequency. It can be shown that, to have a stable system with no ringing (for small signals) we must have PM > 60. If we want to have an amplifier which responds to a large input step without ringing,

PM must be even higher.

|fA(s)|

fA(s)

- 180

1

|fA(s)|

fA(s)

- 180

1

SMALL PM LARGE PM


Frequency Compensation

Single-pole op-amps would always be stable (the phase does not go

below - 90). But a typical op-amp circuit always contains several poles (and zeros!). These op-

amps can easily be unstable, and they need

therefore to be compensated. This is

generally done lowering the frequency of the

dominant pole.

|fA(s)|

fA(s)

- 90- 180

1 1

RED: BEFORE COMPENSATIONGREEN: AFTER COMPENSATION


Outline – Part II



Analog design methodology

Define specifications

Choose architecture

Simulate schematic

Simulate schematic varying T, VDD, process parameters

Masks layout

Design Rules Check (DRC)

Extract schematic from layout

Layout Versus Schematic (LVS) check

Extracted schematic simulations

BLOCK DONE!

In a complex design, this will be repeated

for every block of the design hierarchy.


Analog design trade-offs

NOISE LINEARITY

GAIN

SUPPLY VOLTAGE

VOLTAGE SWINGS

SPEED

INPUT/OUTPUT IMPEDANCE

POWER DISSIPATION

ANALOG DESIGN

OCTAGON


Bibliography

Books:

B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001.R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999.R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990.D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999.K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System Design, John Wiley and Sons, 1993.A. L. McWhorter, Semiconductor Surface Physics, University Pennsylvania Press, 1956, pp. 207-227.Z.Y. Chang and W.M.C. Sansen, Low-noise wide-band amplifiers in bipolar and CMOS technologies, Kluwer Academic Publishers, 1991.

Papers:

K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design", IEEE Journal of Solid-State Circuits (JSSC), vol. 21, no. 6, December 1986, pp. 1057-1066. Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", JSSC, vol. 34, no. 3, March 1999, p. 268.M.J.M. Pelgrom et al., “Matching Properties of MOS Transistors”, IEEE JSSC, vol. 24, no. 10, 1989, p. 1433.M.J.M. Pelgrom et al., “A 25-Ms/s 8-bit CMOS A/D Converter for Embedded Application”, IEEE JSSC, vol. 29, no. 8, Aug. 1994 , pp. 879-886.R. W. Gregor, "On the Relationship Between Topography and Transistor Matching in an Analog CMOS Technology", IEEE Transactions on Electron Devices, vol. 39, no. 2, February 1992, pp. 275-282.

ELEC 2005

ELEC-2005Electronics in High Energy Physics

Spring term: Integrated circuits and VLSI technology for physics

Basic Analog Design

Giovanni Anelli

15 March 2005

Part II

CERN Technical Training 2005

elec 2005 elec-2005 electronics in high energy physics spring term: integrated circuits and vlsi...

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