elct 201: digital logic designeee.guc.edu.eg/courses/electronics/elct201 digital logic...elct 201:...
TRANSCRIPT
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ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, [email protected]
Dr. Eng. Wassim Alexan, [email protected]
Lecture 4
Following the slides of Dr. Ahmed H. Madian
هــ 1441محرم
Winter 2019
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COURSE OUTLINE
1. Introduction
2. Gate-Level Minimization
3. Combinational Logic
4. Synchronous Sequential Logic
5. Registers and Counters
6. Memories and Programmable Logic
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LECTURE OUTLINE
• Combinational Logic Circuits • Steps of Combinational Logic Design
• The XOR Function
• Half Adder
• Full Adder
• Binary Adder/Subtractor
• Binary Multiplier
• Magnitude Comparator
• Parity Generator/Checker
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COMBINATIONAL LOGIC
• Combinational logic circuits can have any number of inputs and outputs
• The logic states of the inputs at any given instant determine the state of the output
4
• Sequential circuits, which we will discuss later in this course, will feature circuits in which the outputs are not determined solely by the inputs at the same time
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HOW TO DESIGN A COMBINATIONAL LOGIC CIRCUIT?
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each
2. Derive the truth table that defines the required relationship between the inputs and outputs
3. Obtain the simplified Boolean functions for each output as a function of the input variables (using a K-map)
4. Sketch the logic diagram
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DESIGN PROBLEM
Design a digital system whose output is defined as logically
low if the 4-bit input binary number is a multiple of 3;
Otherwise, the output will be logically high. The output is
defined if and only if the input binary number is greater
than 2
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INPUT/OUTPUT RELATIONSHIP AND TRUTH TABLE
• Design a digital system
whose output is defined as
logically low if the 4-bit
input binary number is a
multiple of 3; otherwise, the
output will be logically high
• The output is defined if and
only if the input binary
number is greater than 2
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BOOLEAN FUNCTION SIMPLIFICATION USING A K-MAP
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BOOLEAN FUNCTION SIMPLIFICATION USING A K-MAP
SOP POS
𝑌𝑆𝑂𝑃 = 𝐵′𝐷′ + 𝐴′𝐶′ + 𝐴′𝐵𝐷 + 𝐵𝐶′𝐷 + 𝐴𝐵′𝐶 + 𝐴𝐶𝐷′
𝑌𝑃𝑂𝑆 = (𝐴 + 𝐵)(𝐵 + 𝐶 + 𝐷′)(𝐴 + 𝐶′ + 𝐷)(𝐴′ + 𝐵′ + 𝐶 + 𝐷)(𝐴′ + 𝐵′ + 𝐶′ + 𝐷′)
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SKETCHING THE LOGIC DIAGRAM
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THE XOR FUNCTION
The XOR symbol is denoted as ⊕
Its Boolean operation is 𝑥 ⊕ 𝑦 = 𝑥𝑦′ + 𝑥′𝑦
The XNOR symbol is denoted as ⊙
Its Boolean operation is 𝑥 ʘ 𝑦 = 𝑥𝑦 + 𝑥′𝑦′
The identities of the XOR operation are
given by:
𝑥 ⊕ 0 = 𝑥 𝑥 ⊕ 1 = 𝑥′
𝑥 ⊕ 𝑥 = 0 𝑥 ⊕ 𝑥′ = 1
Commutative and associative:
A ⊕ 𝐵 = 𝐵 ⊕ 𝐴
(A ⊕ 𝐵) ⊕ 𝐶 = 𝐴 ⊕ (𝐵 ⊕ 𝐶) = 𝐴 ⊕ 𝐵 ⊕ 𝐶
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Z Y X
0
1
1
0
0
1
0
1
0
0
1
1
Z Y X
1
0
0
1
0
1
0
1
0
0
1
1
XOR
XNOR
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦
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THE XOR IMPLEMENTATION
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• The output analysis for the first
circuit is very easy!
• The output at each of the NAND
gates for the second circuit is as
follows:
• At L1: 𝑥𝑦 = 𝑥′ + 𝑦′
• At L2:
𝑥(𝑥′ + 𝑦′) = 𝑥𝑥′ + 𝑥𝑦′ = 𝑥𝑦′ = 𝑥′ + 𝑦
• At L3:
𝑦(𝑥′ + 𝑦′) = 𝑥′𝑦 + 𝑦𝑦′ = 𝑥′𝑦 = 𝑥 + 𝑦′
• At L4:
L1
L2
L3
L4
(𝑥′+𝑦)(𝑥 + 𝑦′) = (𝑥′ + 𝑦) + (𝑥 + 𝑦′) = 𝑥𝑦′ + 𝑥′𝑦 = 𝑥 ⊕ 𝑦
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ARITHMETIC CIRCUITS
• We will continue with the design of digital logic circuits
• One of the famous digital logic circuits is the calculator
• How to design it?
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ARITHMETIC CIRCUITS
• An arithmetic circuit is a combinational circuit that performs arithmetic operations such as: • Addition
• Subtraction
• Multiplication
• Division
• A combinational circuit that performs the addition of two bits is called a Half Adder
outputs one digit
outputs two digits!
carry sum
So, we need two binary outputs to
represent the addition block
(carry & sum)
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10
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HALF ADDER
It is required to design a combinational circuit that adds two binary numbers and produces the output in the form of two bits, sum and carry
Solution:
1. We need to determine the inputs and output of the system and give letters for all of them: Our system has two inputs (x, y) and two outputs (S, C)
Half Adder
x
y C
S
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HALF ADDER
2. Derive the truth table according to the given relation between inputs and outputs
Outputs Inputs
S C y x
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
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HALF ADDER
3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map
𝐶 = 𝑥𝑦 𝑆 = 𝑥𝑦′ + 𝑥′𝑦
= 𝑥 ⊕ 𝑦
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HALF ADDER
4. Sketch the logic diagram
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FULL ADDER
It is required to design a combinational circuit that adds three binary numbers and produces the output in the form of two bits, sum and carry
Solution:
1. We need to determine the inputs and outputs of the system and give letters for all of them: Our system has three inputs (x, y, z) and two outputs (S, C)
Full Adder y
S
C z
x
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FULL ADDER
2. Derive the truth table according to the given relation between the inputs and outputs
Decimal
Equivalent
Outputs Inputs
S C z y x
0
1
1
2
1
2
2
3
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
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FULL ADDER
3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map
𝑆 = 𝑥′𝑦′𝑧 + 𝑥′𝑦𝑧′ + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧
= 𝑧 𝑥′𝑦′ + 𝑥𝑦 + 𝑧′ 𝑥′𝑦 + 𝑥𝑦′
= 𝑧(𝑥′𝑦 + 𝑥𝑦′) + 𝑧′(𝑥′𝑦 + 𝑥𝑦′)
= 𝑧 𝑥 ⊕ 𝑦 + 𝑧′ 𝑥 ⊕ 𝑦
= 𝑧 ⊕ 𝑥 ⊕ 𝑦
= 𝑥 ⊕ 𝑦 ⊕ 𝑧
Remember that:
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦, 𝑥 ⊕ 𝑦 = 𝑥𝑦′ + 𝑥′𝑦, 𝑥⊙𝑦 = 𝑥𝑦 + 𝑥′𝑦′
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FULL ADDER
3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map
𝐶 = 𝑥𝑦 + 𝑥𝑧 + 𝑦𝑧
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FULL ADDER
4. Sketch the logic diagram
𝑆 = 𝑥′𝑦′𝑧 + 𝑥′𝑦𝑧′ + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 𝐶 = 𝑥𝑦 + 𝑥𝑧 + 𝑦𝑧
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FULL ADDER
• The logic circuit for the full adder could also be sketched using two half adders and a single OR gate
𝐶 = 𝑥 ⊕ 𝑦 𝑧 + 𝑥𝑦
= 𝑥𝑦′ + 𝑥′𝑦 𝑧 + 𝑥𝑦
= 𝑥𝑦′𝑧 + 𝑥′𝑦𝑧 + 𝑥𝑦
𝑆 = 𝑥 ⊕ 𝑦 ⊕ 𝑧
Half adder Half adder
Compare the obtained Boolean expression
for 𝐶 here and the one obtained in slide 22
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4-BIT BINARY RIPPLE CARRY ADDER
• Connecting n full adders in cascade allows us to add n-bit binary numbers together
• Example:
Connecting 4 full adders in cascade allows us to add 1011 to 0011.
𝐴 = 𝐴3𝐴2𝐴1𝐴0 = 1 0 1 1 𝐵 = 𝐵3𝐵2𝐵1𝐵0
= 0 0 1 1
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4-BIT BINARY RIPPLE CARRY ADDER 𝑨𝟎 = 𝟏
𝑪𝟎 = 𝟎
𝑺𝟎 = 𝟎 𝑪𝟒 = 𝟎
𝟏 𝟏 𝟎
𝑨𝟏 = 𝟏 𝑨𝟐 = 𝟎 𝑨𝟑 = 𝟏 𝑩𝟎 = 𝟏 𝑩𝟏 = 𝟏 𝑩𝟐 = 𝟎 𝑩𝟑 = 𝟎
𝑺𝟏 = 𝟏 𝑺𝟐 = 𝟏 𝑺𝟑 = 𝟏
This adder is extremely
slow, as each stage must
wait for the previous one to
get the carry from it!
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BINARY SUBTRACTOR
• The subtraction of binary numbers can be easily done using complements
• The subtraction 𝐴 − 𝐵 is done by taking the 2’s complement of 𝐵 and adding it to 𝐴
• The 2’s complement can be obtained by taking the 1’s complement and adding 1 to the least significant bit (LSB)
• The 1’s complement can be implemented easily with an inverter gate
• We can add 1 to the sum by making the initial input carry of
the parallel adder equal to 1
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BINARY ADDER/SUBTRACTOR
• Subtractor
• Adder/Subtractor
FA
FA
𝑆
𝐶𝑜𝑢𝑡
𝐴
𝐶𝑖𝑛 = 1
𝐵
𝐵 𝐴
𝑆
𝐶𝑜𝑢𝑡
This is equivalent
to 𝐴 plus the 2’s
complement of 𝐵
Remember that 𝐵 ⊕ 0 = 𝐵
and 𝐵 ⊕ 1 = 𝐵′
If 𝐶𝑖𝑛 = 0, circuit acts as an Adder
If 𝐶𝑖𝑛 = 1, circuit acts as a Subtractor
𝐶𝑖𝑛
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BINARY MULTIPLIER
2 bits × 2 bits = max 4 bits
(11)2× (11)2= (1001)2
(3)10× (3)10= (9)10
𝑀3 𝑀2 𝑀1 𝑀0 𝑀3 𝑀2 𝑀1 𝑀0
𝑆 𝐶 𝐶 𝑆
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MAGNITUDE COMPARATOR
It is required to design a circuit to compare between two inputs 𝐴 = {𝐴1, 𝐴2} and 𝐵 = {𝐵1, 𝐵2}. Both inputs consist of two binary bits and the circuit has three outputs: Greater than, Less than or Equal
Solution:
1. We need to determine the inputs and outputs of the system and give letters for all of them: Our system has four inputs (𝐴0, 𝐴1, 𝐵0, 𝐵1) and three outputs (𝐺, 𝐿, 𝐸)
Magnitude
Comparator
𝐴0
𝐴1
𝐵1
𝐵0
𝐺
𝐿
𝐸
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MAGNITUDE COMPARATOR
2. Derive the truth table that defines the required relationship between the inputs and outputs
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MAGNITUDE COMPARATOR
3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map
𝐺 𝐴1, 𝐴0, 𝐵1, 𝐵0 = 𝐴1𝐴0𝐵0′ + 𝐴0𝐵1
′ 𝐵0′ + 𝐴1𝐵1
′
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MAGNITUDE COMPARATOR
3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map
𝐸 𝐴1, 𝐴0, 𝐵1, 𝐵0 = 𝐴1′ 𝐴0
′ 𝐵1′ 𝐵0
′ + 𝐴1′ 𝐴0𝐵1
′ 𝐵0 +𝐴1𝐴0𝐵1𝐵0 + 𝐴1𝐴0
′ 𝐵1𝐵0′
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MAGNITUDE COMPARATOR
3. Obtain the simplified Boolean functions for each output as a function of the input variables using a K-map
𝐿 𝐴1, 𝐴0, 𝐵1, 𝐵0 = 𝐴1′ 𝐴0
′ 𝐵0 + 𝐴0′ 𝐵1𝐵0 + 𝐴1
′ 𝐵1
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MAGNITUDE COMPARATOR
4. Sketch the logic diagram for the output 𝐺
𝐺 𝐴1, 𝐴0, 𝐵1, 𝐵0 = 𝐴1𝐴0𝐵0′ + 𝐴0𝐵1
′ 𝐵0′ + 𝐴1𝐵1
′
𝐴1
𝐴0
𝐵0′
𝐴0
𝐵1′
𝐵0′
𝐴1
𝐵1′
𝐺
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4. Sketch the logic diagram for the output 𝐸
𝐴1′
𝐴0′
𝐵1′
𝐵0′
𝐸 𝐴1, 𝐴0, 𝐵1, 𝐵0 = 𝐴1′ 𝐴0
′ 𝐵1′ 𝐵0
′ + 𝐴1′ 𝐴0𝐵1
′ 𝐵0 +𝐴1𝐴0𝐵1𝐵0 + 𝐴1𝐴0
′ 𝐵1𝐵0′
𝐸
𝐴1′
𝐴0
𝐵1′
𝐵0 𝐴1
𝐴0
𝐵1
𝐵0 𝐴1
𝐴0′
𝐵1
𝐵0′
MAGNITUDE COMPARATOR
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MAGNITUDE COMPARATOR
4. Sketch the logic diagram for the output 𝐿
𝐿 𝐴1, 𝐴0, 𝐵1, 𝐵0 = 𝐴1′ 𝐴0
′ 𝐵0 + 𝐴0′ 𝐵1𝐵0 + 𝐴1
′ 𝐵1
𝐴1′
𝐴0′
𝐵0
𝐴0′
𝐵1
𝐵0
𝐴1′
𝐵1
𝐿
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PARITY BITS
• XOR functions are very useful in systems requiring error detection and correction (e.g. communication systems)
• A parity bit is used to detect errors that occur during the transmission of binary information
• A parity bit is an extra bit included with a binary message to make the number of 1s either even or odd
• The message, including the parity bit, is transmitted and then checked for errors at the receiver
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PARITY BITS
• An error is detected if the checked parity does not correspond with the one transmitted
• The circuit that generates the parity bit in the transmitter is called a parity generator
• The circuit that checks the parity bit in the receiver is called a parity checker
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PARITY BITS: AN EXAMPLE OF EVEN PARITY
• Consider a three-bit message to be transmitted together with an even-parity bit
• For even parity, the bit P must be generated to make the total number of 1s even
• P is an odd function, thus we can express it using the XOR operator as
𝑃 = 𝑥 ⊕ 𝑦 ⊕ 𝑧
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• The three-bits in the message, as well as the parity bit, are transmitted to the destination
• At the destination, a parity checker circuit is used to check for possible errors
• Since the information was transmitted with even parity, the four bits received must have an even number of 1s
• An error occurs during the transmission if the four bits received have an odd number of 1s (this means that a bit has changed in value)
• The output of the parity checker circuit will be equal to 1 if an error occurs
PARITY BITS: AN EXAMPLE OF EVEN PARITY
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• The output of this circuit is equal to 1 whenever there is an odd number of 1s in the inputs
PARITY BITS: AN EXAMPLE OF EVEN PARITY
Does having a value of 𝐶 = 0 insures
that there are no errors?
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• A parity generator/checker circuit can be implemented in a single circuit
• This is done if the input P is connected to logic 0 and the output is marked with P
• This is possible because
𝑧 ⊕ 0 = 𝑧
PARITY GENERATOR AND CHECKER CIRCUITS