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Eindhoven University of Technology

MASTER

Design of an enhanced 8051 microcontroller core architecture in IDaSS, synthesised withASA

Heuts, P.W.H.

Award date:1994

Link to publication

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https://research.tue.nl/en/studentthesis/design-of-an-enhanced-8051-microcontroller-core-architecture-in-idass-synthesised-with-asa(a956e7b6-b38c-4ece-94f0-9f5ea650c29b).html

Technische Universiteit

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Faculty of Electrical Engineering

Section of Digital Information Systems

Master's Thesis:

Design of an enhanced 8051microcontroller core architecturein IDaSS, synthesised with ASA

P.W.H. Heuts

Coach : Prof.ir. M.P.J. Stevens

Supervisor: Prof.ir. M.P.J. Stevens

Period : January 1994 - August 1994

The Faculty of Electrical Engineering of Eindhoven University of Technology does notaccept any responsibility regarding the contents of Master·s Theses.

Section of Digital Infonnation Systems

Abstract

Enhanced 8051 Core

This master's thesis describes the upgrading of the frequently used 8051 microcontroller. Theaddress range of the 8051 core has been extended from 64 Kbytes to 16 Mbytes. The stackdepth has been increased from 256 bytes to 64 Kbytes. To handle these extensions, theinstruction set of enhanced 8051 core has been adapted, but is still compatible to the standard8051 instruction set. Furthermore, the number of clock cycles needed to execute an instructionis reduced considerably.

The Section of Digital Information Systems of the Eindhoven University of Technologydeveloped an interactive design and simulation tool, called IDaSS. IDaSS is a very suitabledesign environment for complex hardware. The IDaSS library contains re-usable components,like processor cores and input/output interfaces. Interconnection of the library elementsimposes strict rules for the interfaces. The IDaSS design of the enhanced 8051 corearchitecture satisfies these specifications. Since the enhanced 8051 core ought to be suitablefor synthesising with the ASA Silicon compiler, restrictions of the 'idasstosid' convener andlimits of ASA have been taken into account while designing the architecture.

The CMOS 1.0 micron process technology is used in ASA. The synthesised enhanced 8051core consumes 28 mm2 of die area. The maximum clock frequency is 7.5 MHz. Although theclock frequency is relatively low, the enhanced 8051 core executes instructions four timesfaster than the standard 8051. Funher improvement of the enhanced 8051 core must be doneto increase the processor speed and to decrease the amount of die area. Redesigning the ALU,stretching out several instruction executions and manually making a data pad layout of theregister RAM are recommended actions.

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Contents

Enhanced 805 I Core

1 Introduction 1

2 Overview of the 8051 microcontroller 22.1 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 32.2 Special Function Registers in the Core . . . . . . . . . . . . . . . . . . . . . . . . . . .. 32.3 Addressing Modes 52.4 Boolean Processor 52.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52.6 CPU Timing 6

3 Upgrading the Standard 8051 Core 7

4 Core Interfaces 84.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 84.2 Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 94.3 Interrupt Interface 9

5 Enhanced 8051 Core Design for ASA 115.1 State Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 125.2 External Memory Interface 135.3 Internal RAM 145.4 Direct Addressing Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 165.5 Arithmetic and Logical Unit 175.6 Program Counter 195.7 ALU Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 215.8 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 225.9 Data Pointer 23

6 ASA synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24

7 Conclusions 26

References 28

Appendix A: MCS-51 Instruction Set 29

Appendix B: Enhanced 8051 Insuuction Set 30

Section of Digital Infonnation Systems Enhanced 8051 Core

Appendix C: Instruction Execution Time Specification 31

Appendix D: First IDaSS Design 36

Appendix E: IDaSS Document of the Enhanced 8051 Core , 39


1 Introduction

Enhanced 8051 Core

This report presents the results of my master's thesis. This final project is executed for theSection of Digital Infonnation Systems, Department of Electrical Engineering of theEindhoven University of Technology. The Section of Digital Infonnation Systems hasdeveloped an Interactive Design and Simulation System, abbreviated as IDaSS [2]. IDaSS isa design environment for complex synchronous (and in near future asynchronous) hardware.The design is described as a tree-like hierarchy of schematics. The schematics are enteredgraphically and represent elements like registers, ALUs, memories, and state controllers. TheIDaSS designs can be converted into an operational ASIC, using the 'idasstosid' and ASAtools provided by Sagantec. Complete automatic synthesis is not yet possible, because theconversion program 'idasstosid' cannot convert all the IDaSS functions and is not free ofbugs. FUlthermore, the ASA silicon compiler has specific limitations.

The target of the master's thesis was: design an upgrade of the 8051 microcontroller corearchitecture in IDaSS that can be synthesised with ASA. The upgrades consist of a linearaddress range extension to 16 Mbyte and a stack extension to 64 Kbyte. The instruction setis adapted to handle the extended address range, but the assembly source code is compatiblewith the standard 8051 instruction set.

The next section of this report gives a short overview of the standard 8051 microcontrollerfeatures. The enhancements of the standard 8051 are described in section three. The fourthsection specifies the standard memory, input/output, and interrupt interfaces. The interfacesprovide an easy connection of the enhanced 8051 microcontroller core with componentspresent in the IDaSS library. In section five the architecture of the enhanced 8051microcontroller core is clarified. The synthesis of the design in ASA is described in the sixthsection. Finally, section seven concludes this work.

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2 Overview of the 8051 microcontroller

Enhanced 8051 Core

A short overview of the 8051 microcontroller is given in this section. The 8051 is a memberof INTEL's MCS-51 8-bit microcontroller family [1]. The MCS-51 architectural blockdiagram is displayed in figure 1. The major microcontroller features are:

• an 8-bit central processing unit;• a Boolean processor;• 64 Kbyte address space for the external program memory;• 64 Kbyte address space for the external data memory;• 32 I/O lines;• multiplexed address and data lines;• a full duplex serial port;• a six-source interrupt structure with two priority levels;• three 16-bit timer/counters.

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- 2 -

Seclion of Digital Informalion Systems

2.1 Memory Organization

Enhanced 8051 Core

The 8051 has separate address spaces for the program memory and the data memory. Theprogram memory can be up to 64 Kbyte long and may partially reside on-chip. The 16-bitprogram counter is the addressing mechanism. The EA input detennines the instruction fetchfrom the internal ROM or the external program memory. The interrupt service routinesoccupy the ROM locations 03H through 32H. The start address after a reset is OOH.

The data memory can consist of up to 64 Kbytes of off-chip RAM and is only accessed whenan external move instruction is executed. The internal data memory is divided into threephysically separate and distinct blocks: the lower 128 bytes of the RAM; the upper 128 bytesof the RAM; and the 128-byte special function register area. While the upper RAM area andthe special function register area share the same address locations, they are accessed throughdifferent addressing modes.

In the lower RAM area four 8-register banks occupy locations OOH through 1FH. Only oneof these banks is enabled at a time through a two-bit field in the prOb'Tam status word. Thenext sixteen bytes, locations 20H through 2FH, contain 128 bit addressable locations. Thespecial function register area also has bit addressable locations.

An illustration of the memory organization is given in figure 2.

2.2 Special Function Registers in the Core

The 8051 microcontroller core can address 128 special function registers. Five of them arerelated to the core. A short description of their functionality is given below. The specialfunction address is mentioned between brackets.

• The accumulator register (EOH) is the most important source and/or destination registerprovided that arithmetic and logical operations are performed. The accumulator is alsoused during special move instructions;

• The B register (FOH) is used during multiply and divide operations. The B registercontains the multiplier or divider and receives the second result byte;

• The program status word register (DOH) reflects the program status information. Thestatus bits specify:

• Bit 0 is the parity flag. The parity flag shows whether the accumulator containsan even number of ones or not;

• Bit 2 is the overflow flag. The overflow is set to indicate that the operationgenerated a result outside the data range;

• Bit 3 and bit 4 are the register bank select control bits. The working register bankin the internal RAM corresponds with the binary contents of bit 4 and bit 3;

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• Bit 6 is the auxiliary carry flag and is used for packed decimal operations;• Bit 7 is the carry flag. The ALU uses the carry flag during arithmetic operations.

The Boolean processor applies the carry flag as accumulator.• The stack pointer register (81H) is 8 bits wide. In case of a push action, the stack pointer

is incremented before the data is stored. The stack may reside anywhere in the internalRAM, although it is initialized to start at location 08H after a reset;

• The data pointer consists of a high byte (82H) and a low byte (83H). Its intended functionis to hold a 16-bit address. The data pointer may be manipulated as a 16-bit register oras two independent 8-bit registers.

The accumulator, the B register, and the program status word are also bit addressable.

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2.3 Addressing Modes

Enhanced 8051 Core

The 8051 incorporates several addressing mechanisms which can each access a part of thememory spaces. The five addressing modes and the associated memory spaces are thefollowing:

• Register addressing has access to the eight working registers of the selected register bank.The least three bits of the instruction op code indicate which register has to be used. Theaccumulator, the B register, the data pointer, and the carry flag can also be addressed asregisters;

• Direct addressing is the only method of accessing the special function registers. The lower128 bytes of the internal RAM are also directly addressable;

• Register-indirect addressing uses the contents of the first or the second register in theselected register bank as a pointer to a location in the internal RAM or the lower 256bytes of the external data memory. Access to the full 64Kbyte external data memoryaddress space is accomplished by using the 16-bit data pointer. The stack operations alsouse register-indirect addressing;

• Immediate addressing allows constants to be a part of the op code instruction in theprogram memory;

• Base-register plus index-register indirect addressing allows a byte to be accessed from theprogram memory via an indirect move from the location whose address is the sum of abase register (the data pointer or the program counter) and the index register (theaccumulator). This mode facilitates look-up-table accesses.

2.4 Boolean Processor

The Boolean processor is an integrated bit processor within the 8051. It has its owninstruction set, accumulator (the carry flag), and bit addressable RAM and I/O. Thebit-manipulation instructions allow a bit to be set, cleared, complimented, jump-if-set,jump-if-not-set, jump-if-set-then-cleared, and moved to/from carry. Addressable bits, or theircompliments, may logically ANDed or ORed with the contents of the carry flag. The resultis returned to the carry register.

2.5 Instruction Set

The MCS-51 insu'uction set includes 111 instructions, 49 of which are single-byte, 45two-byte. and 17 three-byte. The instruction op code format consists of a function mnemonicfollowed by a "destination, source" operand field. This field specifies the data type and

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Section of Digital Information Systems Enhanced 8051 Core

addressing methodes) to be used. The complete insu·uction set of the MCS-51 family can beseen in appendix A. The insuuction set is divided into four functional groups:

• Data Transfer: These operations perform the internal and external data byte movements;• Arithmetic: The 8051 has four basic mathematical operations. Only 8-bit operations using

unsigned arithmetic are suppOlted directly. The overflow flag, however, permits theaddition and subu·action operation to selve for both unsigned and signed binary integers.

Arithmetic can also be pelfOlmed on packed decimal representations.• Logic: The 8051 performs basic logic operations on both bit and byte operands;

• Control Transfer: All control transfer operations cause, some upon a specific condition,the program execution to continue at a non-sequential location in the program memory.

There are three classes of control u'ansfer operations:• Unconditional calls, returns and jumps;

• Conditional jumps;

• Interrupts.

2.6 CPU Timing

The 8051 machine cycle consists of 12 oscillator periods. Most one-byte and two-byteinstructions execute in one machine cycle. Multiply and divide are the only insuuctions that

take more than two cycles to complete. They take four cycles. Responding to an interrupt

needs 38 to 81 oscillator periods. Regarding the oscillator frequency of 12 MHz, the meannumber of instruction executions per second is about 0.7 MIPS.

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3 Upgrading the Standard 8051 Core

Enhanced 8051 Core

The standard 8051 core. described in the previous chapter. has been upgraded. Theenhancements consist of enlarged address spaces. 16 Mbyte address space for both theprogram memory and the data memory is accessible now. The stack address space is extendedto 64 Kbytes. Space for eight additional instructions is created in the existing instruction map.The assembly source code is kept compatible with the standard 8051 instruction set. Still sixinstruction codes are free to implement new instructions (e.g. for a frame pointer).

The upgraded 8051 contains the following additions and adaptions:• 24 not multiplexed address lines.• 8 not multiplexed data lines.• A 16-bit stack pointer for the 64 Kbyte stack addressing. The stack continues to the

external data memory if the stack exceeds address FFH.• A 24-bit program counter for 16 Mbyte program memory addressing.• A 24-bit data pointer gives 16 Mbyte address space for specific external move operations.• The data pointer load instruction, op code 90H, has become a 4-byte insltuction to move

the 24-bit immediate data.• The absolute jump and subroutine call address range is reduced to a 1K page. This frees

eight op codes at the addresses 81H, 91H, AIH, BIH, CIH, DIH, EIH, and FIH in theinstruction set for new instructions.

• A global jump instruction, GJMP addr24, has been added with op code 81 H. This is a4-byte instruction that jumps to an address location in the 16 Mbyte program memory.

• A global subroutine call instruction, GCALL addr24, has been added with op code 91H.This is a 4-byte instruction that calls a subroutine at a location in the 16 Mbyte programmemory.

• The subroutine call instructions and the intelTupt routine call push a 3-byte return addressonto the stack.

• The return from subroutine call and interrupt instructions pop a 24-bit address from thestack.

The enhanced 8051 instruction set is to be seen in appendix B. The new and alteredinstructions are shaded.

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4 Core Interfaces

Enhanced 8051 Core

The IDaSS design ought to satisfy the specifications of the Object-Oriented (Hardware)System Design project library [3]. This library contains re-usable processor cores andinput/output controllers. With this library, building a custom processor to perform specifictasks is eased to the point that only a few library components must be picked from the library,interconnected in IDaSS and converted to silicon with ASA. To be able to interconnect theelements of this library, strict rules for the interfaces (hardware and timing) must be followed.The boundary of the enhanced 8051 core provides the connection to the program and datamemory, the input/output devices, and the interrupt controller. The configuration of theenhanced 8051 core is shown in figure 3. The va devices symbolise the timer/counters, serialport and so forth.

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4.1 Memory Interface

The interface to the program memory and the data memory consists out of four buses:• An 8-bit bidirectional data bus DATAbus;• The 25-bit address bus ADDRbus indicates which data word in the memory must be read

or written. The most significant bit (bit 24) determines the selection between the programmemory (%0) and the data memory (% 1);

• The 2-bit control bus CfRLbus This output bus controls the read and write action inmemory. The least significant bit (bit 0) indicates a read action. The most significant bit(bit 1) indicates a write action. The read and wlite strobes on the control bus are all active

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high, a one indicates an action is to be pelfonned. Simultaneously reading and writing isnot allowed;

• The I-bit ready bus Ready. This input bus is used for a simple handshake protocol thatallows synchronisation of slow memories. The ready condition signals the last clock cycleof a memory access cycle with a non-zero value.

Whenever a read or write action is started the output must be kept stable until the readysignal is detected. A zero value puts the processor on hold.

4.2 Input/Output Interface

The input/output interface pelforms the access to the special function registers outside theprocessor core. The input/output interface is fitted with a separate input and output data busto be able to update a special function register within a single clock cycle. The combinedcontrol and address bus is used to indicate the operation to be performed. No handshake isdone in hardware. The input/output interface uses three buses:

• The 8-bit data output bus SFRo;• The 8-bit data input bus SFRi;• The lO-bit control/address bus SFRaddr. This output bus is build up with the special

function register address (bit 0 through bit 7), the write bit (bit 8), and the read bit (bit9). The read and write bits are both active high. A read-modify-write action is performed,when bit 8 and bit 9 are ones at the same time. If no input or output is performed, biteight and bit nine should be zero and the address bits may take any value.

4.3 Interrupt Interface

I/O devices must be capable of intetTupting the processor core with which they arecommunicating. An extemal intetTupt controller (present in the library) detects interrupts takenpriorities into account, and outputs an interrupt vector. In this case extra interrupt maskingflags within the processor core are not necessary.

The interrupt interface consists out of two buses:• The 3-bit interrupt vector bus Ireq. This input bus contains the inten-upt number generated

by the interrupt controller. All bits high (value 7) indicates no interrupt. The other sevenvalues specify the interrupt routine to be performed. If more intelTupt vectors are requiredin the future, the inten-upt vector bus width can be increased. In that case all bits high stillindicates no interrupt request;

• The 2-bit handshake bus lack. This output bus signals to the interrupt controller whetherthe processor core started or finished interrupt handling. When bit 0 is one clock periodpulse high (% 1), the core has started handling the interrupt routine indicated by the vector

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on the interrupt vector bus during the previous clock cycle. A one clock period pulse high(% 1) of bit 1 indicates that the processor core has finished an interrupt routine. This pulseis used within the intenupt conn'oller to select the next interrupt for handling and resetmask bits automatically. The interrupt controller does not generate a new interrupt vectorin the clock period which follows the inten'upt routine end pulse.

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5 Enhanced 8051 Core Design for ASA

Enhanced 8051 Core

The purposes mentioned below have been taken into account as the architecture of theenhanced 8051 core was designed.

• The core intelfaces have to satisfy the specifications for IDaSS library components;• The number of clock cycles necessary to execute an instruction ought to be restricted to

a minimum;• The design must be suitable for synthesising with the ASA silicon compiler;• The design may not explode in complexity and size.

In essence, the requirements mentioned are contradictory. The processor perfonnance is inproportion to the die area consumption, wherein an optimum has to be found. The enhanced8051 core reads sequentially the instruction code bytes from the program memory. In the lastcycle of the instruction execution the next op code is fetched. This method is calledprefetching. In contrast to pipelining, prefetching does not request a lot of additional controllogic. By means of prefetching, one clock cycle is saved with loading the instruction bytes.Further on, the architecture is designed to perfonn the instruction execution as quickly aspossible. The modification of data bytes occurs within one clock cycle independent of theaddressing mode, although only the input/output interface dictated the one clock cycle datamodification. The consequence is that the internal data bus structure consists of unidirectionaldata buses. In combination with the several addressing modes, the data buses will consumea considerable amount of die area.

The architecture of the enhanced 8051 core has been designed in IDaSS. At first, a designwithout any restrictions has been made. This ideal architecture, briefly described in appendixD, cannot be synthesised with the ASA silicon compiler. Therefore, a new architecture hasbeen designed specifically for synthesis with the ASA silicon compiler. Designing for ASAmeans many restrictions have to be taken into account. On the one side, some useful IDaSSfunctions are simply not suppOlted, on the other side the hardware consequences have to beexaminated. For example, the functionality of an IDaSS register is very extensive. In ASA,the IDaSS register functionality is implemented via counters and adders. To avoidredundancy, it is recommended to use only the basic register functionality and put the extrafunctionality in an additional operator.

The converter 'idasstosid' and the ASA silicon compiler each have their limitations [4]. Manylimitations can simply be get around, but two problems have influenced the architecturedesign. At first, an asynchronous signal, like the handshake signal of the external memories,has to be detected without losing a clock cycle. The solution resulted in an implementationof an internal bus intelface which is described in subsection 5.2. The second restriction comesfrom ASA that only has synchronous read RAM. This means that every read or modify action

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Section of Digital Inform:llion Systems Enhanced 8051 Core

with a RAM data byte needs two clock cycles. Therefore, the register banks in the internalRAM are implemented as registers to increase the execution time. Details are given insubsection 5.3.

Figure 4 displays the entire enhanced 8051 core architecture in IDaSS. The architecture iscomposed of subschematics. The functionality of the subschematics is explained in thefollowing subsections. The design is based on small autonomous operators and a simple statemachine instead of putting the whole intelligence in a complex, ergo large and slow, statemachine. Appendix E contains the entire IDaSS description.

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5.1 State Controller

The state machine ARBITER has eight states and co-ordinates the core activities. The firststate is the wait state during the multiply or divide instruction execution, but serves also asthe start up state after a reset. The next four states fetch the instruction bytes from theexternal program memory. After all the instruction bytes are fetched, a lO-bit instruction codeword is generated in the IR_Sel subschematic. The state machine selects a 2-bit code to beconcatenated to the instruction register IR. The resulting lO-bit instruction code word indicatesthe instruction execution status and runs through the whole design to drive the operators.Some comprehensive insuuctions, like the move code byte and the move external, arepartially handled by the state machine. In that case, relatively simple state descriptions fulfil

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the remaining complex operations. The last three states provide the program counter push ontoand pop from the stack during calls and returns.

5.2 External Memory Interface

The BUSIFACE subschematic, to be seen in figure 5, provides the external memory access.According to the memory interface as described in subsection 4.1, a ready signal indicates thelast cycle of a memory access. Unfortunately, IDaSS signals are not supported by theconverter 'idasstosid'. So, the Ready signal had to be clocked into a register which can bechecked in the state machine. Around the ready register RDY, an external memory interfaceis constructed to control the external memory access. If the continuous loading RDY registercontains the value one, an external memory access has completed and the next processor

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action can occur. Normally, the program counter unit drives the external memory interface,but the SPwrop operator can switch the ADDR_op and WR_op multiplexers over to anexternal stack access.

An external memory access starts when the WR_CTRL subschematic receives a read or writesignal. At the same time, the Addcout subschematic contains the external memory address.During a write cycle the Data_out subschematic outputs the data. The external memoryinterface continues the memory access until the ready signal is detected to support slowresponding external memories. Therefore, the output status is retained in the Addr_out,Data_out, and WR_Ctrl subschematics. In case of a read cycle the Data_in subschematic isactive instead of the Data_out subschematic and one of the four data input registers will beloaded. The data input registers are the instruction register IR, the immediate data register 1M,the direct address register AR, and the relative jump offset register REL. Placing theseregisters in the external memory intelface avoids a delaying data movement from a data inputregister to one of the four registers elsewhere in the core. The register selection operator RSopdetermines the data input register to be loaded. The RSbuf register buffers the registerselection code word during a slow read cycle.

Because the converter 'idasstosid' is incapable of performing bidirectional busesautomatically, the continuous data output bus DATobus, the data input bus DATibus and theI-bit three-state driver bus enable are connected manually to the 8-bit bidirectional data busby editing the SID-file.

5.3 Internal RAM

The RAMunit subschematic, shown in figure 6, comprehends the 256 byte on-chip RAM.Unfortunately, the ASA RAM is functionally different from IDaSS RAM. The ASA RAMread behaviour is synchronous, though in IDaSS it is asynchronous. Writing is asynchronousas in IDaSS. In essence, only a single valid IDaSS RAM model can be converted intoworking silicon. The IDaSS library contains RAM models for simulation and synthesis. Thesimulation model imitates the ASA RAM behaviour in IDaSS and is replaced with anequivalent convertible model before synthesis. The design contains the control bus drivenmodel BUSIMPL.

The synchronous read behaviour means that the data is delayed one clock cycle before it isavailable for further operations. This results in a two clock cycle register addressing executionand even four clock cycles for the execution of indirect register addressed instructions. Toobtain faster (indirect) register addressing, the four RAM register banks (the lowest 32 bytes)are implemented as registers. These 32 registers, situated in the ASALRAM subschematic,consume nevertheless much more die area than ordinary ASA RAM. Besides that, the partial

- 14 -


RAMADDR

ADDR

NIlo

llJI

• INa

JiU'M$eleotIADDJt

Figure 6: The internal RAM.

register RAM implementation requires an extra address decoder and a RAM selector. TheRAMSelect and ADDRgen operators represent the RAM selector. The ADDRgen operatorsubtracts 20H from the ASA RAM address, because the ASA RAM starts at address DOH. Asa consequence of the synchronous read behaviour, the modification of an ASA RAM databyte within one clock cycle demands buffers and some extra logic. The HWmod registerstores the one clock cycle delayed modify (i.e. write) signal which activates the HRAMoperator the next clock cycle. The RAM address is stored in the HADDRbuf register.

The DVop operator builds the 2-bit RAM data valid signal from the RAM control signals.The RAM data valid signal constitutes the automatic instruction execution handling.

The most significant bit (bit 2) of the RAM control bus RAMIWR indicates the indirectregister addressing mode if set. The indirect address is read in the selected register bank andstored in the IADDR register. The next clock cycle the indirect addressing is performed withthe control signal buffered in the IWR register.

The Busyop operator and accompanying Busy register avoid a new RAM access until theRAM data valid signal of an earlier access is generated. The state machine overrules the busyprotection during the execution of insu'uctions which may access the RAM in successiveclock cycles. The RAMDATobuf subschematic stores the latter RAM data output to rectifythe difference in RAM access time.

- 15 -


The RAM_SEL subschematic, shown in figure 7, provides the internal RAM control signalsand addresses. The REG_SEL operator generates the (indirect) register addresses and controlsignals. The IWR_Sel operator multiplexes the RAM addresses and control signals.

SFR

PSWi

RAMIWR

RAHADDR

RAMIWR RAHADDRREC_SEL

D--.----13· I R PS W i .:;:.I-----aIR

SPWR

SPaddz-

1OI-----1:!l. S PWR RA H I WR fllI------tai

:======~ . SPad.dz- RAHADDR l!!J----, ;:=======:IWR_SEL

S FR 8-1-----,

• RECIWR RECADDR.

Figure 7: The internal RAM address and control signal generator.

5.4 Direct Addressing Controller

Figure 8 shows the DIRECT subschematic where the direct addressing is arranged.The RWop operator generates the 2-bit read, write, or modify code word for the directaddressed data byte. In the AR_SEL operator the RW code word is concatenated to the directaddress byte. In case of bit addressing the address byte containing the bit address is selected.

DI Ro g...-.... ::===:::::::DIRig...--illI

DIRbu~~e~ ::=====:out 1Dt---a

IR ~=====:~===;:------'

AR.

RWopRlf

• RW

1lH----B. DP 1

~====~ .SPi• WlMi PSWi •

Dh'_Sel

• SFRI RAMDU B'------4~• SFRaddr DIRDU • rDIRDU

• SFR DI Ro c----,

Figure 8: The direct addressing mode control unit.

- 16 -


The Dir_Sel operator, controlled by the lO-bit SFR output of the AR_SEL operator,multiplexes the direct data input, chives the external special function register controVaddressbus SFRaddr and generates the I-bit direct data valid signal DIRDV. The DIRDV signalindicates the direct access status, since the ASA RAM is also partially directly addressable.In spite of the different data access times, all the direct data are modified within one clockcycle.

The DIRbuffer subschematic serves as buffer to eliminate the timing problem with the movedirect byte to direct and (indirect) register instructions. The direct data byte is only stored ifit is not obtained from the ASA RAM. The following clock cycle, the buffer outputs the databyte or transits the ASA RAM data byte.

5.5 Arithmetic and Logical Unit

The arithmetic and logical operations take place in the ALUunit subschematic, to be seen infigure 9. Furthermore, the ALUunit detelmines the I-bit conditional jump vector Jts1.

Bito

DU t 1 1lI---+--EJDulZ

In1

in2

Biti

Bitt Bito

BYTEopL....-_-EJ. i n1 aut1 s------'

ALUs

r+--t--HllII'S Wi !'SiloI R Jts t 1lI---+-h r-----,

Jts t liI--+f-J l- --'

'-t------a. I'SWi I'SlloBOOL

1l5-----DCTRL DIRDUDU_CTRL

RAMDU

AR

A

1M

Figure 9: The arithmetic and logical unit.

The ALUunit consists of a byte and a bit processor. Figure 10 shows the byte processingsubschematic ALUs. The byte operations have been distributed among four ALUs, because

- 17 -


ASA is not capable of synthesising a complex block like one huge ALU. The lO-bit addersin ALUI and ALU2s are re-used by means of performing similar operations with the sameASA library element. This implies some adaption to the function descriptions, but the amountof generated hardware is reduced to a minimum. The bit processing occurs in the BOOLoperator. The bit is extracted from the direct data byte in the BYTEop operator. The threeleast significant bits of the AR register indicate the bit number.

The multiplexers ALUinlMUX and ALUin2MUX pick out the data bytes in such a way thatplural function implementation could be prevented. The ALUunit also transits data bytesduring move instructions which results in less routing and smaller multiplexers in the core.Since the ALU is always present in the critical path and three-stated output ports are slow,the ALU output ports are multiplexed.

--P out!. I::: InJ. ou tJ. ::: ;:: ALUJ. outJ. III ,....-

::: in2 ~ALU2

ALUJ. ALUou tJ.HUX

r-·"'U

;

Ps ....o - ,.- l=J ALU3

Jtst:1--0 It'

I-I:J inJ. ou tJ. : out2 - ~ out2

::: In2 outZ:?T

-1- l:J ALU2

ALU2 -C I ALUout2HUX

:::PSWi Ps ....o [if- THP ~1;J.LU3a THP [if-.

1Cf---<I--

~::: inJ. ou t!. :: '---l:J ALUJ. PSWo _ FPs ....o It po. 00"- IL-l=J ALU2

I CNTR I ALU3 ALUPSWoHUX

: tII-~ PSWi PSWo ~ ;:: ALU3

IR .------ l:J ALU41Cf---<

I ":- inJ.inJ.

~ ALUJ. Jtst :: ~ Jtst I~

I in2 l::: in2

ALU4 ALUJtstHUX

I PS .... I l:::PSWi Ps ....o ::

Jtst _ I.;oALU4IC>"'-

Figure 10: The byte processors.

In ALUI one lO-bit adder performs the execution of the increment, decrement, add, add withcarry, and subtract with borrow instruction. Unfortunately, the re-use of the lO-bit adder could

- 18 -


not proceed with the multiply and divide instruction, because the operator became toocomplex for logic optimisation in ASA. Therefore, a second lO-bit adder is present in ALU2.In ALU3 two 4-bit adders were needed to execute the decimal adjust instruction. Joining thisinstruction in ALUI or ALU2 resulted again in too complex operators. At last, ALU4 containsan 8-bit unsigned compare less than operator to set or reset the carry flag during the compareand jump if not equal instruction execution. All in all, a redesign of the four ALUs shouldbe done to improve the re-use of the ASA library elements which reduces the total die areaconsumption.

The multiply and divide instruction executions take eight clock cycles. In this way, thehardware requirements have been restricted to a minimum. In the future, the multiplicationand division can be speeded up, if desirable. The CNTR register is used as counter to indicatethe number of passed multiply or divide cycles. The TMP register, attached to ALU2,contains the temporary results during a multiplication or division.

The DV_CTRL operator generates the I-bit control signal CTRL which indicates that the dataon the buses is valid and can be stored. Depending on the instruction code, the CTRL signalis the read or write bit of the RAM data valid signal or the direct data valid signal DIRDV.

5.6 Program Counter

The PCunit subschematic, shown in figure 11, provides the intenupt handling, new programcounter contents and memory addressing. Because of the variable instruction execution length,in particular as a consequence of synchronous read RAM, the CTRL signal arisen from theDV_CTRL operator in the ALUunit was needed to indicate the end of an execution cycle.

If the intenupt number register Ino contains a value between zero and six during the lastinstruction execution cycle, an intellllpt is requested. In case of an intelTupt request the INTRoperator generates the 2-bit interrupt acknowledge signal and stores the program counter. Theinterrupt acknowledge signal activates the lop operator that sets the I-bit register I to indicatethe interrupt handling. The state machine decodes the I register in state STAGEI and pushesthe first byte of the program counter onto the stack. The states STACKI and STACK2 pushthe remaining two program counter bytes onto the stack. The last state STACK3 resets theinterrupt handling register I and loads the program counter with the interrupt routine address.

When no inten'upt is requested, the CTRL signal is used for prefetching. The CTRL signalactivates the read signal in the WR operator and the PCinc operator via the PCop operator.The PCinc operator increments the new program counter value before loading it into theprogram counter register Pc. In this way, the program counter register always represents thenext instruction fetch address. The program counter register is continuously loading, exceptfor the move code byte instruction executions.

- 19 -


Data

out

PCLuJ'

PCIPCdatop

PCela t 1lII-----a

PCo RAM e.--+--ill• Ina 1M • ~===:::::::

PCloulop

PCI J)P •PCadgen

• RAM ADJ)R D----a ADJ)Ro

D--+---i:J. PCI A e·--Ill"'---G11 II PCIJ''" PP ~=====:

• PCLuJ' PCo

RS

Ii lop 10

Ina

CTIlLI •IHTR

laok CTIlLo 1I---+f--tD

• laokililCkop

lacko .

.J t s t 11------8. J t s ti .J t s to D·-1--C1CTIlLop

CYRL a------G. CTRLI CTRLo·

Figure 11: The program coulller Ullil.

The RELop operator adds the signed 8-bit offset byte REL to the program counter. If the Jtstsignal appoints a ShOlt relative jump, the JUMP operator transits the branch address insteadof the program counter contents to the PCgen operator. The jump, call and return addressesare generated with the PCbuf register contents in the PCgen operator. The move code byteaddress is also calculated by the PCgen operator. Then the PCadgen receives the new programcounter contents. The PCadgen operator provides the addresses for the external programmemory and the external data memory. If an address is allocated to the external programmemory, a zero bit is concatenated in front of it. During the move external instructions themost significant address bit is a one.

The PCbufop operator an'anges the storage of the new program counter bytes in the PCbufregister during jumps, calls, interrupt handling and returns (from interrupt). The input comesfrom the internal memory, the external memory, or the interrupt number register. During callsand interrupt handling the PCdatop operator extracts the program counter bytes to be pushedonto the stack.

The program counter increment following upon a relative jump calculation means two 24-bitadd operations in succession. These adders return in the critical path and slow down theprocessor operation frequency dramatically. Therefore, it is recommended to re-design the

- 20-


PCunit in the near future and omit the prefetching after a relative jump to increase theprocessor speed.

5.7 ALU Related Registers

The SFR_core subschematic, shown in figure 12, contains the accumulator register A, theprogram status word register PSW, and the B register which are primary related to the ALU,but also directly addressable. Since each register has the same modification logic, the 'X' inthe operator names below replaces the registers names.

f=GlSFR I I SFR41c 1-

~SFR• SFR.:. 1-DlrAop Di I'PSWOP •~ Dil'Bop

r- CAW I CTRL *- PSWW BWI:ii I-

'- 8 DirAW g .....~

- § Dil'PSWWG c- I IR ~~g DirBWI:If-

AWop PSWWop BWopr- r:.JAW CTRL::: ;:: CT RL PS WW [l ,... - r:.JBW

'- g ~PJ

~P PSWWG r-<"- - gA 1 B

- 8 rE - PSWo:

L-E PSW~III

PSWop

r:.JPPSWi G r----- II Bo-- CA g - Pop l3 in out IS

- 8 Direct - 8A,::B Direct IiAiHUX -

PSW .- 8 ALUout2 BiHUX

8 ALUout1. DirDat ~ r-~ ALUout2 g -.-l3 Di I'ec t !fro-PSWiHUX

ALUout1. ALUPSW ~ ~ ALU psw 1:i1lr-- ~ ALUout2 I

Figure 12: The ALU related registers.

The direct addressed write signal is extracted from the SFR bus in the DirXop operator. TheXWop operator generates a write signal depending on the instruction code word or transit thedirect write signal. The accumulator and the program status word write signal is only validif the CfRL signal is high (% l). The XiMUX operators multiplex the new register contents.

The program status word is split up into two registers; one for the parity bit, the P register,and the other one for the remaining seven status bits, the PSW register. The PSWop operator

- 21 -


provides the 8-bit program status word output and the new contents for the PSW register. TheParity register, bit 0 of the program status word, represents the even parity of the accumulator.The actual accumulator contents determine the parity via the Pop operator. So, the parityupdate is one clock cycle delayed and does not contribute to the critical path length anymore.In spite of this delay, the COlTect program status word is available when it is addresseddirectly. In that case, fetching of the instruction bytes overlaps the delay.

5.8 Stack Pointer

The stack pointer is placed in the SP_CfRL subschematic, shown in figure 13. The t6-bitstack pointer is divided into a low and high byte for the direct addressing mode. The specialfunction registers SPL and SPH take possession of the addresses 8tH respectively 85H. TheSP_Sel operator extracts and SPL and SPH from the stack pointer. The SPop provides themodification of the continuous loading stack pointer register SP_reg.

SPJ-eg

SFR

1Df-----fil. S PiSP ~ 6 0 [8]xf-----I-Il!I. S P 0 U t 0·'f------I!)

SP_Se 1 c SPop

IOI----{]., SPo SP~6 i [!:.}--+--I:!I- in

SPadd~

WRSTACK

WRosPyoP

rC:J----.--m. WR i

L...-----------l8J SPo

STACKop

I-----------<....,~.ADDRo

SPWR

Figure 13: The stack pointer logic.

- 22 -


The stack pointer addresses the 64 Kbyte stack. The stack may reside anywhere in the internalRAM and can be continued to the external data memory. The STACKop operator containsa 16-bit adder to perform the push and pop addresses and increments respectively decrementsthe stack pointer at the same time. Since the STACKop operator modifies the stack pointerduring stack operations, the stack pointer register needs no extra functionality. The statemachine controls the STACK operator which generates the stack write/read control signal. Incase of popping SPL or SPH from the stack, the stack pointer may not be decremented. Thisexception is obtained with the NoDec operator. Although this exception is compatible withthe standard instruction set, this special case may be removed for the extended stack pointeron account of diminished profit.

The decoding complexity in the state machine had to be reduced for the stack operations. Thisis achieved by decreasing the number of decoding bits. During a pop from the stack thePOPop operator encodes the 16-bit POP address into a 3-bit code word and stores it in thePOPreg register. Five code words distinguish the register RAM, ASA RAM, external RAMand the transitions between the different kinds of memories. The POPreg register contentsdetermine the movement of the popped data and is controlled by the state machine. The stackvalid register SV points out the end of a stack operation. In case of an external access the SVregister is loaded with the ready signal, otherwise the SVop operator loads the SV registerwith a one. The I-bit SV register replaces also the stack pointer decoding in the state machineduring push operations.

5.9 Data Pointer

The data pointer is placed in the DP_reg subschematic, to be seen in figure 14. The 24-bitdata pointer is divided into three bytes in the direct addressing mode. The three data pointerbytes DPL. DPH and OPE take possession of the special function register addresses 82H,83H, and 84H, respectively. The DP_Sel operator extracts the addressed byte from the datapointer. The data pointer register DPreg is default loading. Therefore, the operator DPop giveson the old data pointer contents unless the data pointer has been modified.The data pointer can be loaded with a new constant. During this instruction execution theDP_CTRL operator generates the data pointer special function addresses to replace the datapointer register contents with immediate data. In this way, the internal structure is re-used.

- 23 -


IR

DPo

DPo ~----'

SFR

1M

Di~Dat

• SFR

• I M DPs£~E·<I--I---------.....----;gc out m-----.,rn c• DPi DPop DP~eg

DP_CTRL • DPi DP240 ~·I-+----.,rn·DP in l!J'~---181

DP_Sel

.. DPo DP24 i [!J.I------------.

Figure 14: The data poillter logic.

The data pointer increment makes use of the IDaSS register increment function, however thedata pointer is implemented as a 24-bit counter in ASA. On the other hand, the instructionexecution takes only one clock cycle.

- 24 -


6 ASA synthesis

Enhanced 8051 Core

Before the ASA silicon compiler can be used, the IDaSS design must be converted to theASA description language SID by means of the conversion tool 'idasstosid'. The conversionsucceeded after some changes in the IDaSS design, like renaming reserved words, adaptingthe control connector coding to the binary form and appending a parallel input connector tothe control connector if an operator function uses the control value. In the SID-file thebidirectional data bus is connected. Also, the type parameter of the IDaSS registers and theadders have been set to maximum speed in the expense of die area consumption. Sometimesthe mysterious error 'segmentation fault' appeared after the design had been changed. In thatcase, the only solution was pelforming the changes in the previous design in another way.

In first instance, the ASA compiler had a problem with deeply nested state machines. Theconverter had cut off some states, because 'idasstosid' restricts the line length to 80characters. Since deeply nested state machines explode in complexity, the states have beenrewritten with less transitions. FUl1hermore, the test conditions must be kept simple. Forexample, testing the 16-bit stack pointer register contents was too complex and was replacedby testing the 3-bit POPreg register. On the other hand, cenain operators have been simplifiedor even split up, as the ALUs, to perfOlm the logical optimalisation in ASA.

After the conversion to gates, a dummy inverter is added to the STACK operator in the SIDfile, because the STACK operator contained no logic. The dummy inverter is removedautomatically when the layout is made.

The synthesis time reduces considerably when a control connector calls a function only once.Now, the synthesis of the complete design to a layout takes only three hours. The total diearea consumption is 28 mm2

• The maximum clock frequency is 7.5 MHz. In appendix C, thenumber of needed execution clock cycles is listed per instruction. Broadly, an instructionexecution takes the same number of clock cycles as instruction bytes. An ASA RAM accesstakes one clock cycle more and stack operations take three clock cycles extra. Since about 40percent of the instruction set is executed in one clock cycle and around 50 percent of theremaining instructions is executed in two or three clock cycles, the mean number ofinstruction executions per second is approximately 3.5 MIPS.

The response to an intenupt request takes between four and eleven clock cycles. The responsetime includes finishing of the instruction execution (one to seven clock cycles), pushing theprogram counter onte;> the stack (three clock cycles) and fetching the first byte of the interruptroutine (one clock cycle).

- 25 -


7 Conclusions

Enhanced 8051 Core

The designed enhanced 8051 core can address 16 Mbyte of external memory and has a 64Kbyte stack depth. The instruction set is adapted, but is still compatible with the standard8051 instruction set. The core satisfies the IDaSS library interfaces and is synthesised withthe ASA silicon compiler.

The synthesis technology is the CMOS 1.0 micron process. The architecture die areaconsumption is 28 mm2

• The ASA timing analyzer calculates a maximum clock frequency of7.5 MHz. This frequency is based on the longest path in the circuit. In practice, this path willnot be the real critical path in the circuit, thus the enhanced 8051 core can probably operateon a higher clock frequency.

The Idass register implementation of the four register banks in the internal RAM demands anincredible amount of die area. Making a data pad layout of the RAM register part manuallyin ASA is compacter and saves a lot of die area. It is a pity that ASA only has synchronousread RAM. The presence of asynchronous read and wl;te RAM would simplify the RAMunitconsiderably. The additional control logic that serves the ASA RAM byte modification andthe selection between the ASA RAM and the RAM registers becomes unnecessary. Also theCTRL signal can be removed, because the execution time of every instruction is fixed in thatcase.

The 24-bit adders in the program counter unit cause a part of the long critical path length.Abandon the prefetching, e.g. during a relative jump execution, prevents two 24-bit addoperations in succession. Pelforming the add operations by means of one 24-bit adderincreases clock frequency and saves much die area too.

The four byte processors in the ALUunit do not optimally re-use the hardware libraryelements. Redesigning the byte processors in such a way that only one lO-bit adder isnecessary to pelform all the arithmetic operations reduces the hardware requirements and thecritical path delay. The operator which contains the lO-bit adder receives the data input viasome intelligent multiplexers in order to avoid a too complex operator for ASA optimization.

Furthermore, it is recommended to update the instruction set. Some exceptions, such as nodecrement after popping stack pointer low or high byte, are not relevant anymore and can beremoved. If the stack would only reside in the external data memory, the extra stack logic inthe SP_CfRL subschematic becomes superfluous and the three STACK states in the statemachines can be integrated in other states. This will result in a less complex state machine.

- 26 -


The instruction execution needs a minimum of clock cycles; 40 percent of the instructions isexecuted in one clock cycle and 50 percent of the insuuction executions takes two or threeclock cycles. Since the clock frequency is 7.5 Mhz, the mean number of instructionexecutions per second is estimated at 3.5 MIPS. The standard 8051 runs at 12 Mhz, but needsat least 12 clock cycles for an instruction execution. So, the enhanced 8051 core is four timesfaster than the standard 8051 core.

Finally, further conformations as described above will improve the core performance. A10 MHz clock frequency and 30 percent die area save should be achievable.

- 27 -


References

[1] INTEL, "Microcontroller Handbook", USA, 1984.

Enhanced 8051 Core

[2] Verschueren, A.C., "IDaSS for ULSI", IDaSS manual VO.08d, Internal publication ofthe Eindhoven University of Technology, Department of Electrical Engineering, Sectionof Digital InfOlmation Systems, the Netherlands, July 20, 1990.

[3] Verschueren, A.C., "Specification of the standard system and I/O buses for the ObjectOriented (Hardware) System Design project library", Internal publication of theEindhoven University of Technology, Department of Electrical Engineering, Sectionof Digital Infotmation Systems. the Netherlands, April 21, 1993.

[4] Verschueren, A.C.. "IDaSS does and don'ts to enable synthesis of ASIC's with theASA silicon compiler", Intemal publication of the Eindhoven University ofTechnology, Department of Electtical Engineering, Section of Digital InformationSystems, the Netherlands, September 17, 1993.

- 28 -


Appendix A: MCS-Sl Instruction Set

Enhanced 8051 Core

L 0 I 2 3 4 5 6 .. 7 8 .. FH

0 NOP AJMP UMP RR INC INC INC INCpage 0 addrl6 A A dir @Ri Rn

I JBC ACALL LCALL RRC DEC DEC DEC DECbit. rei page 0 addrl6 A A dir @Ri Rn

2 JB AJMP RET RL ADD ADD ADD ADDbit. reI page I A A. #data A. dir A.@Ri A.Rn

3 JNB ACALL RETI RRC ADDC ADDC ADDC ADDCbit. reI page I A A. #data A. dir A.@Ri A.Rn

4 JC AJMP ORL ORL ORL ORL ORL ORLrei page 2 dir. A dir. #data A. #data A. dir A.@Ri A,Rn

5 JNC ACALL ANL ANL ANL ANL ANL ANLreI page 2 dir. A dir. #data A. #data A. dir A.@Ri A.Rn

6 JZ AJMP XRL XRL XRL XRL XRL XRLreI page 3 dir. A dir. #data A. #data A. dir A.@Ri A.Rn

7 JNZ ACALL ORL JMP MOV MOV MOV MOVrei page 3 C, bit @A+DPTR A. #data dir. #data @Ri. #data Rn, #data

8 SJMP AJMP ANL MOVC DIV MOV MOV MOVrei page 4 C. bit A.@A+PC AB dir. dir dir. @Ri dir, Rn

9 MOV ACALL MOV MOVC SUBB SUBB SUBB SUBBDPTR. page 4 bit. C A.@A+DPTR A. #data A. dir A.@Ri A,Rn#datal6

A ORL AJMP MOV INC MUL MOV MOVC. /bit page 5 C, bit DPTR AB @Ri, dir Rn. dir

B ANL ACALL CPL CPL CJNE CJNE CJNE CINEC. /bit page 5 bit C A. #data. A. dir. @Ri. #data. Rn, #data.

reI reI reI reI

C PUSH AJMP CLR CLR SWAP XCH XCH XCHdir page 6 bit C A A. dir A.@Ri A.Rn

D POP ACALL SETB SETB DA DJNZ XCHD DJNZdir page 6 bit C A dir. reI A.@Ri Rn. reI

E MOVX AJMP MOVX MOVX CLR MOV MOV MOVA,@DPTR page 7 A.@RO A.@RI A A, dir A.@Ri A.Rn

F MOVX ACALL MOVX MOVX CPL MOV MOV MOV@DPTR. A page 7 @RO.A @Rl,A A die. A @Ri.A Rn.A

- 29 -


Appendix B: Enhanced 8051 Instruction Set

L 0 2 3 4 5 6 .. 7 8 .. FH

0 NOP AJMP UMP RR INC INC INC INCpage 0 addr16 A A dir @Ri Rn

JBC:fJ~11 ~£~: RRC DEC DEC DEC DEC

bit, reI .~g<lfl§) A A dir @Ri Rn

2 18 AJMP RL ADD ADD ADD ADDbit. reI page 1 A A, #data A, dir A, @Ri A, Rn

3 JNB )XC,.\I..i.t RRC ADDC ADDC ADDC ADDCbit. reI Pht~l A A. #data A, dir A, @Ri A, Rn

4 JC AJMP ORL ORL ORL ORL ORL ORLreI page 2 dir. A dir. #data A. #data A, dir A, @Ri A, Rn

5 JNC ACAJ.,I.) ANL ANL ANL ANL ANL ANLreI P~g9g< dir, A dir. #data A. #data A, dir A. @Ri A, Rn

6 JZ AJMP XRL XRL XRL XRL XRL XRLreI page 3 dir, A dir, #data A. #data A. dir A, @Ri A, Rn

7 JNZ

i~1ORL MOV MOV MOV MOV

rei C, bit A, #data dir, #data @Ri, #data Rn, #data

8 SJMPI

ANL DIV MOV MOV MOVreI C, bit AB dir, dir dir, @Ri dir, Rn

9 SUBB SUBB SUBB SUBBA, #data A, dir A, @Ri A, Rn

A MUL MOV MOVAB @Ri, dir Rn, dir

B ANL CPL CJNE CJNE CJNE CJNEC, /bit C A. #data, A, dir, @Ri, #data, Rn, #data,

reI reI reI reI

C CLR SWAP XCH XCH XCHC A A, dir A, @Ri A, Rn

D SETB DA DJNZ XCHD DJNZC A dir, reI A, @Ri Rn, reI

E MOVX CLR MOV MOV MOYA, @Rl A A, dir A. @Ri A, Rn

;.;.:::::::.:;:;:;:::::;:;:;:;:::;::

F MONX MOVX CPL MOY MOY MOY

~Bgm;:~.: @RI, A A dir, A @Ri, A Rn, A

- 30-


Appendix C: Instruction Execution Time Specification

Table 1. Arithmetic operation execution time.

Mnemonic Instruction bytes Execution cycles Execution cyclesenhanced 8051 core standard 8051 core

ADD A. Rn 1 1 12

ADD A, direct 2 2-3 12

ADD A,@Ri 1 2-3 12

ADD A, #data 2 2 12

ADDC A. Rn I 1 12

ADDC A, direct 2 2-3 12

ADDC A.@Ri I 2-3 12

ADDC A, #data 2 2 12

SUBB A, Rn 1 1 12

SUBB A, direct 2 2-3 12

SUBB A, @Ri 1 2-3 12

SUBB A, #data 2 2 12

INC A 1 I 12

INC Rn 1 I 12

INC direct 2 2-3 12

INC@Ri 1 2-3 12

DEC A I 1 12

DECRn 1 1 12

DEC direct 2 2-3 12

DEC@Ri 1 2-3 12

INC DPTR 1 1 24

MULAB 1 8 48

DIV AB 1 8 48

DAA 1 1 12

- 31 -


Table 2. Logical operation execution time.

Enhanced 8051 Core


ANL A. Rn 1 1 12

ANL A. direct 2 2-3 12

ANL A.@Ri 1 2-3 12

ANL A. #data 2 2 12

ANL direct. A 2 2-3 12

ANL direct. #data 3 3-4 24

ORL A. Rn 1 1 12

ORL A. direct 2 2-3 12

ORL A.@Ri 1 2-3 12

ORL A. #data 2 2 12

ORL direct. A 2 2-3 12

ORL direct. #data 3 3-4 24

XRL A. Rn 1 1 12

XRL A. direct 2 2-3 12

XRL A.@Ri 1 2-3 12

XRL A. #data 2 2 12

XRL direct. A 2 2-3 12

XRL direct. #data 3 3-4 24

CLR A I 1 12

CPL A I 1 12

RLA I I 12

RLC A 1 1 12

RRA 1 1 12

RRCA I 1 12

SWAP A I 1 12

- 32 -


Table 3. Data transfer execution time.

Enhanced 8051 Core


MOV A.Rn 1 1 12

MOV A. direct 2 2-3 12

MOV A.@Ri 1 2-3 12

MOV A. #data 2 2 12

MOV Rn. A 1 1 12

MOV Rn. direct 2 3 24

MOV Rn. #data 2 2 12

MOV direct, A 2 2 12

MOV direct, Rn 2 3 24

MOV direct. direct 3 3 24

MOV direct. @Ri 2 4 24

MOV direct. #data 3 3 24

MOV@Ri,A 1 2 12

MOV @Ri. direct 2 3 24

MOV @Ri. #data 2 3 12

MOV DPTR. #addr24 4 * 4 24

MOVC A. @A+DPTR 1 2 24

MOVC A. @A+PC 1 2 24

MOVX A.@Ri 1 2 24

MOVX A. @DPTR 1 2 24

[email protected] 1 2 24

MOVX @DPTR, A 1 2 24

PUSH direct 2 4 24

POP direct 2 3 24

XCH A. Rn 1 1 12

XCH A, direct 2 2-3 12

XCH A,@Ri 1 2-3 12

XCHD A,@Ri 1 2-3 12

* The standard 8051 core provides the 3-byte instmction MOV DPTR,#addr16.

- 33 -


Table 4. Boolean variable manipulation execution time.

Enhanced 8051 Core


CLRC 1 1 12

CLR bit 2 2-3 12

SETB C 1 1 12

SETB bit 2 2-3 12

CPLC 1 1 12

CPL bit 2 2-3 12

ANL C. bit 2 2-3 24

ANL C. /bit 2 2-3 24

ORL C, bit 2 2-3 24

ORL C. /bit 2 2-3 24

MOV C. bit 2 2-3 12

MOV C, /bit 2 2-3 24

JC reI 2 2 24

JNC rei 2 2 24

JB bit. reI 3 3-4 24

JNB bit. reI 3 3-4 24

JBC bit, reI 3 3-4 24

- 34 -


Table 5. Program branching execution times.

Enhanced 8051 Core


ACALL page x 2 5 24

LCALL addr 16 3 6 24

GCALL addr24 4 7 not supported

RET 1 3-4 24

RETI 1 3-4 24

AJMP page x 2 2 24

LJMP addrl6 3 3 24

GJMP addr24 4 4 not supported

SJMP rei 2 2 24

JMP@A+DPTR I I 24

JZ rei 2 2 24

JNZ rei 2 2 24

CJNE A. direct. rei 3 3-4 24

CJNE A. #data. rei 3 3 24

CJNE Rn. #data. rei 3 3 24

CJNE @Ri. #data. reI 3 4-5 24

DJNZ Rn. reI 2 2 24

DJNZ direct. rei 3 3-4 24

NOP I 1 12

Notes on the instruction set and addressing modes:Rn : Register addressing (n = 0..7).@Ri : Register-indirect addressing (i = 0.. 1).direct : Direct addressing.#data : 8-bit constant included in instruction.#datal6 : 16-bit constant included in instruction.#data24 : 24-bit constant included in instruction.page x : Branching within I Kbyte (x = 0..3).addrl6 : Branching within 64 Kbytcs.addr24 : Branching within 16 Mbytes.rei : signed 8-bit offset byte for short jumps.bit : Direct addressed bit.

- 35 -


Appendix D: First IDaSS Design

Enhanced 8051 Core

The architecture described below is the first design of the enhanced 8051 core. This designis not suitable for synthesis with the ASA silicon compiler because of the followinglimitations:

• The external memory ready signal, implemented as IDaSS signal, cannot be converted;• The use of asynchronous read and write RAM is not supported by ASA;• In ASA the state machines cannot deal with the semaphore flag;• Several operators are too complex and use prohibited IDaSS functions.

The enhanced 8051 core is compatible to the standard 8051 core which satisfies the interfacespecifications for IDaSS library components. Furthelmore, the number of clock cycles neededto execute an instIuction has been restricted to a minimum. An 8-bit data input and outputbus runs through the design as needed for the I/O interface. The presence of these data busesprovides the possibility of modifying a data byte within one clock cycle. Therefore, theinternal RAM has to be accessed asynchronously when a read or write action is performed.

The instruction code bytes are sequentially read and during instruction execution the next opcode is fetched. This method is called prefetching and results in an architecture that uses forinstruction execution the same number of clock cycles as the number of instruction bytes.Exceptions are indirect register addressing, subroutine operations and the multiply and divideinstruction.

The complete architecture of the processor core is schematically represented in figure 1. Allthe blocks are controlled by four state machines. Each state machine is activated by a setsemaphore flag of specific registers. The semaphore flag is an extra register bit that isautomatically set each time a load action occurs and can be tested and reset by controlllers.

The four state machines are divided into the addressing modes. The advantages of four statemachines above one state machine are smaller states and design surveyability. Testing of theready signal also occurs in the state machines. The ready signal, generated by the externalmemories, is simulated by a pulse signal from the signal editor in IDaSS. The state machinesfunctionality is as follows:

• DIRECf (2 states): All the direct addressing operations are handled by this state machinewhich is linked with register AR.

• BOOLEAN (2 states): This state machine handles the bit-manipulation instructions andis activated by register BaaL.

• REGISTER (3 states): This state machine is linked with the RAMunit temporary registerTMP2 and completes the instructions that are associated with registers of the four registersbanks. The temporary register TMP2 is loaded with the indirect address. If the TMP2

- 36 -


------------

....-+_I~EQ

t---------,~w..t---------:.:,,... ADDRfSS8uS I1-- ----,,.. lACK

1-- .... SFRe'"

~-------r--SfRI"

1-+-------,--...,....-..... DATAIUS

I - - - - - - - - - - - - - - - ALUunit I

I II II I

IIII

DECODER I I DIRECT

REGISTER I I BOOLEAN

I SFR.dd, •

I .RAMumtL _

1----------I II II 8. 8_'" I

WhiR I--....."...--+----J~

I .. ~ ..wADDRSet

Figure 1: The architecture of the first enhanced 8051 core in IDaSS.

semaphore flag is not set, a second test is done on bit 3 of the instruction register JR. Inthis way the difference between register addressing and register indirect addressing modeis detected.

• DECODER (7 states): This is the main state machine which controls the total process ofinstruction fetching and execution depending on the instruction register IR contents.Furthennore the interrupt request, if present in the interrupt number register INo, arehandled by this state machine. The first state is used as start up state, so after anasynchronous reset the processor core starts with fetching the first op code. One stateserves as wait state to finish the multiplication and division that take eight clock cycles.

The architecture is constituted out of three units: A RAM unit to perform the internal RAMoperations; an ALU unit executes the arithmetic and logical operations; and the PC unit tocontrol the external addressing. All the units are interconnected by a switch. The switch isresponsible for correct data transpott between the units and the external world.

- 37 -


The core contains five special function registers which are placed near the operator that usesthe register. The ALU is surrounded by the Accumulator, the Program Status Word and theB register. The temporary register TMPI is used for storing immediate data and partial resultsduring the multiply and divide operation. The Stack Pointer and Data Pointer accompany theprogram counter unit.

- 38 -


Appendix E: IDaSS Document of the Enhanced 8051 Core

IDaSS VO.Oam document.

=~===========================================

'TopLevel\TopLevel\Core80S1' is a schematic,

Bidirectional connector (25 bits) with name 'Addrbus'Bidirectional connector ( 2 bits) with name 'Ctrlbus'Bidirectional connector ( a bits) with name 'DATibus'Bidirectional connector ( a bits) with name 'DATobus'Bidirectional connector ( 1 bit ) with name 'enable'Bidirectional connector ( 2 bits) with name 'lack'Bidirectional connector ( 3 bits) with name ' Ireq'Bidirectional connector ( 1 bit ) with name 'Ready'Bidirectional connector 00 bits) with name 'SFRaddr'Bidi rect iona 1 connector ( 8 bits) with name 'SFRi'Bidirectional connector ( a bits) with name 'SFRo'============================================='TopLevel\TopLevel\Core8051\ALU_SFR' is a schematic.

Bidirectional connector ( 8 bits) with name 'ALUout I'Bidirectional connector ( 8 bits) with name 'ALUout2'Bidirectional connector ( a bits) with name ' ALUPSW'Bidirectional connector ( a bits) with name 'Ao'Bidirectional connector ( a bits) with nam€ 'Bo'Bidirectional connector ( 1 bit ) with name 'CTRL'Bidirectional connector ( a bits) with name 'DirDat'Bidirectional connector 00 bits) with name 'IR'Bidirectional connector ( a bits) with name 'PSWo'Bidirectional connector 00 bits) with name 'SFR'============================================='TopLevel\TopLevel\CoreaOS1\ALU_SFR\A' is a register.

This register is 8 bits wide and is controlled by an unnamed control input,The default function is 'hold'.This register is loaded with value 0 following system reset.

The value loaded for the 'reset' command is O.

Control specification:----------------------v----------------------'Write register A,"%1 load. "New contents."----------------------~----------------------

'TopLevel\TopLevel\Core8051\ALU_SFR\AiMUX' is an operator.

This operator has 3 functions and is controlled by an unnamed control input.The default function is 'ALUoutl',

Control connector (10 bits) without a name

Control specification:----------------------v----------------------"Select register A input."%0100010000, "JBC bit,rel"%0111010000, "POP dir"%010100001x, "ORL dir,A & 8data"%010101001x, "ANL dir, A & 8data"%010110001x, "XRL dir,A & 8data"%0110010010, "MOV bit,C"%0110110010, "CPL bit"%0111000010, "CLR bi t"%0111010010, "SETB bit"%0100000101. "INC dir"%0100010101, "DEC dir"%0101110101, "MOV dir, *data"%1010000101, "MOV dir,dir"%0111010101. "WNZ dir, reI"%0111110101. "MOV dir, A"%011000011x, "MOV dir, @Ri"%0110001xxx Direct. "MOV dir,Rn"%0111000101, "XCH A, dir"%OlllOOOl1x, "XCH A,@Ri"%011101011x, "XCHD A,@Ri"%0111001xxx XCH. "XCH A,Rn"

- 39 -


______________________ A _

Enhanced 8051 Core

Output connectorInput connectorInput connectorInput connector

8 bits) with name 'A'8 bits) with name 'ALUoutl'8 bits) with name 'ALUout2'8 bits) with name 'Direct'

Text for function 'ALUoutl' of 'TopLevel\TopLevel\Core8051\ALU_SFR\AiMUX':----------------------v----------------------·ALU output. moves included.'A := "'LUoutl.______________________ A _

Text for function 'Direct' of 'TopLevel\TopLevel\Core8051\ALU_SFR\AiMUX':----------------------v----------------------'Direct addressing.·... := Direct.______________________ A _

Text for function 'XCH' of 'TopLevel\TopLevel\Core8051\ALU_SFR\AiMUX':----------------------v----------------------'XCH instruction.·A := "'LUout2.______________________ A _

'TopLevel\TopLevel\Core8051\ALU_SFR\AWop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is ·Direct·.


Control specification:----------------------v----------------------·Select register A control,%1011100000. ·MOVX A.@DPTR·%101110001x. ·MOVX A. @Ri·%1010000011. ·MOVC A.@A+PC·%1010010011. ·MOVC [email protected]'%0101110100. ·MOV A.Hdata·%0111100100. ·CLR ... •%0111100101. ·MOV A. dir·%011110011x. 'MOV A.@Ri·%0111101xxx. ·MOV A.Rn·%0100000011. ·RR A·%0100010011. ·RRC A·%0100100011. ·RL A·%0100110011. ·RLC A·%0100000100 .• INC A'%0100010100. ·DEC A'%01001001xx. "ADD·%01001 01xxx. •ADD·%010011 01xx. • ADDC·%010011lxxx. •ADOC·%01010001xx. ·ORL ... •%0101001xxx. ·ORL A·%01010101xx. • ANL A·%0101011xxx. ·ANL A·%01011001xx. 'XRL A'%0101101xxx. 'XRL A·%0110000100. 'DIV "'B·%1010000100. ·DIV"'B last cycle·%01100101xx. ·SUBB·%0110011xxx. ·SUBB·%0110100100. ·MUL AB·%1010100100. ·MUL AB last cycle·%0111000100, ·SWAP A·%0111010100. ·DA A·%0111110100. ·CPL A·%0111000101. ·XCH A. dir·%011100011x. 'XCH @Ri·%011101011x. ·XCHD @Ri·%0111001xxx Wrt. ·XCH .... Rn·_____________ • A _

OUtput connectorInput connectorInput connector

bitbitbit

with name 'AW'with name 'CTRL'with name 'DirAW'

Text for function 'Direct' of ·T,~pLevel\T,JpLevel\Core8051\ALU_SFR\AWop·:

----------------------v----------------------·Direct addressing.·AW := DirAW 1\ CTRL.

- 40 -


----------------------~----------------------

Text for function 'Wrt' of 'TopLevel\TopLevel\Core8051\ALU_SFR\AWop':----------------------v----------------------"Write register A."AW := 1 ones /\ CTRL.______________________ A _

'TopLevel \TopLevel\Core8051 \ALU_SFR\B' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with value 0 following system reset.


Control specification:----------------------v----------------------%1 load. "Write new value in register B."______________________ A _

'TopLevel\TopLevel\Core8051\ALU_SFR\BiMUX' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Direct'.


Control specification:----------------------v----------------------"Select register B input."%10l0xOOlOO M_D. "Multiplication or division."----------------------~----------------------

Enhanced 8051 Core

Input connectorOUtput connector

Input connector

8 bits) with name 'ALUout2'8 bits) with name 'B'8 bits) with name 'Direct'

Text for function 'Direct' of 'TopLevel\TopLevel\Core8051\ALU_SFR\BiMUX':----------------------v----------------------"Direct adressing."B := Oirect.______________________ A _

Text for function 'M_D' of 'TopLevel\TopLevel\CoreB051\ALU_SFR\BiMUX':----------------------v----------------------"Multiplication or division."B := ALUout2.----------------------~----------------------

'TopLevel\TopLevel\CoreB051\ALU_SFR\BWop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Normal',


Control specification:----------------------v----------------------"Activate register B access for multiplication or division."%1010xOOlOO M_O. "MUL or OIV"______________________ A _

OUtput connector ( 1 bit) with name 'BW'Input connector ( 1 bit ) with name 'OirBW'

Text for function 'M 0' of 'TopLevel\TopLevel\Core8051\ALU_SFR\BWop':----------------------v----------------------"Multiplication or division,"BW := 1 ones. "Write high byte result register B."

A---------------------- ----------------------

Text for function 'Normal' vf 'TopLevel\TcpLevel \Core8051 \ALU_SFR\BWop' :----------------------v-----~----------------

"Wait for ALU active signal."BW := OirBW.----------------------~----------------------

'TopLevel\TopLevel\Core8051\ALU_SFR\OirAop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Normal'.

- 41 -



Control specification:----------------------v----------------------·Direct addressing to register A.·(0 •• 7)%11100000 A.______________________ A _

OUtput connector ( 1 bit) with name 'AW'Input connector (10 bits) with name 'SFR'

Text for function 'A' of 'TopLevel\TopLevel\Core80S1\ALU_SFR\DirAop':----------------------v----------------------·Register A access.·AW : = SFR at: 8.______________________ A _

Text for function 'Normal' of 'TopLevel\TopLevel\Core8051\ALU_SFR\DirAop':----------------------v-----·----------------·No direct addressing to register A.·AW : = 1 zeroes.______________________ A _

'TopLevel\TopLevel\Core80Sl\ALU_SFR\DirBop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Normal',


Control specification:----------------------v----------------------·Direct addressing to register B.·(0 •• 7)%11110000 B.______________________ A _

OUtput connector ( 1 bit) with name 'BW'Input connector (10 bits) with name 'SFR'

Text for function 'B' of 'TopLevel\TopLevel\Core80S1\ALU_SFR\DirBop':----------------------v----------------------·Register B access.·BW := SFR at: 8.______________________ A _

Text for function 'Normal' of 'TopLevel\TopLevel\Core8051\ALU_SFR\DirBop':----------------------v----------------------·No direct addressing to register Bo·BW := 1 zeroes.______________________ A _

'TopLevel\TopLevel\Core80S1\ALU_SFR\DirPSWop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Nor",al'.


Control specification:----------------------v----------------------·Direct addressing to register PSW.·(0 .. 7)%11010000 PSW.______________________ A _

Output connector ( 1 bit) with name 'PSWW'Input connector (10 bits) with name 'SFR'

Text for function 'Normal' of 'TopLevel\TopLevel\Core80S1\ALU_SFR\DirPSWop':----------------------v----------------------·No direct addressing to register PSW.·PSWW := 1 zeroes.______________________ A _

Text for function 'PSW' of 'TopLevel\TopLevel\Core80S1\ALU_SFR\DirPSWop':----------------------v----------------------·Register PSWaccess.·PSWW := SFR at: 8.______________________ A _

'TopLevel\TopLevel\Core80S1\A~U_SFR\P' is a register.

- 42-

Enhanced 8051 Core


This register is 1 bit wide.The default function is 'load'.This register is loaded with value 0 following system reset.


'TopLevel\TopLevel \Core8051 \ALU_SFR\Pop' is an operator.

This operator has 1 function.The default function is 'Parity'.

Enhanced 8051 Core


8 bits) with name 'A'1 bit) with name 'P'

Text for function 'Parity' of 'TopLevel\TopLevel\Core8051\ALU_SFR\Pop':----------------------v----------------------"Generate parity bit."P := (A at: 0) >< (A at: 1) ><

(A at: 2) >< (A at: ]) ><(A at: 4) >< (A at: 5) ><(A at: 6) >< (A at: 7).

______________________ A _

'TopLevel\TopLevel\Core8051\ALU_SFR\PSW' is a register.

This register is 7 bits wide.The default function is 'load'.This register is loaded with value 0 following system reset,


'TopLevel\TopLevel \Core8051 \ALU_SFR\PSWiMUX' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'ALU'.

Control connector ( bit ) without a name

Control specification:----------------------v----------------------"Select register PSW input."%1 Direct. "Direct addressing mode"

Input connectorInput connector

OUtput connector

8 bits) with name 'ALU'8 bits} with name 'Dire~t'

8 bits) with name 'PSW'

Text for function 'ALU' of 'TopLevel\TopLevel\Core8051\ALU_SFR\PSWiMUX':----------------------v----------------------"ALU input."PSW : = ALU.----------------------~----------------------

Text for function 'Direct' of 'TopLevel\TopLevel\Core8051\ALU_SFR\PSWiMUX':----------------------v----------------------"Direct addressing."PSW := Direct.______________________ A _

'TopLevel\TopLevel\Core8051\ALU_SFR\PSWop' is an operator.

This operator has I function.The default function is 'PSWmod'.

Input connector 7 bits) with name ~ in'OUtput connector 7 bits) with name 'out'

Input connector 1 bit ) with name 'P'Input connector 8 bits) with name 'pswi'

OUtput connector 8 bits) with name 'PSWo'Input connector I bit ) with name 'PSWW'

Text for function 'PSWmod' of 'TopLevel\TopLevel\Core8051\ALU_SFR\PSWop':-----------~----------v----------------------

"Register PSW modify."out := PSWW if0: in "Old value."

ifl: (pswi from: I tv: 7). "New value."PSWo := in, P._----- --- ~ -- '" - - - - - - - - -- - - - - - - - - - - --

==================~=========~================

'TopLevel\TopLevel \Core8051 \ALU_SFR\PSWWop' is an operator,

- 43 -


This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Direct'.


Control specification:----------------------v----------------------'Select register PSW control.'%0110100000, 'ORL C, /bit'%0110110000, 'ANL C, /bit'%0101110010, 'ORL C,bit'%0110000010, 'ANL C,bit'%0110100010, 'MOV C,bit'%0100010011. 'RRC A'%0100110011, 'RLC A'%011 0 11 00 11. 'CPL C'%0111000011. 'CLR C'%0111010011, 'SETB C'%0100 1001xx, 'ADD'%0100101xxx, 'ADD'%01001101xx, 'ADDe'%01 OOlllxxx, 'ADDe'%01100101xx, 'SUBB'%0110011xxx, 'SUBB'%01101101xx, 'CJNE'%0110111xxx, 'CJNE'%1010x00100, 'DIV AS and MUL AB last cycle'%0111010100 Wrt. 'DA A'______________________ A _

Enhanced 8051 Core


Output connector

bitbitbi t

with name 'CTRL'with name 'DirPS~~'

WIth name 'PSWW'

Text for function 'Direct' of 'TopLevel \TopLevel\Core8051 \ALU_SFR\PSWWop' :----------------------v----------------------'No register PSW operation.'PSWW := DirPSWW /\ CTRL.______________________ A _

Text for function 'Wrt' of 'TopLevel\TqoLevel\Core8051\ALU_SFR\PSWWop':----------------------v----------------------'Write register PSW.'PSWW := 1 ones /\ CTRL,______________________ A _

'TopLevel\TopLevel\Core8051\ALUunit' is a schematic.

Bidirectional connector 8 bits) with name 'A'Bidirectional connector 8 bits) with name 'AR'Bidirectional connector 8 bits) with name 'B'Bidirectional connector 1 bit ) with name 'CTRL'Bidirectional connector 1 bit ) with name 'DIRDV'Bidirectional connector 8 bits) with name I Direct'Bidirectional connector ( 8 bits) with name '1M'Bidirectional connector (10 bits) with name ' IR'Bidirectional connecte,r ( 1 bit ) with name 'Jtst'Bidirectional connector ( 8 bits) with name 'outl'Bidirectional connector ( 8 bits) with name 'out2'Bidirectional connector ( 8 bi ts) with name 'PSWi'Bidirectional connector ( 8 bits) with narr:e 'PSWo'Bidirectional connector ( 8 bits) with name 'RAMDATi'Bidirectional connector ( 2 bits) with name 'RAMDV'==============~==============================

'TopLevel\TopLevel\Core8051\ALUunit\ALUin1MUX' is an operator.

This operator has 3 functions and is controlled by an unnamed control input.The default function is 'A' .


Control specification:----------------------v----------------------'Select ALU input and enable.'%0100010000, 'JBC bit. rel'%0100100000, 'JB bit, reI'%0100110000, 'JNB bit, reI'%0110100000, 'ORL C, /bit'%0110110000, 'ANL C, /bit'%0101110010, 'ORL C, bit'%0110000010, "ANL C,bit'%0110010010, 'MOV bit, C'

- 44-


%0110100010, "MOV C, bit"%0110110010, "CPL bit"%0111000010, "CLR bit"%0111010010, "SETB bit"%0101000011, "ORL dir,Hdata"%0101010011, "ANL dir, Hdata"%0101100011, "XRL dir,Hdata"%0100000101. "INC dir"%0100010101. "DEC dir"%0101110101. "MOV dir, Hdata"%0111010101 DIR. "DJNZ dir,re1"%010000011x, "INC QRi"%010001011x, "DEC @Ri"%010111011x, "MOV @Ri,Hdata"%011011011x, "CJNE @Ri, Hdata, reI"%0100001xxx, "INC Rn"%0100011xxx, "DEC Rn"%0101111xxx, "MOV Rn, Hdata"%OllOl11xxx, "CJNE Rn, Hdata, reI"%0111011xxx RAM. "DJNZ Rn,rel"---------------------- ~ ----------------------

Input connector 8 bits) with name 'A'Input connector 8 bits) with name 'Di rect'

Output connector 8 bits) with name ' in 1 'Input connector 8 bits) with name 'RAM'

Text for function 'A' of 'TopLevel\TopLevel\CoreS051\ALUunit\ALUin1MUX':----------------------v----------------------in1 := A.______________________ A _

Text for function 'DIR' of 'TopLevel\Te,pL"vel\Core8051\ALUunit\ALUin1MUX':----------------------v----------------------in1 := Direct.______________________ A _

Text for function 'RAM' of 'TopLevel \TopLevel\Core8051 \ALUunit\ALUin1MUX' :----------------------v----------------------inl := RAM.______________________ A _

'TopLeve1\TopLevel\Core8051\ALUunit\ALUin2MUX' is an operator.

This operator has 4 functions and is controlled by an unnamed control input.The default function is 'RAM'.


Control specification:----------------------v----------------------"Select ALU input and enable,"%0110x00100, "DIV AB and MUL AB"%1010x00100 B. "DIV AS and MUL AB last cycle"%1011100000, "MOVX A,@DPTR last cycle"%1011010000, "POP dir from €xtern31 stack"U01110001x, "MOVX A,@Ri last cycle"%0100100100, "ADD A, Hdata"%0100110100, "ADDC A, Hdata"%0101000100, "ORL A, Hd3ta"%0101010100, "ANL A, Hd3ta"%0101100100, "XRL A, Hdata"%0101110100, "MOV A,Hdata"%0110010100, "SUBB A,Hdata"%0110110100, "CJNE A,fidata,rel"%1010000011, "MOVC A,@A+PC"%1010010011, "MOVC A,@A+DPTR"%010111011x, "MOV @Ri,Hdata'%011011011x, "CJNE @Ri, Hdata, reI"%0101111xxx, "MOV Rn, Hdata"%0110111xxx, "CJNE Rn,Hdata,rel"%0101000011, "ORL dir.Hdata'%0101010011, "ANL dir, Hdata"%010110001 L "XRL dir, Hdata"%0101110101 1M. "MOV dir,Hdata"%1011000000, "PUSH dir"%0101000010, "ORL dir,A"%0101010010, "ANL dir, A"%0101100010, "XRL dir,A"%0100100101, "ADD A,dir"%0100110101, "ADDC A,dir,"%0101000101, "ORL A,dir"

- 45 -

Enhanced 8051 Core


%0101010101, "ANL A, dire%0101100101, "XRL A, dire%0110010101, "SUBB A, dire%0110110101, "CJNE A, dir, reI"%0111000101, "XCH A, dire%0111100101, "MOV A, dire%101010011x, "MOV @Ri,dir"%1010101xxx DIR. "MOV Rn,dir (second cycle)"______________________ A _

Input connector 8 bits) with name 'B'Input connector 8 bits) with name 'Direct'Input connector 8 bits) with name ' 1M'

OUtput connector 8 bits) with name 'in2'Input connector 8 bits) with name 'RAM'

Text for function 'B' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUin2MUX':----------------------v----------------------in2 := B.______________________ A _

Text for function 'DIR' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUin2MUX':----------------------v----------------------in2 :.:= Direct.

Text for function' 1M' of 'TcpLevel\T0pLevel\Core80S1\ALUunit\ALUin~MUX':

- - - - - - - - - - - - - - - - - - - - - -v- - - - - - - - - - - - - - - - - - - - --in2 := 1M.______________________ A _

Text for function 'RAM' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUin2MUX':----------------------v----------------------

in2 := RAM.

'TopLevel\TopLevel\Core80SI\ALUunit\ALUs' is a schematic.

Bidirectional connector ( 8 bits) with name ' inl'Bidirectional connector ( 8 bi ts) with narne ' in2'Bidirectional connector (10 bits) with name ' IR'Bidirectional connector ( 1 bit ) with naITlC 'Jtst'Bidirectional connector ( 8 bits) with naITle 'out1'Bidirectional connector ( 8 bits) with name 'out2'Bidirectional connector ( 8 bits) with name 'PSWi'Bidirectional connector ( 8 bits) with name 'PSWo'=====================================~=======

'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU1' is an operator.

This operator has 8 functions and is controlled by an unnamed control input.The default function is 'DEC'.


Control specification:----------------------v----------------------"Select ALU function."%0101100000 JZ. "JZ reI"%0101110000 JNZ. "JNZ reI"%0110000000 SJMP. "SJMP reI"%OlOOOOOlxx,%0100001xxx INC. "INC"%01001001xx,%0100101xxx ADD. "ADD"%01001101xx,%0100111xxx ADDC. "ADOC"%01100101xx,%0110011xxx SUBB. "SUBB"---------------------- A ----------------------

Input connector 8 bits) with name ' in1'Input connector 8 bits) with name 'in2 '

Output connector 1 bit ) with name 'Jtst'Output connector 8 bits) with name 'out1'

Input connector 8 bits) with name 'pswi'OUtput connector 8 bits) with name 'PSWo'

Text for function 'ADD' of 'TopLeve1\TopLevel\Core8051\ALUunit\ALUs\ALU1':----------------------v----------------------"ADDA,in2."Sum .- (1 zeroes, in1, 1 zeroes) • (1 zeroes, in2, 1 zeroes).

outl .- <_Sum from: 1 to: 8).PSWo .- (_Sum at: 9), «(inl at: 4) >< (in2 at: 4) >< (_Sum at: 5»,

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Enhanced 8051 Core


(PSWi from: 3 to: 5), «(in1 at: 7) <> (in2 at: 7» /\ «in1 at: 7) >< (_Sum at: 8»),(PSWi from: 0 to: 1).

______________________ A _

Text for function 'ADDe' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU1':----------------------v----------------------• ADDC A, in2."_Sum .- (l zeroes, in!, (PSWi at: 7» + (l zeroes, in2, (PSWi at: 7»).out1 .- LSum from: 1 to: 8).PSWo .- (_sum at: 9), «in1 at: 4) >< (in2 at: 4) >< (_Sum at: 5»),

(PSWi from: 3 to: 5), «(in1 at; 7) <> (in2 at: 7» /\ «in1 at: 7) >< LSum at; 8))),(PSWi from: 0 to: 1).______________________ A _

Text for function 'DEC' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU1':----------------------v----------------------·DEC in!."_Sum := (1 zeroes, inl, 1 ones) + (1 zeroes, 7 ones, 1 zeroes, 1 ones).out1 := _Sum from: 1 to: 8.·Activate jump for DJNZ.·Jtst := «_Sum at: 1) \/ (_Sum at: 2) \/ (_Sum at: 3) \/ (_Sum at: 4) \/

LSumat: 5) \/ LSumat: 6) \/ LSumat: 7) \/ (_Sum at: 8»),______________________ A _

Text for function' INC' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU1':----------------------v----------------------• INC in!.·_Sum := (1 zeroes, inl, 1 zeroes) + (8 zeroes, lones, 1 zeroes),outl ;= _Sum from; 1 to; 8.______________________ A _

Text for function 'JNZ' of 'TopLevel\TopLevel \Core8051 \ALUunit\ALUs\ALU1, :----------------------v----------------------·JNZ·Jtst ;= (inl at: 0) \/ (inl at: 1) \/ (inl at: 2) \/ (inl at: 3) \/

(inl at: 4) \/ (in1 at: 5) \/ (in1 at: 6) \/ (inl at; 7).

Text for function 'JZ' of 'ToPLevel\TopLevel\Core8051\ALUunit\ALUs\ALUl':----------------------v----------------------.,J? •

Jtst ;= «inl at; 0) \/ (inl at: 1) \/ (inl at; 2) \/ (inl at; 3) \/(inl at: 4) \/ (inl at; 5) \/ (inl at; 6) \/ (in1 at; 7) not.______________________ A _

Text for function 'SJMP' of 'TopLevel\T0pLevel\Core8051\ALUunit\ALUs\ALU1':----------------------v----------------------• SJMp·Jtst ;= 1 ones.______________________ A _

Text for function 'SUBB' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU1':----------------------v----------------------·SUBB A,in2."_Sum ._ (1 zeroes, in1, (PSWi at: 7) not) + (l zeroes, in2 not, (PSWi at: 7) not),out1 .- (_Sum from; 1 to: 8).PSWo ._ (_Sum at; 9) not, «(inl at: 4) >< (in2 at: 4) >< (_Sum at: 5)),

(PSWi from: 3 to: 5). «(in1 at: 7) <> (in2 at: 7) not) /\ «in1 at: 7) >< (_Sum at: 8))),(PSWi from: 0 to; 1).______________________ A _

'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU2' is an operator,

This operator has 7 functions and is controlled by an unna~ed control input.The default function is 'MOV' ,


Control specification:----------------------v----------------------·select ALU function.·%0110000100 DIV. ·DIV AB·%1010000100 DIV. ·DIV AS last cycle·%0110100100 MUL. ·MUL AB·%1010100100 MUL. ·MUL AB last cycle·%0100010011 RRC. ·RRC A·%0100110011 RLC. ·RLC A·%0100000011 RR. ·RR A"%0100100011 RL. ·RL A·

-~--------------------~------~---------------Input connector (8 bits) with name 'in1'

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Section of Digital Informnlion Systems Enhanced 8051 Core

Input. connect.or 8 bit.s) wit.h name 'in2'Out. put. connect.or 8 bit.s) with name 'out l'OUtput. connector 8 bit.s) wit.h name 'out.2'

Input. connector 8 bit.s) with name 'PSWi'OUtput. connector 8 bit.s} with name 'PSWo'

Input. connect.or 8 bit.s} with name 'TMP'

Text for function 'DIV' of 'TopLevel \TopLevel \Core8051 \ALUunit. \ALUs\ALU2 , :----------------------v----------------------"DIV AB"_Sum := (TMP, (inl at.: 7),1 ones) + (l zeroes, in2 not., 1 ones).out.1 := (in1 from: 0 t.o: 6), (_Sum at: 9)."out.2 in the last. cycle t.o regist.er B else to TMP"out.2 := <-Sum at: 9) ifl: LSum from: I to: 8)

if0: (TMP from: 0 to: 6), (in1 at: 7)."Update PSW only in the last cycle"PSWo := 1 zeroes, (PSWi from: 3 to: 6), «in2 at: 0) \/ (in2 at: 1) \/ (in2 at: 2) \/

(in2 at: 3) \/ (in2 at: 4) \/ (in2 at: 5) \/ (in2 at: 6) \/ (in2 at: 7» not,(pswi from: 0 to: 1).

______________________ A _

Text for function 'MOV' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU2':----------------------v----------------------"MOVoperation."outl := in2.______________________ A _

Text for function 'MUL' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU2':----------------------v----------------------"HUL AB"_Test := (inl at: 0) if0: 8 zeroes

if 1; i n2 ._Sum := (1 zeroes, TMP. 1 ze~oes) + (1 zeroes, _Test, 1 zeroes).out.l := (_Sum at: 1), (inl from: 1 t.o: 7)."out2 to register B in the last cycle else to TMP"outl := (_Sum from: 2 to: 9)."Update PSW only in the last cycle."PSWo := 1 zeroes, (pswi from: 3 to; 6), ((_Sum at: 2) \/ (_Sum at: 3) \/ LSum at: 4) \/

(_Sum at: 5) \/ (_Sum at: 6) \/ (_Su," at: 7) \/ (_Sum at: 8) \/ (_Sum at: 9»,(PSWi from: 0 to: 1).

Text for funct ion 'RL' of 'Tc,pLeve 1 \ TopLeve I \Cc,re8051 \ALUun i t \hLUs \ALU2' :----------------------v----------------------"RL A"outl := (inl from: 0 to: 6), (inl at: 7).----------------------~----------------------

Text for funct ion 'RLC' of 'Te,pLevel \ T0pL"ve 1 \Core8051 \ALUun i t \ALUs \ALU2' :----------------------v----------------------"RLC A"out 1 : = (inl from: 0 to: 6), (FSWi at: 7).PSWo := (inl at: 7), (FSWi from: 0 to: 6).

Text. for function 'RR' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU2':----------------------v----------------------"RR A"outl := (inl at.: 0), (inl from: 1 to: 7).

----------------------~----------------------

Text for funct.ion 'RRC' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU2':----------------------v----------------------"RRC A"outl := (PSwi at: 7), (inl from: 1 to: 7).PSWo := linl at: 0). (PSWi from: 0 to: 6).

'TopLevel\TopLevel\Core805l\ALUunit\ALUs\ALU3' is an operator.

This operat.or has 9 functions and is c0ntr,~l1ed by an unnamed control input.The default. function is 'XCH'.

Control connectOr (10 bit.s) without a name

Control specification:----------------------v----------------------"Select ALU function."%0111010100 DA. "DA A"%Ol0100001x, "ORL dire%01010001xx, "ORL A"

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%0101001xxx ORL. "ORL A,Rn"%010101001x, "ANL dir"%0101010Ixx, "ANL A"%0101011xxx ANL. "ANL A,Rn"%010110001x, "XRL dir"%0101100Ixx, "XRL A"%0101101xxx XRL. "XRL A,Rn"%0111000100 SWAP. "SWAP A"%0111100100 CLR. "CLR A"%0111110100 CPL. "CPL A"%011101011x XCHD. "XCHD A,@Ri"______________________ A _

Input connector 8 bits) with name ' inl'Input connector 8 bits) with name ' in2'

Output connector 8 bits) with name 'outl 'OUtput connector 8 bits) with name 'out2'

Input connector 8 bits) with name 'PSWi'OUtput connector 8 bits) with name 'PSWo'

Text for function 'ANL' of 'TopLevel\TOpLevel\Core8051\ALUunit\ALUs\ALU3' :----------------------v----------------------"Logical AND operation."outl := inl /\ in2.----------------------~----------------------

Text for function 'CLR' of 'TopLevel\TopLevel\Core8051\ALUunit \ALUs\ALU3 , :----------------------v----------------------"CLR A."outl := 8 zeroes.----------------------~----------------------

Text for function 'CPL' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU3' :----------------------v----------------------"CPL A."outl := inl not.

Text for funct ion 'DA' of 'TopLevel \TopLeve I \Core8051 \ALUunit \ALUs \ALU3' :----------------------v----------------------

(PSWi trom: 0 to: 6).

_Test2b .- _Test2a \/Add2 .- (inl from: 4

_High := _Test2b ifl:irO:

outl := _High, _Low.PSWo := (_Test2a \/ (PSWi at: 7)),

"DA A"_Testla .- (inl at: 3) if 0: 1 zer,:;>es

in: ((inl at: 1) \/ (inIat: 2)).Testlb .- _Testla \/ (PSWi at: 6).

_Addl := (inl from: 0 to: 3) + (1 zeroes, ~ ones, I zeroes).Low:= Testlb ifl: Addl

if0: (inl froOm: (l t,:;>: 3)._Test2a .- (inl at: 7) irO: 1 ~er·~es

ifl: (inl at: 5) \/ (inlat: 6)).(PS;./ i at: 7) \ / Tes t 1a.to: 7) + (1 zeroes, 2 ones, _Testla).

Add2(inl fr·~m: 4 to: 7).

______________________ A _

Text for function 'ORL' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU3':

----------------------v----------------------"Logic OR operation."outl := inl \/ in2.______________________ A _

Text for function 'SWAP' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU3':

----------------------v----------------------"SWAP A."outl := (inl from: 0 to: 3), (inl from: 4 to: 7).______________________ A _

Text for function 'XCH' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU3':----------------------v----------------------"XCH operation."outl := inl.out2 : = in2.______________________ A _

Text for function 'XCHD' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU3':----------------------v----------------------"XCHD A,@Ri."outl := (in2 from: 4 to: 7), (inl from: 0 to: 3).out2 := (inl from: 4 to: 7), (in2 from: 0 to: 3).______________________ A _

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Text for function 'XRL' of 'TcpLevel\TorLevel\Core8051\ALUunit \ALUs\ALU3 , :----------------------v-----------------------Exclusive OR operation.-outl := inl >< in2,______________________ A _

'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU4' is an operator.

This operator has 1 function,The default function is 'CJNE'.

Input connector 8 bits) with name ' inl'Input connector 8 bits) with name 'in2'

OUtput connector 1 bit ) with name 'Jtst'Input connector 8 bits) with name 'pswi'

OUtput connector 8 bits) with name 'PSWo'

Text for function 'CJNE' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALU4' :----------------------v----------------------'CJNE inl. in2. "Jtst := «(inl at: 0) >< <in2 at: 0») \/ «inl at: 1) >< <in2 at: 1» \/

«inl at: 2) >< (in2 at: 2» \/ «in1 at: 3) >< (in2 at: 3» \/«inl at: 4) >< (in2 at: 4» \/ (in1 at: 5) >< (in2 at: 5» \/((in1 at: 6) >< (in2at: 6» \/ ((ir,lat: 7) >< (in2at: 7»).

'Carry is set if in1<in2 else cleared."PSWo := (in1<in2), (PSWi from: 0 to: 6).______________________ A _

'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALUJtstMUX' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'ALUl',


Control specification:----------------------v-------------·--------'Select ALU output."%01101101xx, "JNZ reI'%0110111xxx ALU4. "CJNE"______________________ A _

Enhanced 8051 Core


Output connector

bitbitbit

with name 'ALU1'with name 'ALU4'with narne 'Jest'

Text for function 'ALUl' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALUJtstMUX':----------------------v----------------------'ALU1 operation.'Jtst : = ALUI.______________________ A _

Text for function 'ALU4' of 'TopLevel\TopLevel\Core805l\ALUunit\ALUs\ALUJtstMUX':----------------------v----------------------'ALU3 operation.'Jtst := ALU4.______________________ A _

'TopLevel\TopLevel\CoreS051\ALUunit\ALUs\ALUoutlMUX' is an operator.

This operator has 3 functions and is controlled by an unnamed control input.The default function is 'ALU2'.


Control specification:----------------------v----------------------'Select ALU output."%01000001xx,%0100001xxx, • INC'%01000101xx,%0100011xxx, "DEC"%0111010101,%01l1011xxx, 'DJNZ'%01001001xx,%010010 lxxx, • ADD'%01001101xx,%0100111xxx, "ADDC'%01100101xx,%0110011xxx ALUI. "SUBB"%0111010100, 'DA A'%010100001x, "ORL dir'

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%01010001xx, "ORL A"%0101001xxx, "ORL A,Rn"%010101001x, "ANL dir"%01010101xx, "ANL A"%0101011xxx, "ANL A, Rn"%010110001x, "XRL dir"%01011001xx, "XRL A'%0101101xxx, "XRL A,Rn"%0111000100, 'SWAP A'%0111100100, "CLR A'%0111110100, "CPL A'%0111000101, "XCH A, dir'%011100011x, "XCH A,@Ri'%0111001xxx, "XCH A,Rn'%011101011x ALU3. 'XCHD A,@Ri"______________________ A ______________________

Input connector 8 bits) with name ' ALUl'Input connector 8 bits) with name ' ALU2'Input connector 8 bits) with nam-e ' ALU3'

Output connector 8 bits) with name 'out I'

Text for function 'ALUl' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALUoutlMUX':- - - - - - - - - - - - - - - - - - - - - -v- - - - - - - - - - - - - - - - - - - - --"ALUloperation."out 1 : = ALUl.______________________ A _

Text for funct ion 'ALU2' 0 f 'TopLeve 1\ Tc,pLevel \Core8051 \AL'Jun i t \ALUs \ALUout IMUX' :----------------------v----------------------"ALU2 operation."ou t 1 : = ALU2.______________________ A _

Text for function 'ALU3' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUS\ALUoutlMUX':----------------------v----------------------"ALU3 operation."outl := ALU3.______________________ A _

'TopLevel \TopLevel \Core8051 \ALUunit \ALUs\ALU,jut2MUX' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'ALU)'.


Control specification:----------------------v----------------------"Select ALU output.'%1010000100, "DIV AB last cycle'%1010100100 ALU2. "MUL AB last cycle'______________________ A _

Enhanced 8051 Core


Output connector

8 bits) with name 'ALU2'8 bits) with name 'ALU)'8 bits) with name 'out2'

Text for function 'ALU2' of 'TopL-=v",l\TopLevel\Core8051\ALUunit\ALUs\ALUout2MUX':----------------------v----------------------"ALU2 operation."out2 := ALU2.______________________ A _

Text for function 'ALU3' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALUout2MUX':----------------------v----------------------"ALU3 operation."out2 : = ALU3.----------------------~----------------------

'TopLevel\TopLevel \Core8051 \ALUunit\ALUs\ALUPSWoMUX' is an operator.

This operator has 4 functions and is controlled by an unnamed control input.The default function is 'ALU1'.


Control specification:----------------------v----------------------"Select ALU output."UOI0000I00, "DIV AB last cycle"%1010100100 ALU2. "MUL AB last cycle"%0111010100 ALU3. "DA A"

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%01101101xx,%0110111xxx ALU4."CJNE"----------------------~----------------------

Enhanced 8051 Core

Input connectorInput connectorInput connectorInput connector

OUtput connector

a bits) with name 'ALU1'a bits) with name 'ALU2'a bits) with name 'ALU3'a bits) with name 'ALU4'8 bits) with name 'PSWo'

Text for function 'ALU1' of 'TopLevel\TopLevel\Corea051\ALUunit\ALUs\ALUPSWoMUX':----------------------v----------------------"ALU1 operation."PSWo := ALU1.______________________ A _

Text for function 'ALU2' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALUPSWoMUX':----------------------v----------------------"ALU2 operation."PSWo : = ALU2.______________________ A _

Text for function 'ALU3' of 'TopLevel\TopLevel\Core8051\ALUunit\ALUs\ALUPSWoMUX':----------------------v----------------------"ALU3 operation."PSWo : = ALU3.______________________ A _

Text for function 'ALU4' of 'TopLevel\TOpLevel\Corea051\ALUunit\ALUs\ALUPSWoMUX':----------------------v----------------------"ALU4 operation."PSWo := ALU4.______________________ A _

'TopLevel\TopLevel\Corea051\ALUunit\ALUs\CNTR' is a register.

This register is 3 bits wide.The default function is 'hold'.This register is loaded with value 0 following system reset.

The value loaded for the 'reset' com~and is O.

'TopLevel\TopLevel\Core8051\ALUunit\ALUs\TMP' is a register.

This register is 8 bits wide.The default function is 'hold'.This register is loaded with value 0 following system reset.


'TopLevel\TopLevel\Core8051\ALUunit\BOOL' is an operator.

This operator has 12 functions and is controlled by an unnamed control input.The default function is 'JB',

Control connector (10 bits) with0ut a name

Control specification:----------------------v----------------------"Select boolean operation."%0100010000 JB.%0100100000 JB.%0100110000 JNB.%0101000000 JC.%0101010000 JNC.%01101000000RLnot.%0110110000 ANLnot.%0101110010 ORL.%0110000010 ANL.%0110010010 MOV.%0110100010 MOV.%OllOllOOlx CPL.%01l100001x CLR.%011101001x SETB.----------------------~----------------------

Input connector 1 bit ) with name 'Bi t i'OUtput connector 1 bit ) with name 'Bito'Output connector 1 bit ) with n21m~~ 'Jtst'

Input connector 8 bits) with nan,€ 'pswi'OUtput connect.or 8 bits) with name 'PSW0'

Text for function 'ANL' of 'TopLevel\TopLevel\Core80S1\ALUunit\BOOL':

- 52 -


----------------------v----------------------·ANL C,bit."PSWo :~ «pswi at: 7) /\ BitU, (PSWi from: 0 to: 6).----------------------~----------------------

Text for function 'ANLnot' of 'TopLevel\T,:>pLevel\Core8051\ALUunit\BOOL':----------------------v----------------------"ANL C, /bit."PSWo :~ «PSWi at: 7) /\ Biti not), (PSWi from: 0 to: 6).______________________ A _

Text for function 'CLR' of 'TopLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------"CLR bit or C.·PSWo :~ 1 zeroes, (pswi from: 0 to: 6).Bito :~ 1 zeroes.______________________ A _

Text for function 'CPL' of 'TopLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------"CPL bit or C."PSWo := (pswi at: 7) not, (PSWi from: 0 to: 6).Bito := Biti not.

Text for funct ion 'JB' 0 f 'T0pLeve 1 \ T,:,pL",'"", 1 \Cul'e8051 \ALUun i t \BOOL' :----------------------v----------------------·JB or JBC."Jtst : = Bit i.Bito := 1 zeroes.

Text for function 'JC' of 'T0pLevel\TopLevel\CoreB051\ALUunit\BOOL':----------------------v----------------------·JC .•Jtst := psWi at: 7.______________________ A _

Text for function 'JNB' of 'TopLevel\T,:>pLevel\Core8051\ALUunit\BOOL':----------------------v----------------------"JNB. "Jtst :~ Biti not.______________________ A _

Text for function 'JNC' of 'TopLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------·JNC. "Jtst :~ (pswi at: 7) not.______________________ A _

Text for function 'MOV' of 'TopLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------·MOV bit,C or MOV C,bit."PSWo := Biti. (pswi from: 0 to: 6).Bito :~ PSWi at: 7.

Text for function 'ORL' of 'c,:>pLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------·ORL C,bit."PSWo :~ «PSWi at: 7) \/ Biti), (PSWi fr·:>m: 0 to: 6).______________________ A _

Text for function 'ORLnot' of 'TopLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------"ORL C, fbi t , "PSWo := «PSWi at: 7) \/ Biti not), (PSWi from: 0 to: 6).______________________ A _

Text for function 'SETB' of 'TopLevel\TopLevel\Core8051\ALUunit\BOOL':----------------------v----------------------·SETB bit or C."PSWo := lones, (pswi from: 0 to: 6).Bito := 1 ones.______________________ A _

'TopLevel\TopLevel\Core8051\ALUunit\BYTEop' is an operator.

This operator has 8 functions and is controlled by an unnamed control input.The default function is 'UNK'.

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Enhanced 8051 Core


Control connector ( 8 bits) without a name

Control specification:----------------------v----------------------"Select bit operator."(O •• 2)$0 BitO.$1 Bitl.$2 Bit2.$3 Bit3.$4 Bit4.$5 Bit5.$6 Bit6.$7 Bit7.______________________ A _

Input connector 1 bit ) with name ' Bi t i'OUtput connector 1 bit ) with name 'Bito'

Input connector 8 bits) with name 'inl'OUtput connector 8 bits) with name 'outl'

Text for function 'BitO' of 'TopLevel\TopLevel\Core805l\ALUunit\BYTEop':----------------------v----------------------"Bit 0 operation."Bito := inl at: O.outl := (inl from: 1 to: 7), Biti.______________________ A _

Text for function 'Bitl' of 'TopLevel\TopLevel\Core8051\ALUunit\BYTEop':----------------------v----------------------"Bit 1 operation."Bito := inl at: 1.outl := (inl from: 2 to: 7), BitL (inl at: 0).______________________ A _

Text for function 'Bit2' of 'TopLevel\TopLevel\Core80Sl\ALUunit\BYTEop':----------------------v-----------------------Bit 2operation.-Bito := inl at: 2.outl := (inl from: 3 to: 7), BitL (inl from: (I to: 1).----------- - -- - -- - -- --""-- - - ------- ----- - - ----

Text for function 'Bit3' of ''j',:;.pLevel\TC,pLevel\Core80S1\ALUunit\BYTEOp':----------------------v-----------------------Bit 30peration.-Bito := inl at: 3.outl := (inl from: 4 to: 7), BitL (inl from: 0 to: 2).

Text for function 'Bit4' of 'TopLevel\TopLevel \Core80S1 \ALUunit \BYTEop , :----------------------v-----------------------Bit 4 operation.-Bito := inl at: 4,outl := (inl from: S to: 7), Biti, (inl from: 0 to: 3).

Text for function 'BitS' of 'TopLevel\TopLevel\Core8051\ALUunit\BYTEop':----------------------v----------------------"Bit 5 operation."Bito := inl at: 5.outl := (inl from: 6 to: 7), Biti, (inl from: 0 to: 4).______________________ A _

Text for function 'Bit6' of 'TopLevel\TopLevel\Core8051\ALUunit\BYTEop':----------------------v----------------------"Bit 6 operation."Bito := inl at: 6.outl := (inl at: 7), BitL (inl from: 0 to: 5).______________________ A _

Text for function 'Bit7' of 'TopLevel\TOpLevel\Core80S1\ALUunit\BYTEop':----------------------v-----------------------Bit 7 operation.-Bito := inl at: 7.outl := BitL (inl from: 0 to: 6),

'TopLevel\TopLevel\Core805l\ALUunit\DV_CTRL' is an operator.

This operator has 5 functions and is controlled by an unnamed control input.The default function is 'NOP'.

- 54-

Enhanced 8051 Core



Control specification:----------------------y----------------------"Control ALU access."%0100000000, "NOP"%0101000000, "JC reI"%0101010000, "JNC rel"%0101100000, "JZ rel"%0101110000, "JNZ rel"%0110000000, "SJHP rel"%0110010000, "HOV DPTR third byte"%1010010000, "HOV DPTR second byte"%1110010000, "HOV DPTR first byte"%1011000000, "PUSH dir second cycle"%1111000000, "PUSH dir third cycle"%10111xOOOO, "MOVX @DPTR second cycle."%01xxxx0001, "AJHP, ACALL, GJMP, GCALL and not implemented functions"%01000x0010, "LJMP and LCALL"%0100100010, "RET"%10111x001x, "MOVX @Ri second cycle."%0100000011, "RR A"%0100010011, "RRC A"%0100100011, "RL A"%0100110011, "RLC A"%0101110011, "JMP @A+DPTR"%1010000011, "MOVC A,@A+PC second cycle."%1010010011, "MOVC A,@A+DPTR second cycle."%0110100011, "INC DPTR"%0110110011, "CPL C"%0111000011, "CLR C"%0111010011. "SETB C"%01xxxx0100, "ALL inputs valid"%1010x00100, "DIV AB and MUL AB last cycle"%101000011x, "MOV dir.@Ri"%1010001x:,x Ne,rmal. "HOV dir,Rn"%0100010000, "JBC bit. rel"%0100100000, "JB bit. rel"%0100110000, "JNB bit,rel"%0110100000, "ORL c. /bit"%0110110000, "ANL C, /bit"%0111000000, "PUSH dir"%0111010000, "POP dir"%1011010000, "POP dir"%0101000010, "ORL dir,A"%0101010010, "ANL dir,A"%0101100010, "XRL dir, A"%0101110010, "ORL C. bi t"%0110000010, "ANL C, bit"%0110010010, "HOV bit. C"%0110100010, "MOV C, bit"%0110110010, "CPL bit"%0111000010, "CLR bit"%0111010010, "SETB bit"%0101000011, "ORL dir, Hdata"%0101010011, "ANL dir, Hdata"%0101100011, "XRL dir, Hdata"%0100000101, "INC dir"%0100010101, "DEC dir"%0100100101, "ADD A,dir"%0100110101, "ADDC A, dir"%0101000101, "ORL A,dir"%0101010101, "ANL A,dir"%0101100101, "XRL A,dir"%0101110101, "HOV dir, Hdata"%0110000101, "MOV dir,dir first cycle"%1010000101, "MOV dir,dir second cycle"%0110010101, "SUBB A, dir"%0110110101, "CJNE A, dir, rel"%0111000101, "XCH A,dir"%0111010101, "DJNZ dir,rel"%0111100101, "MOV A,dir"%0111110101 Direct. "MOV dir.A"%010000011x, "INC @Ri"%010001011x, "DEC @Ri"%010010011:<, "ADD A,@Ri"%010011011:-:, "ADDC A,@Ri"%01010001lx, "ORL A,@Ri"%0101010l1x, "ANL A,@Ri"%010110011x, "XRL A,@Ri"%011001011x, "SUBS A,@Ri"

- 55 -

Enhanced 8051 Core


%011011011x, ·CJNE @Ri,*data.dir·%011100011x, ·XCH A,@Ri·%011101011x, ·XCHD A,@Ri·%011110011x, ·MOV A,@Ri"%0100001xxx, "INC Rn"%0100011xxx, "DEC Rn"%0100101xxx, "ADD A,Rn"%010011lxxx, "AnDC A,Rn"%0101001xxx, ·ORL A,Rn"%0101011xxx, "ANL A,Rn"%0101101xxx, "XRL A,Rn"%0110011xxx, "SUBB A,Rn"%0110111xxx, "CJNE Rn,Mdata,re1"%0111001xxx, "XCH A,Rn"%0111011xxx, "DJNZ Rn,rel"%0111101xxx RAMread, "MOV A,Rn"%010111011x, "MOV @Ri, Mdata"%101010011x, "MOV @Ri,dir"%011111011x, "MOV @Ri,A"%0101111xxx, "MOV Rn,Mdata"%1010101xxx, "MOV Rn,dir"%0111111xxx RAMwrite, "MOV Rn,A"______________________ A _

Enhanced 8051 Core

OUtput connectorInput connectorInput connector

1 bit ) with name 'CTRL'1 bit ) with name 'DIRDV'2 bits) with name 'RAMDV'

Text for function 'Direct' of 'TopLevel \TopLevel\Core80S1 \ALUun it \ DV_CTRL , :----------------------v----------------------"Direct data valid,"CTRL : = DIRDV.

Text for function 'NOP' of 'T':'loLevel\TqoLe'Je!\Core90S1\ALUunit\DV_CTRL':- - - - - - - - - - - - - - - - - - - - - -v- - - - - - - - - - - - - - - - - - - - --"Data not valid."CTRL := 1 zeroes.______________________ A _

Text for function 'Normal' of 'TopLevel\TopLeve1\Core80S1\ALUunit\DV_CTRL':----------------------v----------------------"Data valid."CTRL := 1 ones.______________________ A _

Text for function 'RAMread' of 'TopLevel\TopLevel\Core8051\ALUunit\DV_CTRL':----------------------v----------------------"RAM read data valid."CTRL := RAMDV at: O.

Text for function 'RAMwrite' of 'TopLevel\TopLevel\Core80Sl\ALUunit\DV_CTRL':----------------------v----------------------"RAM write data valid,"CTRL := RAMDV at: 1.

'TopLevel\TopLeve1\Core80S1\ALUunit\JtstMUX' is an operator.



Control specification:----------------------v----------------------"Select boolean operation."%0100010000, "JBC"%0100100000, "JB"%0100110000. "JNB"%0101000000, "JC"%0101010000 Bool. "JNC"----------------------~----------------------


OUtput connector

bitbitbit

with name 'ALU'with name 'BOOL'with name 'Jtst'

Text for function 'ALU' of 'TopLevel\TopLevel\Core80S1\ALUunit\JtstMUX':----------------------v----------------------"ALU operation.'Jtst := ALU.

- 56 -


____________ ~ A _

Text for function 'Bool' of 'TopLevel\TopLevel\Core8051\ALUunit\JtstMUX':----------------------v----------------------"Boolean operation."Jtst := BOOL.______________________ A • _

'TopLevel\TopLevel\Core8051\ALUunit\outlMUX' is an operator.



Control specification:----------------------v----------------------"Select boolean operation."%0100010000, "JBC bit,rel"%0110010010, "MOV bit,C"%0110110010, "CPL bit"%0111000010, "CLR bit"%0111010010 Bool. "SETB bit"______________________ A _

Enhanced 8051 Core

Input conneo:torInput connector

Output connector

a bits) with nan\~ 'ALU'8 bits) with na",·? 'BOOL'a bits) with naffi~ '0utl'

Text for function 'ALU' of ',·~pLevel\T·)p:..-=v-=I\Core8051\ALUunit\outlMUX':

----------------------v----------------------"ALU op_=ration."out 1 : = ALU.______________________ A _

Text for function 'Bool' of 'TopLevel\Tc-pLev"I\Core8051\ALUunit\out1MUX':----------------------v----------------------"Boolean operation."out1 := EOOL.______________________ A _

'TopLevel\TopLevel\Core8051\ALUunit\FSWoHUX' is an operator.



Control specification:----------------------v----------------------"Select boolean operation."%0110100000, "ORL C, fbi t"%0110110000, "ANL C, fbit"%0101110010, "ORL Co bit"%0110000010, "ANL C, bit"%0110100010, "MOV C. bit"%0110110011, "CPL C"%0111000011, "CLR C"%0111010011 Bool. "SETB C"______________________ A _


Output connector

8 bits) with name 'ALU'8 bits) with name 'BOOL'a bits) with name 'PSWo'

Text for function 'ALU' of 'TopLevel\TopLevel\CoreB051\ALUunit\PSWoMUX':----------------------v----------------------"ALU operation."PSWo : = ALU.______________________ A ~ _

Text for function 'Bool' of 'TopL_=vel\TopLevel\Core8051\ALUunit\PSWoMUX':----------------------v----------------------"Boolean operation."PSWo := BOOL.______________________ A _

'TopLevel\TopLevel\Core80S1\ARBITER' is a state machine controller.

This state machine controller has 8 states.No stack is available for 'subroutine' calls.This controller is enabled following system reset.

- 57 -


Text for state number 1 (reset state) of 'TopLevel\TopLevel\Core8051 \ ARB ITER , :----------------------v----------------------WAIT: "Wait until multiplication or division is completed."[ALUunit\ALUs\CNTR

ISO IR_SEL\IRop First; "Start up"lSI .. S6 ALUunit\ALUs\CNTR inc;

ALUunit\ALUs\TMP load;«IS7 ALUunit\ALUs\CNTR inc;

ALUunit\ALUs\TMP reset;IR_Sel\1Rop Second;

J;----------------------~----------------~-----

Text for state number 2 of 'TopLevel\TopLevel\Core8051\ARBITER':----------------------v----------------------STAGE1: "Decode instruction register or load next instruction code."[PCUnit\1

ISl PCunit\PCbufop INTR;SP_CTRL\STACK PUSH;->STACKl

);[BUSIFACE\RDY 11 "Wait until instruction code is loaded."[BUS1FACE\Data_in\1R

IS73 PCunit\PCgen MOVC_DF;IS5. S10, S15, S20, S25, S30. S35. S4~. $43, $45,S52,S53.S55,S6~,S63,S65.S7~.S75,$82,SB5.. S&F,S92,S95,SAO,SA2,SA6 .. SAF,SBO,SE2,SB5,SCO,SC2,SC5,SDO,SD2.SD5.SE5.SF5BUS1FACE\RSop AR: "Load direct addressing register AR"PCunit\WR Read:PCunit\PCop INC;»

ISl, S2, Sll, S12, S21, S24, S31, S34, S4 1, S44,S51, S54, S61, S64, S71, S74. S76 .. S7F. S81,S90,$91,$94,$B4,SB6 .. $BFBUSIFACE\RSop 1M: "Load immediate data register 1M"PCunit\WR Read;PCunit\PCop INC;»

1$40,S50,$60,$70,$80,SD8 .. $DFBUSIFACE\RSop REL; "Load relative jump address register- REL"PCunit\WR Read;PCunit\PCop INC;»

IS22,S32 SP_CTRL\STACK POP;BUS1FACE\RSop 1M;RAMunit\Busyop RET;[SP_CTRL\SP_reg from: 5 to: 15

ISO PCunit\PCbufop PCEram;];->STACKl

ISEO BUS1FACE\RSop 1M;PCunit\PCadgen DATA_DP;PCunit\WR Read;»

ISE2.SE3 IR_Sel\1Rop First;BUS1FACE\RSop 1M;PCunit\PCadgen DATA_RAM;PCunit\WR Read;»

1$83 PCunit\PCgen MOVC_PC;PCunit\PC hold;IR_Sel\IRop First;BUSIFACE\RSop 1M;PCunit\WR Read;»

IS93 PCunit\PCgen MOVC_DP;PCunit\PC hold;1R_Sel\1Rop First;BUSIFACE\RSop 1M;PCunit\WR Read;»

ISFO IR_Sel\1Rop First;PCunit\PCadgen DATA_DP;PCunit\WR Write;»

ISF2.$F3 1R_Sel\1Rop First;PCUnit\PCadgen DATA_RAM;PCunit\WR Write;»

IS84.SA4 IR_Sel\1Rop First;ALUunit\ALUs\TMP load;ALUunit\ALUS\CNTR inc;->WA1T

I;IR_Sel\1Rop First;1;«

----------------------~----------------------

Text for state number 3 of 'TopLevel\TopLevel\Core8051\ARBITER':----------------------v----------------------STAGE2: "Decode instruction register or load next instruction code."[BUSIFACE\RDY 11 "Wait until instruction code is loaded."

- 58 -

Enhanced 8051 Core


[BUSIFACE\Data_in\IRIS10.S20.S30.SB4 .. SBF.SD5BUSIFACE\RSop REL; 'Load relative jump address register REL'PCunit\WR Read;PCunit\PCop INC;»

IS43.S53.S63.S75BUSIFACE\RSop 1M; 'Load immediate data register 1M'PCunit\WR Read;PCUnit\PCop INC;»

IS2.S12 PCUnit\PCbufop PCHim;BUSIFACE\RSop 1M;PCUnit\WR Read;PCUnit\PCop INC;»

IS81.S91 PCunit\PCbufop PCEim;BUSIFACE\RSop 1M;PCUnit\WR Read;PCUnit\PCop INC;»

IS90 1R_Sel\1Rop First;BUS1FACE\RSop 1M;PCUnit\WR Read;PCUnit\PCop INC;»

ISDO SP_CTRL\STACK POP;BUS1FACE\RSop 1M;RAMunit\Busyop RET;[BUSIFACE\Data_in\AR 'POP SPL or SPH'

1%10000z01 SP_CTRL\SP_POP NoDec;); »

IS85 1R_SEL\1Rop First;RAMunit\Busyop RET;BUSIFACE\RSop AR; 'Load direct addressing register AR'PCUnit\WR Read;PCunit\PCop INC;»

ISAB .. SAF.SCO RAHunit\Busyc,p RET;IS86 .. S8F.SA6 .. SAF,SCO IR_S-el\IR':;p First;»ISB3.S93.SEO.SE2.SE3.SFO.SF2.SF3IR_Se 1\ I Rop Se':~'nd; - >STAGE 1

1%0;0:00001 PCUnit \PCbufop F'CLim;IR_Sel\IRop First;PCunit\PCgen ABS;->STAGE1

I%Oxx10001 PCUnit \PCbufop PCLim;SP_CTRL \STACK PUSH; - >STJ..CK 1

l;IR_Sel\IRop First;->STAGE1J ;«______________________ A _

Text for state number 4 of 'TopLev-el\TopLevel\Core8051\ARBITER':----------------------v----------------------STAGE3: 'Decode instruction r",gister or load next instruction code.'[BUSIFACE\Data_in\IR

IS86.S87.SA6.SA7 RAHunit\Busyop RET;»IS88 .. $BF.$AB .. $AF IR_Sel\IRop S",cond;->STAGE1ISCO 1R_Sel\IRop Second;

SP_CTRL\STACK PUSH;»ISDO [SP_CTRL\SV lSI

[SP_CTRL\POPregISO •. $4 IR_Sel\IRop First; 'internal stack'IS5 I R_Se 1\IRop Second; 'e:eternal stack'];->STAGEI] ;

] ;[BUSIFACE\RDY10 [BUSIFACE\Data_in\IR

1$85 IR_SEL\IRop NOP;] ;

11 [BUS1FACE\Data_in\IR 'Wait until instruction code is loaded.'IS10.$20.S30.$43.$53.S63.$75.SE4 .. $BF.SD5IR_Sel\IRop First;

IS85 IR_Sel\IRop Second;1$2 PCunit\Pcgen LONG;

IR_Sel\1Rop First;PCunit\PCbufop PCLim;

IS90 IR_Sel\1Rop Second;BUS1FACE\RSop 1M; 'Load immediate data register 1M'PCUnit\WR Read;PCunit\PCop INC;»

IS81.S91 PCunit\PCbufop PCHim;BUSIFACE\RSop IIi; 'L·~ad irr,mediate data reg i ster 1M'PCUnit\WR Read;PCUnit\PCop INC;»

IS12 PCunit \PCbufop PCLirr,;

- 59 -

Enhanced 8051 Core


SP_CTRL\STACK PUSH;->STACKIJ; ->STAGEI

J ;«______________________ A _

Text for state number 5 of 'TopLevel\TopLevel\Core80S1\ARB1TER':----------------------v----------------------STAGE4 :(BUS1FACE\Data_in\IR

IS86,S87,SA6,SA7 1R_Se1\1Rop Second;->STAGE1ISCO [SP_CTRL\SV

lSI 1R_Sel\IRop Third;->STAGE1];

J;[BUS1FACE\RDY11 [BUS1FACE\Data_in\IR "Wait until instruction code is loaded."

IS90 IR_Se1\IRop Third;IS81 PCunit\PCgen GLOBAL;

PCunit\PCbufop PCLim;IR_Sel\IRop First;

IS91 PCUnit\PCbufop PCLim;SP_CTRL\STACK PUSH;»

) ;->STAGEI) ;«______________________ A _

Text for state number 6 of 'T.~pLevel\TopLevel\C0re80S1\ARBITER':

----------------------v----------------------STACKI :[SP CTRL\SV lSI[PCunit \ I

10 [BUS1FACE\Data_in\1RIS22,S32

(SP_CTRL\FOPreglSI SP_CTRL\STACK POP;IS2 RAMunit\BusyoP RET;

SP_CTRL\STACK FOP;PCunit\PCbufop PCHram;

IS3 PCunit\PCbufop FCEram;IS4 SP CTRL\STACK POP;

Pc~nit\PCbufop PCEram;ISS SP_CTRL\STACK POP;

PCunit\PCbufop FCEim;BUSIFACE\RSop 1M;

]; »] ;

1;SP_CTRL\STACK PUSH;PCunit\PCdatop PCH;»J ;«

Text for state number 7 of 'TopLevel\TopLevel\Core80S1\ARB1TER':----------------------v----------------------STACK2 :[SP_CTRL\SV lSI[PCuni t \ I

10 [BUS1FACE\Dato_in\1RIS22,S32

[SP_CTRL\POPreglSI SP_CTRL\STACK POP;IS2 RAMunit\Busyop RET;

SP_CTRL\STACK POP;PCunit\PCbufop PCLram;PCunit\PCgen GLOBAL;[BUSIFACE\Data_in\IRIS22 IR_Sel\1Rop First;IS32 PCunit\1acy.op RET1;

BUS1FACE\RSop IR;PCunit\WR Read;PCunit\PCop INC;

);->STAGEIIS3 [RAMunit\HWR

ISO SP_CTRL\STACK POP;J;PCUnit\PCbufop PCHram;

1$4 SP_CTRL\STACK POP;PCunit\PCbufop PCHram;

ISS SP_CTRL\STACK POP;PCUnit\PCbufop PCHim;BUSIFACE\RSop 1M;

- 60 -

Enhanced 8051 Core


I; »I;

1;SP_CTRL\STACK PUSH;PCUnit\PCdatop PCE;»1;«

Text for state number 8 of 'TopLevel\TopLevel\Core8051\ARBITER':----------------------v----------------------STACK3 :[SP_CTRL\SV lSI[PCUnit \ I

10 [BUSIFACE\Data_in\IRIS22 IR_Sel\IRop First;IS32 PCunit\Iackop RETI;

BUSIFACE\RSop IR;PCUnit\WR Read;PCUnit\PCop INC;

IS22,S32[SP_CTRL\POPregIS2 SP_CTRL\STACK POP;

PCunit\PCbufc,p PCLram;PCunit\PCgen GLOBAL;

IS3 [RAMunit\HWRISO SP_CTRL\STACK FOP;I;PCunit \PCbuf,~p P:::Lr"",;PCunit\PCgen GLOBAL;

1$4 PCunit \PCbufc,p PCLram;PCunit\PCgen GLOBAL;

IS5 PCunit\PCbufop P:::Lim;PCunit\PCgen GLOBAL;

I;ISll,S3l,S5l,$7l PCunit\PCgen AES;

IR_Sel\IRop First;IS12 PCunit\PCgen LONG;

IR_Sel\IRop First;IS9l PCunit\PCgen GLOBAL;

IR_Sel\IRop First;J;

1%1 PCUnit\PCgen GLOBAL;PCunit\I reset;BUSIFACE\RSop IR;PCUnit \WR Read;PCunit\PCop INC;

1; ->STAGEIJ ;«______________________ A _

'TopLevel \TopLevel\Core8051 \BUSIFACE' is a schematic.

Bidirectional connector ( 8 bits) with name 'A'Bidirectional connector (25 bits) with name 'Addrbus'Bidirectional connector ( 8 bits) with name 'ALUoutl'Bidirectional connector ( 8 bits) with name 'ARo'Bidirectional connector ( 8 bits) with namo? 'DATibus'Bidirectional connector ( 8 bits) with name 'OATobus'Bidirectional connector ( 1 bit ) with naTOe 'enable'Bidirectional connector ( 8 bits) with n.a.rn-:1 'IMo'Bidirectional connector (10 bits) with name ' IR'Bidirectional connector ( 3 bits) with name 'IRclr'Bidirectional connector ( 8 bits) with name ' IRo'Bidirectional connector (25 bits) with name 'PCaddr'Bidirectional connector ( 8 bits) with name 'PCdat'Bidirectional connector ( 2 bits) with name 'PCWR'Bidirectional connector ( 1 bit ) with name 'Ready'Bidirectional connector ( 8 bits) with name 'RELo'Bidirectional connector ( 1 bit ) with name 'RS'Bidirectional connector (16 bits) with name ' SPaddr'Bidirectional connector ( 2 bits) with name 'SPWR'Bidirectional connector ( 2 bits) with name 'WR'============================~========~~~===~~

'TopLevel\TopLevel\Core8051\BUSIFACE\AODR_op' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'PC'.

Enhanced 8051 Core

Control connector (

Control specification:

bit ) without a name

- 61 -


----------------------v----------------------·Select external address.·%1 SP. ·Stack operation.·______________________ A _

OUtput connector (25 bits) with name 'ADDR'Input connector (25 bits) with name 'PC'Input connector (16 bits) with name 'SP'

Text for function 'PC' of 'ToPLevel\TopLevel\Core8051\BUSIFACE\ADDR_Op':----------------------v----------------------·Program counter address,·ADDR := PC,

Text for function 'SP' of 'TopLevel\TopLevel\Core8051\BUSIFACE\ADDR_op':----------------------v----------------------·Stack address,·ADDR := lones, 8 zeroes, SP.______________________ A _

'TopLevel\TopLevel\Core8051\BUSIFACE\Addr_out, is a schematic,

Bidirectional connector (25 bits) with naF.le 'ADDRi'Bidirectional connector (25 bits) with name 'ADDRo'Bidirectional connector ( 2 bits) with name 'wRi'Bidirectional connector ( 2 bits) with name 'WRo'

'TopLevel\TopLevel\Core8051\BUSIFACE\Addr_out\AddrReg' is a register,

This register is 25 bits wide and is controlled by control input 'WRo'.The default function is 'hold'.This register is loaded with value 0 following system reset.


Control specification:----------------------v----------------------%01 load. ·Continue reading.'%10 load. ·Continue writing.'______________________ A _

'TopLevel\TopLevel\CoreB051\BUSIFACE\Addr_out\AddrSel' is an operator.

This operator has 2 functivns and is controlled by control input 'WRi'.The default function is 'OldAddr'.

Input connector (25 bits) with name ' ADDRi'Input connector (25 bits) with name ' in'

Output connector (25 bits) with name '0Ut.'

Control connector ( 2 bits) with narrl"? 'WRi'

Control specification:----------------------v----------------------%OOOldAddr. ·Idle.·%01 NewAddr. ·Start read cycle.·%10 NewAddr. ·Start write cycle.·______________________ A _

Enhanced 8051 Core

Text for function 'NewAddr' of 'TopLevel\TopLevel\Core8051\BUSIFACE\Addr_out\AddrSel':----------------------v-----------------------New read or write cycle.-out := ADDRi.______________________ A _

Text for function 'OldAddr' of 'TopLevel\TopLevel\Core8051\BUSIFACE\Addr_out\AddrSel':----------------------v----------------------·continue read or write cyle.·out := in.______________________ A _

'TopLevel\TopLevel\Core8051\BUSIFACE\Data_in' is a schematic.

Bidirectional connector 8 bits) with name 'ARo'Bidirectional connector 8 bits) with name 'DATi'Bidirectional connector 8 bits) with name ' IMo'Bidirectional connector 8 bits) with name ' IRo'Bidirectional connector 1 bit ) with name 'Ready'Bidirectional connector S bits) with naTTI>? 'RELo'Bidirectional connector 3 bits) with naTTIC 'Rsi'Bidirectional connect-or 2 bits) with nama 'WRo'====~~==~==~~=~~=~~~~~===~~~==~=~==========~=

- 62-


'TopLevel\TopLevel\Core805l\BUSIFACE\Data_in\AR' is a register.



Control specification:----------------------v----------------------"Load new direct address,"%010 load.______________________ A _

'TopLevel\TopLevel\Core805l\BUSIFACE\Data_in\IM' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold',This register is loaded with value 0 following system reset.


Control specification:----------------------v-------~--------------

"Load new immediate data.·%011 load.----------------------~----------------------

'TopLevel\TopLevel\Core305l\EUSIFACE\Data_in\IR' is a register.

This register is 8 bits wide and is cc·ntr~,ll~d by an unnamed control input.The default function is 'hold'.This register is l·~aded with value f) f·~ll:Ming system reset.


Control specification:----------------------v-----------------------Load new instruction code.-%001 load.______________________ A _

'TopLevel\TopLevel\Core8051\BUSIFACE\Data_in\RegSel' is an operator.

This operator has 2 functions and is controlled by control input 'RDYi'.The default function is 'Idle'.

Output connectorControl connector

3 bits) with name 'out'1 bit) with name 'RDYi'

Control specification:----------------------v----------------------%0 Idle.%1 RegLoad.______________________ A _

Input connector ( 3 bits) with name 'RSi'Input connector ( 2 bits) with nam~ 'WRo'

Text for function 'Idle' of 'TopL~vel\To~Level\Core805l\BUSIFACE\Data_in\RegSel':

----------------------v----------------------out := 3 zeroes.______________________ A _

Text for function 'RegLoad' of 'TopLevel\TopLevel\Core8051\BUSIFACE\Data_in\RegSel':----------------------v----------------------"Select register to load if reading is ready."out := (WRo at: 0) if 0: 3 zeroes

ifl: RSi.______________________ A _

'TopLevel\TopLevel\Core9051\BUSIFACE\Data_in\REL' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold',This register is loaded with valu~ a folle·wing system reset.


Control specification:----------------------v----------------------"Load new relative jump address.·

- 63 -


%l00 load.______________________ A _

============================================='TopLevel\TopLevel\CoreBOSl\BUSIFACE\Data_out' is a schematic.

Enhanced 8051 Core

Bidirectional connector ( 8 bits) with name 'A'Bidirectional connector ( 8 bits) with name ' ALUout1'Bidirectional connector ( B bits) with name 'DATo'Bidirectional connector (10 bits) with name ' IR'Bidirectional connector ( B bits) with name 'PCdat'Bidirectional connector ( 2 bits) with name 'WRi'======~======================================

'TopLeVel\TopLevel\CoreBOS1\BUSIFACE\Data_out\DataBuf' is a register.

This register is B bits wide,The default function is 'load'.This register is loaded with value 0 following system reset.


'TopLevel\TopLevel\Core80S1\BUSIFACE\Data_out\DataSel' is an operator.

This operator has 2 functions and is controlled by control input 'WRi'.The default function is 'OldData'.

Input connector 8 bits) with nam'2 'DATA'Input connector 8 bits) with name ' in'

Output connector B bits) with name 'out'Control connector 2 bits) with name 'wRi'

Control specification:----------------------v----------------------'Detect external write cycle,'(1)%1 NewData. 'Start write cycle.'______________________ A _

Text for function 'NewData' of 'T~pLevel\TopLevel\CoreB05l\BUSIFACE\Data_out\DataSel':

----~-----------------v----------------------

'New write cycle.'out : = DATA.______________________ A _

Text for function 'OldData' of 'TvpL"v"1\T~·pLev"1\Core8051\BUSIFACE\Data_out\DataSel':

----------------------v----------------------·Continue write cyle.'out :;: in.______________________ A _

'TopLevel\TopLevel\Cor"SOSl\BUSIFACE\Data_0ut\DATv_Sel' is an operator.

This operator has 3 functions and is controlled by control input 'IR'.The default function is 'PCstacK'.

Input connect.or B bits) with name 'A'Input connector B bits) with nama 'ALUout I'

Output connector ( B bits) with nam~? 'DATA'Control connector (10 bits) with name ' IR'

Control specification:----------------------v----------------------'Select output data,'%1011000000 PUSH. 'PUSH direct.'%0111110000, 'HOVX @DPTR,A'%011111001x HOVX. 'HOVX @Ri,A·______________________ A _

Input connector ( B bits) with name 'PCdat'

Text for function 'MOVX' of 'TopLevel\TopLevel\CoreBOS1\BUSIFACE\Data_out\DATo_Sel':----------------------v----------------------'HOVX @DPTR or @Ri,A.'DATA := A.______________________ A _

Text for function' PCstacy.' of 'TopLevel \T'~pLevel\CoreB051 \BUSIFACE\Data_out \DATo_Sel':----------------------v----------------------'PUSH program counter onto stack.'DATA := PCdat,----------------------~----------------------

Text for function 'PUSH' of 'TopLevel \TopLevel\CoreBOS1 \BUSIFACE\Data_out \DATo_Se 1 ':

- 64-


----------------------v----------------------"PUSH dir."DATA : = ALUout 1.______________________ A _

'TopLeve1\TopLeve1\Core8051\BUSIFACE\RDY' is a register.



'TopLevel\TopLevel\Core8051\BUSIFACE\RSbuf' is a register.

This register is 3 bits wide and is controlled by an unnamed control input.The default function is 'load'.This register is loaded with value 0 following system reset.


Control specification:----------------------v----------------------"Reset when data is loaded."%1 reset.______________________ A _

'TopLevel\TopLevel \Core8051 \BUSIFACE\RSop' is an operator.

This operator has 5 functions.The default function is 'Normal'.

Input e:,;.nnector 3 bits) with n.ztrrl~ . in'Input connector 1 bit ) with narn02 'RS'

Output c,:.nne..:tor 3 bi tsl with name . RS(·'

Text for function 'AR' of 'T",pLevel\TopLevel\Core8051\BUSIFACE\RSop':----------------------v-----------------------Load direct addressing register.-RSo := 1 zeroes, lones, 1 zeroes.

Text for funct ion '1M' of 'Tor-Leve I \T.:.pLevel \Coro8051 \BUSIFACE\RSop' :----------------------v----------------------"Load immediate data register."RSo := 1 zeroes, 2 ones.

Text for funct ion 'IR' of 'TopLeve I \ TopLeve I \Col-e8051 \BUSI FACE\RSop' :----------------------v-----------------------Load instruction code register.-RSo := 2 zeroes, 1 ones.______________________ A _

Text for function 'Normal' of 'TopLevel\TvpLev~I\Core8051\BUSIFACE\RSop':

----------------------v----------------------"Continue data input."RSo := RS if0: in

if1: (2 zeroes, lanes).______________________ A _

Text for function 'ReI' of 'TopLevel\TopLevel\Core8051\BUSIFACE\RSop':----------------------v----------------------"Load relative jump address register."RSo := lones, 2 zeroes.______________________ A _

'TopLevel\TOpLevel\Core8051\BUS1FACE\SPwrop' is an operator.

This operator has 2 functions and is c(·ntrolled by an unnamed control input.The default function is 'SP'.


Control specification:----------------------v----------------------"Detect internal stack acces."(8 •• 15)SO PC.______________________ A _

Output connector ( 1 bit) with name 'SPc'

- 65 -

Enhanced 8051 Core


Input connector ( 2 bits) with name 'SPWR'

Text for function 'PC' of 'TopLevel\TopLevel\Core8051\BUSIFACE\SPwrop':----------------------v------------------·---"No external stack acces,"SPc := 1 zeroes,______________________ A _

Text for function 'SP' of 'TcpLevel\TopLevel\Core8051\BUSIFACE\SPwrop':----------------------v----------------------·External stack acces."SPc := (SPWR at: 0) \/ (SPWR at: 1).______________________ A _

'TopLevel\TopLevel\Core8051\BUSIFACE\WR_Ctrl' is a schematic.

Bidirectional connector 1 bit ) with name 'enable'Bidirectional connector 1 bit ) with name 'ROYi'Bidirectional connector 2 bits) with name 'wRi'Bidirectional connector 2 bits) with name 'WRo'

'TopLevel\TopLeve1\Core8051\BUSIFACE\WR_Ctrl\WRop' is an operator,

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Continue'.


Control specification:----------------------v----------------------%00 Continue. ·Continue cycle.·%01 NewWR. ·Start read cycle."%10 NewWR. "Start write cycle."______________________ A _

Enhanced 8051 Core

Output connectorInput connectorInput connector

OUtput connector

1 bit ) with name 'enable'2 bits) with name . in'2 bits) with name 'wRi'2 bits) with name 'WRo'

Text for function 'Continue' of 'TopLevel\TopLevel\Core8051\BUSIFACE\WR_Ctrl\WRop':----------------------v----------------------"Continue previous cycle."WRo := in.enable := in at: 1.______________________ A _

Text for function 'NewWR' of 'TorLevel\T0l'L.?vel\C<ne8051\BUSIFACE\WR_Ctrl\WRop':- - - - - - - - - - - - - - - - - - - - - -v- - - - - - - - - - - - - - - - - - - - ---Start read or write cycle.-WRo : = WRi.enable := WRi at: 1.---------------------_1\_---------------------

'TopLevel\TopLevel\Core80S1\EUSIFACE\WR_Ctrl\WRreg' is a register.



Control specification:----------------------v----------------------"Register WR contains WRo contents of rrevious cycle."%0 load. ·Continue.·%1 reset. "End of read-write cycle.·

A---------------------- ----------------------

'TopLevel\TopLevel\Core8051\BVSIFACE\WR_op' is an operator.



Control specification:----------------------v----------------------%1 STACK.---------------------_1\_---------------------

Input connector ( 2 bits) with name 'PC'Input connector ( 2 bits) with name 'srWR'

- 66 -


Output connector ( 2 bits) with name 'WRo'

Text for function 'PC' of 'TopLevel\TopLevel\Core8051\BUSIFACE\WR_op':----------------------v---------·------------"Program counter unit operation."WRo := PC.______________________ A _

Text for function 'Stack' of 'TopLevel\TopLevel\Core8051\BUSIFACE\WR_op':----------------------v----------------------"Stack operation."WRo := SPWR.______________________ A _

'TopLevel\TopLevel\Core8051\Direct' is a schematic.

Enhanced 8051 Core

Bidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connectorBidirectional connector

8 bits) with name 'Ai'8 bits) with name 'ALUoutl'8 bits) with name 'AR'8 bits) with name 'B i'8 bits) with name 'DirDat'1 bit) with name 'OIROV'8 bits) with n5"1~ 'DIRo'

( 8 bits) with name 'opi'(10 bits) with name 'IR'( 8 bits) with name 'pswi'( 8 bits) with name 'RAMDATi'( 2 bits) wlth name 'RAMOV'(10 bits) with name 'SFR'(10 bits) with name 'SFRaddr'( 8 bits) with name 'SFRi'( 8 bits) with name 'SPi'

'TopLevel\TopLevel\Core8051\Direct\AR_SEL' is an operator.

This operator has 2 functions and is ccntrolled by an unnamed control input.The default function is 'Direct'.


Control specification:----------------------v----------------------"Select boolean operations (Direct operation is default).'%0100010000 BOOL. "JBC bit,rel"%0100100000 BOOL. "JB bit,rel"%0100110000 BOOL. "JNB bit,rel"%0110100000 BOOL. "ORL C,/bit"%0110110000 BOOL. "ANL C, /bit"%0101110010 BOOL. "ORL C.bit'%0110000010 BOOL. "ANL C.bit'%0110010010 BOOL. "MOV bit,C'%0110100010 BOOL. "MOV C,bit'%0110110010 BOOL. "CPL bit"%0111000010 BOOL. "CLR bit"%0111010010 BOOL. "SETB bit"

Input connector ( 8 bits) with name 'AR'Input connector ( 2 bits; with name 'RW'

OUtput connector (10 bits) with name 'SFR'

Text for function 'BOOL' of 'TopLevel\TopLevel\Core8051\Direct\AR_SEL':----------------------v----------------------"Boolean operation."SFR := (AR at: 7) if0: RW, 2 zeroes, 1 ones. (AR from: 3 to: 7)

if1: RW, (AR from: 3 to: 7), 3 zeroes.----------------------~----------------------

Text for function 'Direct' of 'TopLevel\TopLevel\Core8051\Direct\AR_SEL':----------------------v----------------------"Direct addressing."SFR : = RW, AR.______________________ A _

'TopLevel\TopLevel\Core8051\Direct\Dir_Sel' is an operator.

This operator has 7 functions and is controlled by an unnamed control input.The default function is 'SFR'.



- 67 -


----------------------v----------------------·Select direct addressing llLode.'(0 •• 7)%Oxxxxxxx RAM.%10000xOl SP.%1000001x DP.%10000100 DP.%11010000 PSW.%11100000 A.%11110000 B.----------------------~----------------------

Input connector ( 8 bits) with name 'Ai'Input connector ( 8 bits) with name 'Bin'

OUtput connector ( 1 bit ) with name ' DIRDV'OUtput connector ( 8 bits) with name 'DIRo'

Input connector ( 8 bits) with name 'DPi'Input connector ( 8 bits) with name ' pswi'Input connector ( 2 bits) with name 'RAMDV'Input connector ( 8 bits) with name 'RAMi'Input connector (10 bits) with name 'SFR'

Output connector (10 bits) with name 'SFRaddr'Input connector ( 8 bits) with name 'SFRi'Input connector ( 8 bits) with name 'spi'

Text for function 'A' of 'TopLevel \T,:,pLevel \C,:,re8051 \Direct \Dir_Sel':----------------------v----------------------·SFR operation on register A,DIRo := Ai.SFRaddr := 2 zeroes, (SFR frollL: 0 to: 7).DIRDV:= (SFRat: 9) \/ (SFF."t: '=').

Text for function'S' of 'TopLevel\TopLevel\Core8051\Direct\Dir_Sel':----------------------v----------------------

·SFR operation on register B.·DIRo := Bin.SFRaddr := 2 zeroes, (SFR from: 0 to: 7).DIRDV:= (SFR at: 9) \/ (SFR at: 8).

Text for function 'DP' of 'T0pLevel\Tc,pLevel\Core8051\Direct\Dir._Sel':----------------------v----------------------·SFR operation on byte in register DP."DIRo : = DPi.SFRaddr := 2 zeroes, (SFR from: 0 to: 7).DIRDV:= (SFRat: 9) \/ (SFRat: 8).______________________ A _

Text for function 'PSW' of 'TopLevel\TopLevel\Core8051\Direct\Dir_Sel':----------------------v----------------------·SFR operation on register PSW."DIRo : = pswi.SFRaddr := 2 zeroes, (SFR from: 0 to: 7).DIRDV := (SFR at: 9) \/ (SFR at: 8).______________________ A _

Text for function 'RAM' of 'TopLevel\To~Level\Core8051\Direct\Dir_Sel':

----------------------v----------------------·SFR operation on internal RAM byte.·DIRo : = RAMi.SFRaddr := 2 zeroes, (SFR from: 0 to: 7).DIRDV := «(SFR at: 8) /\ (RAMDV at: 1) \/ «SFR at: 9) /\ (RAMDV at: 0».

Text for function 'SFR' of 'T,:,pL;;vel\T,)pLev·:;1\Cor<?8051\Direct\Dir_Sel':----------------------v----------------------"SFR operation on external SFR."DIRo : = SFRi.SFRaddr := SFR.DIRDV:= (SFRat: 9) \/ (SFRat: 8).

Text for function 'SP' of 'TopLevel\TopLevel\Core8051\Direct\Dir_Sel':----------------------v----------------------·SFR operation on byte in register SP."DIRo : = SPi.SFRaddr : = 2 zeroes, (SFR from: 0 to: 7).DIRD'/ : = (SFR <:Ie: 9) \/ (SFR at: 2).______________________ A _

'TopLevel\TopLevel\Core8051\Direct\DIRbuffer' is a schematic.

- 68 -

Enhanced 805 I Core


Bidirectional connector ( 1 bit ) with name 'DIRDV'Bidirectional connector ( 8 bits) with name 'DIRi'Bidirectional connector ( 8 bits) with narr.,\? 'DIRo'Bidirectional connector ( 8 bits) with name • in'Bidirectional connector (10 bits) with name ' IR'Bidirectional connector ( 8 bits) with name 'out'Bidirectional connector ( 8 bits) with name 'RAMdat i'Bidirectional connector ( 2 bits) with name 'RAMDV'============================================='TopLevel\TopLevel\Core8051\Direct\DIRbuffer\DIRbuf' is a register.

This register is 8 bits wide and is controlled by an unnamed control input,The default function is 'hold'.This register is loaded with unknown values after a system reset.


Control specification:----------------------v----------------------·Output buffer for instructions:

MOV direct,direct & MOV direct,@Ri & MOV direct,Rn·%1 load.______________________ A _

'TopLevel\TopLevel\Core8051\Direct\DIRbuffer\DIRbufop' is an operator.

This operator has 3 functions and is controlled by control input 'IR'.The default function is 'Normal'.

Input connector ( 8 bits) with name 'Euf'Input connector ( 1 bit ) with r.am.: 'DIED..,'Input co:>nn·:;ctor ( 8 bits) with flame 'DIR;'

Output C0nnector ( 8 bits) with narrl'9 'DIRo'Input connector ( 8 bits) with name • in'

Control connector (10 bits) with nam~::? ' IR'

Control specification:----------------------v----------------------·Direct addressing output buffer.·%0111000000 BufferIn. "PUSH dir first cycle"%1011000000 BufferOut. "rUSH dir second cycle"%0110000101 BufferIn. "MOV dir,dir first cycle"%1010000101 BufferOut. "MOV dir,dir secone! cyde"%011010011x Bu HerIn. ·MOV @Ri, di r first cy·~le"

%101010011x BufferOut. "MOV @Ri,dir secc·nd cycle"%0110101xxx BufferIn. "MOV Rn,dir first cycle"%1010101xxx BufferOut. "MOV Rn,dir sec,~nd cycle"______________________ A _

Output connector 1 bit ) with name 'load'Output connector 8 bits) with name 'out'

Input connector 2 bits) with name ' RAMDV'Input connector 8 bits) with name 'RAMi'

Enhanced 8051 Core

Text for function 'BufferIn' of 'TopLevel\TopLevel\Core8051\Direct\DIRbuffer\DIRbufop':----------------------v----------------------·Buffer direct addressing output."load := DIRDV.DIRo := in.______________________ A _

Text for function 'BufferOut' of 'TopLevel\TopLevel\Core8051 \Direct \DIRbuffer\DIRbufop' :----------------------v----------------------·Output buffer if not read for ASA RAM."out := (RAMDV at: 0) itO: Buf

i fl: RAMi.load ._ RAMDV at: O.DIRo ._ (RAMDV at: 0) if 0: Buf

if 1: F.AI~ i .______________________ A _

Text for function 'Normal' of 'TopLevel \T,:·pLevel \Cor-e8051 \Direct \DIRbuffer\DIRbufop':----------------------v----------------------·Normal direct addressing output."load := 1 zeroes.DIRo := in.out : = DIRi.______________________ A _

'TopLevel\TopLevel\Core8051\Direct\RWop' is an operator.

This operator has 4 functions and is controlled by an unnamed control input.

- 69-


The default function is 'NOP'.


Control specification:----------------------v----------------------"Select SFR mode."%0100100000, "JB bit, reI"%0100110000, "JNB bit, reI"%0110100000, "ORL C,/bit"%0110110000, "ANL C, /bit"%0111000000, 'PUSH dir"%0101110010, "ORL C,bit"%0110000010, "ANL C,bit"%0110100010, "MOV C,bit"%0100100101, "ADD A, dir"%0100110101, "ADDC A, dir"%0101000101, "ORL A,dir"%0101010101, "ANL A,dir"%0101100101, "XRL A, di r'%0110000101, "MOV dir, dir (first cycle)"%0110010101, "SUBB A,dir"%0110110101, "CJNE A, d i r, re I"%0111100101, "MOV A,dir"%01101001Ix, "MOV @Ri.dir"%0110101xxx Read. "MOV Rn,dir"%0111010000, "POP dir"%1011010000, "POP dir"%0101110101, "MOV di r, Mdata'%1010000101, "MOV dir,dir (s'2,ocmd c:/cl·:)"%0111110101, "MOV dir,A"%101000011:<, "t10V di",,,Ri (£'o·oor,'.l 'oycl",) "%1010001xxx Wrt. 'MOV dir,Rn (sec0nd cycle)"%0100010000, "JBC bit,rel'%0101000010, "ORL dir, A"%0101010010, 'ANL dir,A"%0101100010, 'XRL dir,A"%0110010010. 'MOV bit,C"%0110110010, "CPL bit'%0111000010. "CLR bit'%0111010010, "SETB bit"%0101000011. 'ORL A, dir"%0101010011, "ANL A,dir"%0101100011, "XRL A,dir"%0100000101, "INC dir"%0100010101, "DEC dir"%0111000101, "XCH A,dir"%0111010101 Modify. "DJNZ dir, rei"______________________ A _

Output connector ( 2 bits) with name 'RW'

Text for function 'M,~dify' of 'Tc,pLevel\TopLev",I\Core8051\Direct\RWop':----------------------v----------------------"Mod i fy SFR."RW := 2 ones.______________________ A _

Text for function 'NOP' of 'TopLevel\TopLevel\Core8051\Direct\RWop':----------------------v-----------------------No SFR access.-RW := 2 zeroes.

Text for function 'Read' of 'TopL",vel\TopLev",I\Core8051\Direct\RWop':----------------------v----------------------"Read SFR."RW := 1 ones, 1 zeroes.______________________ A _

Text for funct ion 'Wrt' of . T,~pLev02 I \ Tq:>Lev02 1 \Core8051 \Di rect \RWop' :----------------------v----------------------"Write SFR."RW := 1 zeroes, 1 ones.______________________ A _

'TopLevel\TopLevel\Core8051\DP_reg' is a schematic.

Bidirectional connector ( 8 bits) with narne 'DirDat'Bidirectional connector (24 bits) with narrle 'OF'Bidirectional connector ( 8 bits) with name 'DPo'Bidirectional connector ( 8 bits) with name ' 1M'

- 70 -

Enhanced 8051 Core


Bidirectional connector (10 bits) with name 'IR'Bidirectional connector (10 bits) with name 'SFR'

'TopLevel \TopLevel\Core80S1 \DP_reg \OP_CTRL , is an operator.

This operator has 4 functions and is controlled by an unnamed control input.The default function is 'SFR'.


Control specification:----------------------v-----·----------------"Select OP control."%0110010000 OPE. "HOV OPTR.#data24; first byte'%1010010000 OPH. "HOV DPTR,#data24; second byte'%1110010000 OPL. "MOV OPTR,#data24; third byte"______________________ A _

Input connector ( 8 bits) with name 'OPi'OUtput connector ( 8 bits) with namo? 'OPo'OUtput connector (10 bits) with name 'OPsfr'

Input connector ( 8 bits) with name ' IM'Input connector (10 bits) with name 'SFR'

Text for function 'OPE' of 'TopLevel\TopLevel\Core80S1\OP_reg\OP_CTRL':----------------------v----------------------'Load new data pointer; third byte."OPsfr := 1 zeroes. 2 ones, 4 zeroes, lones, 2 zeroes.OPo := IH.----------------------~----------------------

Text for funct ion 'OPH' of 'T,~pLev,,1\TorL"vel \C,ne80S1 \OP_reg\OP_CTRL' :----------------------v-----------------------Load new data pointer; second byte.-DPsfr :~ 1 zeroes, 2 vnes, 5 ~eroes, 2 ones.OPo := IH.----------------------~----------------------

Text for function 'OPL' of 'T,~pLevel\TopLe'Jel \Core80S1\DP_reg\OP_CTRL':----------------------v----------------------"Load new data pointer; first byte.'OPsfr := 1 zeroes. Zones,S zeroes, lones, 1 zeroes.DPo := IM.----------------------~----------------------

Text for fun~tion 'SFR' of 'TopLevel\TopLevel\Core80S1\DP_r"g\OP_CTRL':----------------------v----------------------"Oirect addressing."OPsfr := SFR.OPo : = opi.----------------------~----------------------

'TopLevel\TopLevel\Core80S1\DP_reg\DF_Sel' is an operator.

This operator has 3 functions and is controlled by an unnamed control input.The default function is 'OPL'.

Control conne~tor (IO bits) without a name

Control specification:----------------------v----------------------'Select data pointer byte."(0 •• 7)~10000011 OPH. "DPH"%10000100 OPE. "OPE"______________________ A _

Input connector (24 bits) with name 'DP24i'Output connector (24 bits) with name 'DP240'

Input connector ( 8 bits) with name 'OPi'OUtput connector ( 8 bits) with name 'OPo'

Text for function 'DPE' of '7opLevel\TopLevel\Core80S1\OP_reg\OP_Sel':----------------------v----------------------"Select third byte from data pointer."OPo := OP24i from: 16 to: 23,OP240 : = oPi, (OP24i from: 0 to: 15).______________________ A _

Text for fun~t ion 'DPH' ~,t 'T·:,pLeve 1\TopLeve I \C,~re80S1 \OP_reg\DP_Se l' :----------------------v----------------------"Select second byte from data pc.inter."OPo := DP24i from: 8 to: 15.

- 71 -

Enhanced 8051 Core


DP240 := (DP24i fr0m: 16 to: 23). DP;, (DP24i from: 0 to: 7).______________________ A _

Text for function 'DPL' of 'T0PLevel\TopLevel\Core805l\DP_reg\DP_Sel':----------------------v----------------------"Select first byte from data pointer."DPo := DP24i from: 0 to: 7.DP240 := (DP24i from: 8 to: 23), DPi.______________________ A _

'TopLevel\TopLevel\Core805l\DP_reg\DPop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'OLD_DP'.


Control specification:----------------------v----------------------"Control of new data pointer is written."%xllOOOOOlx NEW_DP.%x110000l00 NEW_DP.______________________ A _

Input connector (24 bits) with n3~:e 'DP'Input C0nnector (~4 bits) with name' in'

Output connoctor (2-l bits) with name 'out'

Text for function . NEW_DP , or 'TopLevel \TopLevel\Core8051 \DP_reg\DPop' :----------------------v----------------------"Load data p0inter with new value."out := DP.

Text for funct ion 'OLD_DP' of . Tc'rLevel \TopLevel \Core8051 \DP_reg\DPop' :----------------------v----------------------"Load data rointer with same value."out := in.

'TopLevel\TopLevel \Core8051 \DP_reg\DPreg' is a register.

This register is 24 bits wide and is controlled by an unnamed control input.The default function is 'load'.This register is loaded with value 0 following system reset.

The value loaded for the . reset , command is O.

Control specification:----------------------v----------------------"Load data pointer with same or new value unless increase data pointer instruction."%0110100011 inc.______________________ A .• __

'TopLevel\T·)pLevel\Cc'reS051\IR_Sel' is a s,:herr,atic.

Bidirectional connector ( 2 tits) \o,'i th n21ril02 lacY.'Bidirectional connector ( bi ts) with nZ1:n~ lRch"Bidirectional connector ( 8 bits) with n.::ame IR i 'Bidirection.:ll connector (10 bits) with na.me . IRo'========================================~====

'TopLevel\TopLevel\Core8051\IR_Sel\Clr_op' is an operator.

This operator has 1 function.The default function is 'Clear_1R'.


Output connector

2 bits) with name 'lack'3 bits) with name 'JR'3 bits) with name 'out'

Text for function 'Clear_IR' of 'TopLevel\T.)pLevel\Core8051\IR_Sel\Clr_op':- - - - - - - - - - - - - - - - - - - - - -v - - - - - - - - - - - - - - - - - - - - --"Reset instruction code."out : = IR \/ (l zeroes, Jack).______________________ A _

============================================='TopLevel\TopLevel\Core8051\IR_Sel\IRcode' is a register.

This register is 2 bits wide and is c0ntrolled by an unnamed control input.The default function is 'load'.This register is loaded with value 0 following system reset.

- 72 -


The value loaded for the 'reset' comm3nd is O.

Control specification:---------~------------v----------------------

"Clear register while loading new instruction code."%001 reset.______________________ A _

'TopLevel\TopLevel\Core8051\IR_Sel\IRop' is an operator.


Enhanced 8051 Core


Output connectorOutput connector

( 2 bits) with name . in ~

( 8 bits) with name ' IRi'(10 bits) with narno? ' IRo'( 2 bits) with name 'out'

Text for function 'First' of 'TopLevel\TopLevel\Core8051\IR_Sel\IRop':----------------------v-----~----------------

"First instruction cycle."IRo := 1 zeroes, lones, IRi.out := 1 zeroes, 1 ones.______________________ A _

Text for function 'NOP' of 'TopLevel\TopLevel\Core8051\IR_Sel\IRop':----------------------v-----------------------No instruction cycle.-IRo := 2 zeroes, IRi.out :-::; 2 zeroes.______________________ A _

Text for function 'N·)rrn.=.I' of '~'0rLevel\T01~Lev021\C0re8051\!R_Sel\IRop':

- - - - - - - - - - - - - - - - - - - - - -v- - - - - - - - - - - - - - - - - - - - --·Continue instructi0n c0d~_·

IRo := in, IRi.out := in.______________________ A _

Text for function 'Second' of ''ropLevel\Tq"Level\Core3051\IR_Sel\IRop':----------------------v----------------------"Second instruction cycle."IRo : = lones, 1 zeroes, IRi.out := lones, 1 zeroes.______________________ A _

Text for function 'Third' of 'TopLevel \T.~pl,evel\Core8051 \IR_Sel \IRop':----------------------v----------------------"Third instruction cycle."IRo := 2 ones, IRi.out :::: 2 ones_---------------------- A ----------------------============================================='TopLevel\TopLevel\Core8051\PCUnit' is a sch~matic_

Bidirectional connector (25 bits) with name 'ADDRo'Bidirectional connector ( 8 loits) with name 'Ai'Bidirectional connector ( 1 loit ) with name 'CTRL'Bidirectional connector ( 8 bits) with name 'Data'Bidirectional connector (24 bits) with name 'DP'Bidirectional connector ( 2 bits) with name ' lack'Bidirectional connector ( 8 bits) with name ' 1M'Bidirectional connector (10 bits) with n.a.me ' IR'Bidirectional connector ( 3 bits) with name ' Ireq'Bidirectional connector ( 1 loit ) with name 'Jtst'Bidirectional connector ( 8 bits) ... ith name 'RAMDATi'Bidirectional connector ( 8 bits) with DaITte ' ReI'Bidirectional connector ( 1 bit ) wi th namo? 'RS'Bidirectional conn·?ctor ( 2 bits) with nanl-:? 'WRo'============================================='TcpLeve 1\ TopLevel \CoreS051 \PCu:, i t \CTRLop' is an operator.



Control specification:----------------------v----------------------"Select last cycle program counter control function."%0100010000, ·JBC bit,rel"

- 73 -


%0100100000, "JB bit,reI"%0100110000, "JNB bit, reI"%0101000000, "JC reI"%0101010000, "JNC reI"%0101100000, "JZ reI"%0101110000, "JNZ reI"%0110000000, "SJMP reI"%01101101xx, "CJNE"%0110111xxx, "CJNE"%0111010101, "DJNZ dir,re1"%0111011xxx Re1Jmp. "DJNZ Rn,re1"%0110010000, "MOY DPTR first byte"%1010010000, "MOY DPTR second byte"%0111000000, "PUSH dir"%1011000000, "PUSH dir'%0110x00100, "DIY AB and MUL AB"%0110000101, "MOY dir,dir first cycle"%011000011x, "MOY dir,@Ri first. cycle"%0110001xxx, "MOY dir, Rn first cycle'%011010011x, "MOY @Ri,dir first cycle"%0110101xxx NOP. "MOY Rn,dir first. cycle"______________________ A _

Input connect.or bit with naIfI':? 'CTRLi'Output connector bit with narrloC . CTRLc·'

Input connector bit with n.=tTTlo? 'Jtsti'Output C0nnector bit wi::.h nacn-a 'Jtst0'

Text for functi0n 'Nor' of 'T0pLevel\TopLevel\Cc·re80S1\PCunit\CTRLOp':----------------------v----------------------"Suppress last cycle signal."CTRLo := 1 zeroes.Jtsto := 1 zeroes.______________________ A _

Text. for function 'Normal' of 'Tc·.'L,?vel\TopLevel\C0re80S1\PCunit\CTRLop':----------------------v----------------------"Detect last cycle signal and don't jump relative."Jtsto := 1 zeroes,CTRLo : = CTRLi,______________________ A _

Text for function 'RelJmp' of 'TopLeve1\TopLevel\Core80S1\PCunit\CTRLop':----------------------v----------------------"Detect last cycle signal and jump relative conditionally."Jtsto ,- CTRLi if 0: 1 zeroes

if 1 : Jtsti.CTRLo ,- CTRLi.

'TopLevel\TopLevel\Cc·re60S1\rCunit.\J' is a register.

This register is 1 bit wide.The default function is 'load',This register is 10aded with value 0 fo,llowing system reset.

The valua l~aded for th~ 'reset' co~mand is O.

'TopLevel \ TopLeve 1\CoreSOSl \FCun i t \ Jao:y.·:,p' is an 0perator,

This operator has 2 functi0ns.The default function is 'Iacy,'.

Enhanced 8051 Core

Input connectorOutput connector

2 bits) with name' lacki'2 bits) with name 'lacko'

Text for function 'Jack' of 'TopLevel\TopLeve1\Core80S1\PCunit\lackop':----------------------v----------------------"Acknowledge requested interrupt."Jacko := Iacki.______________________ A _

Text for function 'RETJ' of 'TopLeve1\TopLeve1\Core80S1\PCunit\Iackop':----------------------v----------------------"End of interrupt."Iacko := lones, 1 zeroes.______________________ A _

============================================='TopLeve1\TopLeve1\Core80S1\ycunit\Jno' is a register.

This register is 3 bits wide and is controlled by an unnamed control input,The default function is 'load',

- 74 -


This register is loaded with value 7 following system reset.


Control specification:----------------------v----------------------"Hold interrupt vector if interrupt request is accepted.'%01 hold. "Interrupt handling"______________________ A _

'TopLevel\TopLevel\Core8051\PCunit\INTR' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'INTR'.

Enhanced 8051 Core

Control connector ( bits) without a name

Control specification:----------------------v----------------------'Detect interrupt request."%111 Normal.______________________ A _

Input connectorOUtput connectorOUtput connector

bit) with na~e 'CTRLi'bit) with name 'CTRLo'

2 bits) with nam~ 'lack'

Text for function 'lNTR' of 'TopLevel\TopL.?vel\Core8051\PCunit\INTR':----------------------v----------------------"Interrupt handling if last cycle signal present."CTRLo := 1 zeroes.lack := CTRLi if0: 2 Zeroes

ifl: 1 zeroes, 1 ones.______________________ A _

Text for function 'Normal' of 'TopLevel\TopLevel\Core8051\PCunit\INTR':----------------------v-----------------------No interrupt request.-CTRLo : = CTRI i.lack := 2 zeroes.______________________ A _

'TopLevel\TopLevel\Core8051\PCunit\Iop' is an operator.

This operator has 2 functions and is (;·:,.ntrolled by an unnamed control input.The de tau 1t funct ion i s 'lIo~rrr,a l' .

Control connector ( ~ bits) without a 113rne

Control specification:----------------------v----------------------·Set register I for stack state RI3chine.·(0)%1 INTR.______________________ A _

Input connector ( 1 bit) with namQ 'Ii'Output connector ( 1 bit) with name '10'

Text for funct ion' INTR' of 'TopLevel \TopLevel \C,~re8051\PCUnit \Iop':----------------------v----------------------"Interrupt handling."10 := 1 ones.______________________ A _

Text for function 'Norrnal' of 'TopLevel\TopLevel\Core8051\PCunit\Iop':----------------------v----------------------"Continue routine."10 := Ii.______________________ A _

'TopLevel\TopLevel\Core8051\PCunit\JUMP' is an operator.



Concrol specification:----------------------v----------------------"Detect relative jump."%l REL.______________________ A _

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Input connector (24 bits) with nam~ 'PC'Output connector (24 bits) with narr,.;, 'PCe,'

Input connector (24 bits) with name 'REL'

Text for function 'PC' of 'TopLevel\TopLevel\Core8051\PCunit\JUMP':----------------------v----------------------"Normal throughput program counter,"PCo := PC,----------------------~----------------------

Text for funct ion 'REV of 'TopLeve 1\T~,pLevel \CoreS051 \PCun i t \JUMP' :----------------------v----------------------·Relat i ve jwnp."PCo := REL.______________________ A _

'TopLevel\TopLevel\Core8051\PCunit\PC' is a register.

This register is 24 bits wide.The default function is 'load'.This register is loaded with value 0 following system reset,


'TopLevel\TopLevel\Core8051\PCunit\FCadgen' is an operator.

This operator has 3 functions.The default function is 'PROGRAM'.

Output connector (25 bits) wit.h na.tTI~ , ADD,,'Input conneo:t':>r (24 bits) with n3.r~l-= 'Dr'Input C0nne·:t·:;.r (24 bits) wi th n:1.fLL".=- 'FCi'Input connector ( i3 bits) with r.~~rne ' R,\M'

Text for function 'DATA_DP' c,f 'T,jpL-2vel\Te,p!.kv,,,1\Core3051\PCunit\PCadgen':----------------------v----------------------"MOVX DPTR·ADDR := 1 ones, DP,

Text for function 'DATA_RAM' of 'T,:,pLeV-21\Tq:>Level\Cor"S051\PCUnit\PCadgen':----------------------v----------------------·External data memory,·ADDR := 1 ones, 16 zeroes, RAM.______________________ A _

Text for function 'PROGRAM' of 'TopLevel\Tc-pL",vel\Core8051\PCunit\PCadgen':----------------------v---------------------·"External program memor/,·ADDR := 1 zeroes, pci,______________________ A _

'TopLevel\TopLeve1\Core8051\PCunit\PCbuf' is a register,

This register is 24 bits wid",.The default function is 'load'.This register is loaded with value 0 following system reset.

The value loaded for the 'reset' command is 0,

'TopLevel\TopLevel\Core8051\PCunit\FCbufop' is an operator.

This operator has 8 functions.The default function is 'Normal',

Input connector ( 8 bits) with name ' 1M'Input connector (24 bits) with name ' in'Input connect.or ( 3 bit 5) with name ' Inc·'

Output connector (24 bits) with name 'out'Output connector (24 bits) with n3rrl€ 'rco'

Input connector ( 8 bits) with name ' R!\:-!'

Text for function 'INTR' of 'TopLevel\TopLevel\Core8051\PCunit\PCbufop':----------------------v----------------------"Store interrupt address.·out := 18 zeroes, Ino, 1 zeroes, 2 ones.______________________ A _

Text for function 'Normal' ot 'TopLevel\TopLevel\Core8051\PCunit\PCbufop':----------------------v----------------------"Hold old register contents,·

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Enhanced 8051 Core


PCo := in.out := in.______________________ A _

Texc for function 'PCEim' of 'TopL~v~1\TopLev~I\Core80S1\PCUnit\PCbufop':

----------------------v----------------------·Store chird byte of PC in PCbuf,·ouc := IH, (in from: Q to: 1S).PCo := IH. (in from: 0 to: 1S).----------------------~-----------._---------

Text for funccion 'PCEram' of 'TopLevel\T·)pL",vel\Core80S1\PCunit\PCbufop':----------------~-----v----------------------

·Score third byte of PC in PCbuf.·out := RAM, (in from: 0 to: 1S).______________________ A _

Text for function 'PCHim' of 'TopLevel\TopLevel\Core80S1\PCunic\PCbufop':----------------------v----------------------·Score new second byte of PC in PCbuf.·out := (in from: 16 co: 23), IH, (in from: 0 to: 7).PCo := (in from: 16 to: 23), IH, (in fre-m: 0 to: 7).______________________ A _

Text for function 'PCHram' of 'TopL",vel\TopLevel\Cor",80S1\PCunit\PCbufop':----------------------v----------------------·Score new second byte of PC in PCbuf.·out := (in from: 16 to: 23), RAM, (in fre-ro: 0 co: 7).______________________ A _

Text for function 'PCLim' of 'TorLevel\T.)pLevel\Core30S1\PCunit\PCbufop':----------------------v----------------------·Store new first byte of PC in PCbuL·out := (in from: 8 to: 23), !M,PCo := (in from: 8 to: 23), !l~.______________________ A _

Text for function 'PCLram' oi 'TorLevel\';'-:opLevel\Core80S1\PCunit\PCbufop':- - - - - - - - - - - - - - - - - - - - - -v- - - - - - - - - - - - - - - - - - - - --·Store new first byte of PC in fCbuf.·out: = (in frum: 8 to: 23), F.AH.PCo : = (i n from: 8 t·): 23), F.A~.

'TopLeve 1\TopLeve I \C·:·re80S1 \FCun i t \rCdat·)p' is an operator.

This operator has 3 functions.The defaulc function is 'PCL'.

Output connector ( 8 bits) with name 'fCdat'Input connector (24 bits) with name 'fCi'

Text for function 'PCE' of 'TopLevel\T0pLevel\Core80S1\PCunic\PCdatop':----------------------v----------------------·Output third byte of PC.·PCdat : = pci from: 16 to: 23.

Text for function 'PCH' of 'TopLevel\TopLevel\Core8051\PCunic\PCdatop':----------------------v----------------------·Output second byte of PC.·PCdat := PCi from: 8 to: 1S.______________________ A _

Text for function 'PCL' of 'TopLevel\TopLevel\Core80S1\PCunit\PCdatop':----------------------v----------------------·Output first byte of PC.·PCdat := pci from: 0 to: 7.

'TopLevel\TopLevel\Core80S1\PCunit\PCgen' is an operator.

This operator has 6 functions.The default function is 'Nornal'.

Input conne,:::tor ( 8 bits) with narh8 ' A'Input connector (24 bits) \-dth nam~ , LoP'Input c·:>nnector (10 bit.s) with na~~o2' ' IR'Input cc>nnector (24 bits) with n.=trrlC 'rCbuf'Input connect.or (24 bitsl with nam~ 'PCi'

Output connector (24 bits) with narne 'PCo'

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Enhanced 8051 Core


Text for function 'ABS' of 'TopLevel\TopLevel\Core8051\PCunit\PCgen':----------------------v----------------------"Absolute call or jump."PCo := (pci from: 11 to: 23), (IR from: 5 to: 7), (PCbuf from: 0 to: 7).______________________ A _

Text for function 'GLOBAL' of 'TopLevel\TopLevel\Core8051\PCunit\PCgen':----------------------v----------------------"Global call or jump.·PCo : = PCbuf.______________________ A _

Text for function 'LONG' of 'TopLevel\TopLevel\Core8051\PCunit\PCgen':----------------------v----------------------·Long call or jump.·PCo := (PCi from: 16 to: 23), (PCbuf from: 0 to: 15).______________________ A _

Text for function 'MOVC_DP' of 'TopLevel\TopLevel\Core80SI\PCunit\PCgen':----------------------v----------------------"MOVC A,@A+DPTR or JMP @A+DPTR·PCo := (16 zeroes, A) + DP.______________________ A _

Text for function 'MOVC_PC' of 'TopLevel\TopLevel\Core80S1\PCunit\PCgen':----------------------v----------------------"MOVC A,@A+PC"PCo := (16 zeroes, A) + pci.----------------------,.,----------------------

Text for funct ion 'Norma l' of 'Top LeV;? 1\ TqoL;,ve 1\Core3051 \PCun i t \PCgen' :----------------------v-----------------------Read instruction code.-PCo : = PCi.

'TopLevel\TopLevel\Core8051\PCunit\PCinc' is an operator.

This operator has 2 funct ions an(] is cc·ntroll;?d by an unnamed control input.The default function is 'Normal'.

Enhanced 8051 Core


Control specification:----------------------v-----------------------Select program counter increment.-%! AddOne.______________________ A _

Input connector (24 bits) with name 'in'OUtput connector (24 bits) with name 'out'

Text for function 'AddOne' of 'TopLevel\TopLevel\Core8051\PCunit\PCinc':----------------------v-----------------------Increment program counter before storing.-out := in + (23 zeroes, 1 ones).______________________ A _

Text for function 'Normal' of 'Tc·pLevel\T-:·pr,evel\Core8051\PCunit\PCinc' :----------------------v----------------------"Throughput program counter."out := in.______________________ A _

'TopLevel\TopLevel\Core8051\P0Jnit\PCop' is an operator.

This operator has 2 functions.The default function is 'CTRL'.


bitbit

with name 'CTRL'with name 'PC'

Text for function 'CTRL' of 'TopLevel\TopLevel\Core8051\PCunit\PCop':----------------------v----------------------"Control program counter."PC := CTRL.______________________ A _

Text for function 'INC' of '~opLevel\TopLevel\Core8051\PCunit\PCop':

----------------------v----------------------·Load and increment program count;?r.·PC := I ones.

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______________________ A _

'TopLevel\TopLevel\Core80S1\PCunit\RELop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'FORWARD'.


Control specification:----------------------v----------------------"Detect forward or backward jump."(7)%0 FORWARD.%1 BACKWARD.______________________ A _

Input connector (24 bits) with name 'pci'Output connector (24 bits) with name 'PCo'

Input connector ( 8 bits) with name 'REL'

Text for function 'BACKWARD' of 'TopLevel\TopLevel\Core80S1\PCunit\RELop':----------------------v----------------------"Backward relative jump."PCo := PCi + (16 ones, ReI).----------------------,----------------------

Text for function 'FORWARD' of 'TopLevel\TopLevel\Core8051\PCunit\RELop':----------------------v----------------------"Forward relative jump."PCo : = rci + (16 zere'es, ReI).

'TopLevel\TopLevel\CoreBOS1\PCunit\WR' is an operator.


Enhanced 8051 Core


1 bit) with name 'CTRL'2 bits) with name 'WRo'

Text for function 'Normal' of 'TopLevel\TopLevel\Core80S1\PCunit\WR':----------------------v----------------------"Read new instruction during last cycle."WRo := 1 zeroes, CTRL.

Text for funct ion 'Read' 0 f 'T0pL'2ve 1 \ Tor-Lev." I \Core80S1 \ FCun i t \WR' :----------------------v----------------------"Read control signal."WRo := 1 zeroes, 1 ones.

Tezt for funct ion 'Writ'2' of 'Tq'Le"J021 \T-:-pLev021 \Core80S1 \PCunit \WR':----------------------v----------------------·Write concrol signal.WRo := lones, 1 zeroes.

'TopLevel\TopLevel\Core80S1\RAM_SEL' is a schematic.

Bidirectional connector (10 bits) with name ' IR'Bidirectional connector ( 8 bits) with name 'pswi'Bidirectional connector ( 8 bits) with name 'RAMADDR'Bidirectional connector ( 3 bits) with narn.e 'RAMIWR'Bidirectional connector (10 bits) with narrlC 'SFR'Bidirectional connector (16 bits) with name 'SPaddr'Bidirectional connector ( 2 bits) with name 'SPWR'============================================='TopLevel\TopLevel\Core80S1\RAM_SEL\IWR_SEL' is an operator.

This operator has 3 functions and is controlled by an unnamed control input.The default function is 'Stack'.


Control specification:----------------------v----------------------·Select RAM access mode."%0100010000, "JBC bit,rel"%0100100000, "JB bit, reI"%0100110000, "JNB bit,rel"

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%0110100000, "ORL C, /bit"%0110110000, "ANL C, /bit"%0111000000, "PUSH dir"%0111010000, "POP dir"%0101000010, "ORL dir, A"%0101010010, "ANL dir,A"%0101100010, "XRL dir, A"%0101110010, "ORL C,bit"%0110000010, "ANL C, bit"%0110010010, "MOV bit, C"%0110100010, "MOV C. bit"%0110110010, "CPL bit"%0111000010, "CLR bit"%0111010010, "SETB bit"%0101000011. "ORL dir, Mdata"%0101010011. "ANL dir, Mdata"%0101100011, "XRL dir,Mdata"%0100000101, "INC dir"%0100010101, "DEC dir"%0100100101, "ADD A,dir"%0100110101. "ADDC A, dir"%0101000101. "ORL A, dir"%0101010101, "ANL A,dir"%0101100101, "XRL A,dir"%0101110101. "MOV dir, Mdata"%0110000101. "MOV dir-dir first cy.::le"%1010000101. "MOV dir,dir sec~,nd cycle"%0110010101. "SUBB A,dir"%0110110101. "CJNE A,dir, rei"%0111000101, "XCH A,dir"%0111010101, "DJNZ dir,rel"%0111100101. "MOV A,dir"%0111110101. "MOV dir,A"%101000011=<, "MOV dir,@Ri se,:,:-nrl cycle"%011010011x, "MOV @RLdir first cycle"%1010001xx:<, "MOV dir,Rn s'2c0nd cycle"%0110101:<=<x Direct. "MOV Rn,dir first cycle"%011110001:<, "MOVX A, @Ri"%011111001x, "MOVX @Ri,A"%010000011:<, "INC @Ri"%010001011x, "DEC @Ri"%010010011x, "ADD A,@Ri"%010011011x, "ADDC A,@Ri"%010100011x, "ORL A,@Ri"%010101011x, "NIL A,@Ri"%010110011:<, "XRL A,@Ri"%010111011x, "MOV @Ri,Mdata"%011000011x, "MOV dir,@Ei first cycle"%011001011x, "SUBB A,@Ri"%101010011:<, "MOV @Ri, dir s"c,:'nd cycle"%011011011x, "CJNE @Ri,Mdata,rel"%011100011x, "XCH A,@Ri"%011101011:<, "XCHD A,@Ri"%011110011=<, "MOV A,11Ri"%011111011:<, "MOV @Ri,A"%0100001xxx, "INC Rn"%0100011xxx, "DEC Rn"%0100101xxx, "ADD A,Rn"%0100111xxx, "ADDC A,Rn"%0101001xxx, "ORL A,Rn"%0101011xxx, "ANL A, Rn"%0101101xxx, "XRL A, Rn"%0101111xxx, "MOV Rn,#data"%0110001xxx, "MOV dir,Rn first cycle"%0110011xxx, "SUBS A,Rn"%1010101xxx, "MOV Rn,dir second cycle"%0110111xxx, "CJNE Rn, Mdata, rei"%0111001xxx, "XCH A,Rn"%0111011xxx, "DJNZ Rn, reI"%0111101xxx, "MOV A,Rn"%OIIIl11xxx REG, "MOV Rn,A"---- --- --- - -- --- --- --- , ----------------------

Output connector 8 bits) with narTle ' RAMADDR'Output connector 3 bits) with name 'RAMlWR'

Input connector 8 bits) with name 'REGADDR'Input connector ( 3 bits) with name 'REGIWR'Input connector (10 bi t s) with name 'SFR'Input connector (16 bits) with nam-a 'SF'"ddr'Input connector ( 2 bits) with n3mo? ' S!'~IR'

Text for function 'Direct' of 'TopLeveI\T01'LeveI\Core8051\RAM_SEL\IWR_SEL':

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Enhanced 8051 Core

Section of Digital Information Systems Enhanced 805 I Core

----------------------v----------------------'Direct addressing.'RAMIWR:= (1 zeroes, «SFRat: 8) /\ (SFRat: 7) not), «SFRat: 9) /\ (SFRat: 7) not».RAMADDR := SFR from: 0 to: 7.______________________ A _

Text for function 'REG' of 'TopLevel\TopLevel\Core8051\RAM_SEL\IWR_SEL':----------------------v----------------------'Register addressing,'RAMIWR := REGIWR.RAMADDR := REGADDR.______________________ A _

(1 zeroes, SPWR)(3 zeroes),

9) \/

11) \/13) \/15» if0:

if1 :

at:

at:at:

at:(Sl'addr(SPaddr(Sl'addr(Sf'addr

Text for function 'Stack' of 'TopLevel\TopLevel\Core8051\RAM_SEL\IWR_SEL':----------------------v----------------------'Stack operation.'RAMIWR := «SPaddr at: 8) \/

(SPaddr at: 10) \/(SPaddr at: 12) \/(SPaddr at: 14) \/

RAMADDR := SPaddr from: 0 to: 7,___ - - /'1.- _

'TopLevel \TopLeve1\Core3051 \RAM_SEL\REG_SEL' is an operator,

This operator has 5 functions and is controlled by an unnamed control input.The default function is 'NOP',

Control connector (10 bits) without a na~e

Control specification:----------------------v----------------------'Select register addressing control,'%010010011x, 'ADD A.@Ri·%010011011x, •ADDC A, (lRi'%010100011x, 'ORL A,@Ri'%OlOlOlOl1x, 'ANL A, (lRi'%010110011x, 'XRL A,@Ri"%OllOOOOllx, 'MOV dir, @Ri'%011001011x. 'SUBB A,@Ri'%01l011011x, 'CJNE @Ri, Kdata, reI'%011110011x, 'MOV A,@Ri'%0100101xxx, "ADD A, Rn'%0100111xxx, 'ADDC A, Rn'%010100 lxxx, 'ORL A, Rn'%0101011xxx, 'ANL A, Rn'%0101101xxx, 'XRL A,Rn'%0110001xxx, 'MOV dir,Rn"%0110011xxx, "SUBB A, Rn"%0110111xxx, "CJNE Rn,Kdata,rel"%0111101xxx Read. 'MOV A,Rn"%011110001x, "MOV:': A,@Ri'%011111001x MOVX, "MOV:, @Ri. A"%010111011x, 'MOV @Ri.KrJaU"%101010011x, 'MOV @Ri,dir'%011111011x, 'MOV 8Ri,A"%0101111xxx, 'MOV Rn, Kdata'%101 0101xxx, • MOV Rn, d i r'%0111111xxx Wrt. 'MOV Rn,A"%010000011x, • INC @Ri'%010001011x, 'DEC @Ri"%011100011x, 'XCH A,@Ri'%011101011x, 'XCHD A,@Ri'%0100001xxx, 'INC Rn"%OlOOOllxxx, 'DEC Rn'%0111001xxx, "XCH A,Rn'%0111011xxx Modify. 'DJNZ Rn,rel'______________________ A _

Input connector (10 bits) with name ' IR'Input connector ( 8 bits) with name 'pswi'

Output connector ( 8 bits) with name 'RAMADDR'Output connector ( 3 bits) with name 'RAMIWR'

Text for function 'Modify' of 'TopLevel\TopLevel\Core8051\RAM_SEL\REG_SEL':----------------------v----------------------'Modify register."RAMADDR := 3 zeroes, (pswi from: 3 to: 4), «IR at: 3) itO: (2 zeroes, (IR at: 0»

it'l: ( I R from: 0 to: 2».RAMIWR := (IR at: 3) not, 2 ones.______________________ A _

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Scclion of DigilaI Infonnalion Syslcms

Text for function 'MOVX' of 'T·~pL'2v'21\TopLevel\Core8051\RAM_SEL\REG_SEL':

----------------------v----------------------·Read indirect address."RAMIWR := 2 zeroes, 1 ones.RAMADDR := 3 zeroes, (PSwi from: 3 to: 4), 2 zeroes, (IR at: 0).______________________ A _

Text for function 'NOP' of 'TopLevel\TopLevel\Core8051\RAM_SEL\REG_SEL':----------------------v----------------------·No register addressing."RAMIWR := 3 zeroes.______________________ A _

Text for function 'Read' of 'TopL'2vel \T~,pLevel\Core8051 \RAM_SEL\REG_SEL':----------------------v----------------------"Read register.·RAMADDR := 3 zeroes, (PSWi from: 3 to: 4), «IR at: 3) itO: (2 zeroes, (IR at: 0»

ifl: (IR from: 0 to: 2».RAMIWR := (IR at: 3) not, 1 zeroes, 1 ones.______________________ A _

Text for function 'Wrt' of 'TopLevel\TopLevel\Core8051\RAM_SEL\REG_SEL':----------------------v----------------------·Write register.-RAMADDR := 3 zeroes, (PSWI from: 3 to: 4), «IR at: 3) if0: (2 zeroes, (IR at: 0»

if 1: (IR from: 0 to: 2».RAMIWR := (IR at: 3) not, lones, 1 zero'2S.______________________ A _

'TopLevel\TopLevel\Core805l\RAMunit' is a s.:h.:?m3t"ic.

Enhanced 805 I Core

Designer comments:-------------- --- ---- -v----··-- - --- -- - --- - _.--

RA~ address 0-31 selects as~·~·:hr0nc·us rQ~d and write RAM.RAM address 32-255 s~la·:~s h$A RA~ with ~yn~tlr·~n0l1s re~d.

RAMDATi is RAM data input bus.RAMDATo is RAM data output ]:.us.RAMADDR is RAM addr~ss bus.RAMIWR is RAM re3d-write .:0ntr~·1 bus, wh'2l"e I (Dit 2) indic:ates indirect addressing mode.RAMDV is RAm data v31id flags bus.Data valid read flag (bit. 0) indicat.o?!=i <iati:! can be read frclm cin.r~ output bus.Data valid write flag (bit 11 indi·:ates (bt3 fr·:·m the data input bus will be writeen in RAM.______________________ A _

Bidirectional connector ( B bits) ;,'i th n3.me 'ALUc·ut l'Bidirectional connector ( 8 bits) with name 'DirDat'Bidirectional connector (10 bits) with name ' 1R'Bidirectional connector ( 8 bits) with name 'PCd3t'Bidirectional connector ( 8 bits) with rla.mo? 'RAM':IDDR'Bidirectional connector ( 8 bits) with name 'RAMDAT'Bidirectional connector ( 2 bits) with name 'RAMDV'Bidirectional connector ( 3 bits) with name 'RA~U;~R'

============================================='TopLeve 1\ TopLeve 1\Core8051 \RMlun i t \ADDRgen' is an operator,

This operator has 4 functions and is controlled by an unnamed control input.The default function is 'REGRAM'.


Control specification:----------------------v----------------------"Select RAM addressing mode."(5 •• 7)$0 REGRAM.$1,$3,$5,$7 RAMI.$2,$6 RAM2.$4 RAM3.______________________ A _

Input connector S bits) with name 'ADDR'Output connector 8 bits; with na.me ' H}>.DDR'Output connector 2 bitsl with name , HWm0d'Output connector 2 bits) with name 'HWR'Output connector 7 bits) with n.:sme 'LWR3ddr'

Input connector 2 bits) with name 'WR'

Text for function 'RMIl' of 'TopLevel\T('pL'2vel\Cor'28051\RAMunit\ADDRgen':----------------------v----------------------"Invert bit 5 of address for synchronous read RAM."HWR := «WR at: 1) 1\ (WR at: 0) not), (WR at: 0).HWmod := «WR at: 1) 1\ (WR at: 0», 1 zeroes.

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LWRaddr : = 2 zeroes, (ADDR from: 0 to: 4).HADDR := (ADDR from: 6 to: 7), (ADDR at: 5) not, (ADDR from: 0 to: 4),----------------------~----------------------

Text for function 'RAM2' of 'Te'I'Level\Te'I'Level\Core80S1\RAMunit\ADDRgen':----------------------v----------------------"Invert bit 5 and 6 for synchrounous read RAM,"HWR := «WR at: 1) /\ (WR at: 0) not), (WR at: 0).HWmod:= «WRat: 1) /\ (WRat: 0»,1 z,ne,es,LWRaddr : = 2 zeroes, (ADDR from: (J t·): 4).HADDR := (ADDR at: 7), (ADDR fruIn: 5 to: 6) not, (ADDR from: 0 to: 4),----------------------~----------------------

Text for function 'RAM3' of 'TopLevel\TopLevel\Core80S1\RAMunit\ADDRgen':----------------------v----------------------"Invert three highest address bits for synchrounous read RAM."HWR:= «WR at: 1) /\ (WR at: 0) not), (WR at: 0).HWmod := «WR at: 1) /\ (WR at: 0», 1 zeroes.LWRaddr := 2 zeroes, (ADDR from: 0 to: 4).HADDR := (ADDR from: 5 to: 7) not, (ADDR froIn; 0 to: 4).----------------------~----------------------

Text for function 'REGRAM' of 'Te·pLevel\T,~l'Le'Jol\Core8051\RAMunit\ADDRgen':

----------------------v----------------------"Asynchrones RAM,"LWRaddr := WR, (ADDR from: 0 to: 4).HWR := 2 zeroes.HWmod := 2 zeroes.______________________ A _

'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAM' is a schematic.

Bidirectional connectorBidirectional connectorBidirectional connector

7 bits) with name 'LWRaddr'8 bits) with name 'rd'S bits) with nam~ '~d'

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\BORO' is a register.

This register is 8 bits wi,,:le and is ~c'ntr,:,llo?d by an unnamed control input.The default function is 'hold'.This register is loaded with unkn0wn valu~s after a system reset.

The value loaded for the 'r-?set' cc'mm.=tnd is O.

Control specification:----------------------v----------------------%0100000 enable. "Read"%1000000 load. "Write"%1100000 load; enable. "Modify"______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\BOR1' is a register.

This register is 8 bits wide and is contr·~lled by an unnamed control input.The default function is 'hold'.This register is loaded with unknown values after a system reset.

The va 1ue loaded for the 'reset' ce,mmand is O.


'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAM\BOR2' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with unknown values after a system reset.


Control specification:----------------------v----------------------%0100010 enable. "Read"%1000010 load. "Write%1100010 load; enable. "Modify"______________________ A _

=~========~==================================

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'TopLevel\TopLevel\Co~e80S1\RAMunit\ASALRAM\BOR3' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This registe~ is loaded with unknown values after a system reset.


Control specification:----------------------v----------------------%0100011 enable. 'Read"%1000011 load. "Write'%1100011 load; enable. 'Modify'______________________ A _

============================================='TopLevel\TopLevel\Core80S1\RAMunit\ASALRAM\BOR4' is a registe~.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with unY~own values after a system reset,


Control specification:----------------------v----------------------%0100100 enable. "Read"%1000100 load. "Write"%1100100 load; enabl·? "M·e·dif.,."______________________ A. _

. TopLevel \ T'::-FL~\!e 1 \C·.:,re8051 \F'J\~urL i t \ASr\[,R. ..,~ \EORS' is (i reg ister.

This registo?r is 8 bits wick.' and is ·:':-ntr...:·l1-=-d by an unnarlled control input.The default function is 'h01d'.This register is loaded wit~ unknown values after a system reset.

The valuB loaded for the ~reset~ c0m~and is o.

Control sp~cification:

----------------------v----------------------%0100101 enable. 'Read"%1000101 load. "Write'%1100101 load; enable. 'M'~dify"

----------------------~----------------------

'TopLevel\T0pLeve1\Core80S1\RAMunit\ASALRAM\BOR6' is a registe~.

This register is 8 bits wide and is controll",d by an unnarr.ed control input.The default function is 'hold'.This register is loaded with unknown values after a system reset.


Control specification:----------------------v----------------------%0100110 enable. 'Read"%1000110 load. 'write"%1100110 load; enable. "Modify'----------------------~----------------------

'TopLevel\TopLevel\Co~e80S1\RAMunit\ASALRAM\BOR7'is a ~egister.

This regist~r is 8 bits wicl~ and is c·jr,trc,lled by an unnamed control input.The default function is 'hold'.This register is lc'aded with unr.n·:'wn v ..~luo?s after a syst~m reso?t.

The value loaded for the ~ reset ~ ':'0Irlrnand is O.

Cont~ol specification:----------------------v----------------------%0100111 e~able. 'Read'%1000111 load. "Write"%1100111 load; enable. "Modify'----------------------~----------------------

'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAM\BIRO' is a register.

This register is 8 bits wide and is cCor.tr~·il·::cl by an unnamed control input.The default function is 'hold'.This register is loaded with unkn~~n values after a system reset.

- 84 -

Enhanced 8051 Core




'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAM\BlRl' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with unkn,~wn valu'?s after a system reset.

The value loaded for the' reso=t' c·.:,mmand is O.

Control specification:----------------------v----------------------%0101001 enable. "Read"%1001001 load. "Write"%1101001 load; enable. "M,:>dify"----------------------~----------------------

'TopLevel\Tc,pLevel\Core80S1\R."Munit\ASALRAI1\B1R:' is a register.

This register is 8 bits wide and is cont rc,lled by an unnamed control input.The default function is 'hold'.This register is loaded with unJ.:n·:"wn valu~s after a system reset.

The value loaded for the' res-:t' c·:,.r;,\;r\.3nd is O.


'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAI1\B1R3' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with Uny.n0wn values after a syst€m reset.

The value loaded for the' res-:-t.' c':'f!l~,;tfId is O.

Control specification:- - - - - - - - - - - - - - - - - - - - - - OJ __ .. _

%0101011 enable. "Read"%1001011 load. "Write"%1101011 load; enable. "Hodify"

'TopLevel \T'~pLevel\Corei30S1 \F.AMunit \ASALRAM\BIR4' is a register.

This register is 8 bits wide and is controlled by an unnamed c0ntrol input.Th'? default function is 'hold'.This register is loa'Jed with unkn,~wn values after a system reset.



'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAM\B1RS' is a register.

This register is 8 bits wide and is contr,)lled by an unnamed control input.The default function is 'hold'.This register is loaded with unkn,:>wn values after a system reset.


Control specification:----------------------v----------------------%0101101 enable. "Read"%1001101 load. "Write"

- 85 -

Enhanced 8051 Core


%1101101 load; enable. ·Me,diEy·----------------------~----------------------

'TopLevel \TopLevel\Core8051 \RAMunit\ASALRAM\SIR6' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with unY~own values after a system reset.


Control specification:----------------------v----------------------%0101110 enable. "Read·%1001110 load. "Write"%1101110 load; enable. ·Modify·______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\BIR7' is a register.



Control specification:----------------------v----------------------%0101111 enable. "Read"%1001111 luad. "Write"%1101111 load; enable. "Modiiy"____________________ _-"" - - - - - - - - - - - - - - - - - - - - --

'TopLeve 1\TcopLev,,, I \C0re8051 \RMiun i t \.;Sl-.LR.'.H \E2R()' is " reg i ster.

This register is 8 bi.ts wide "nd is ·:ontr,,,lle,l by an unnamed cc·ntrol input.The d~fault function is 'h01~·.

This register is loaded with llnkn0wn valu~s after a syste~ reset.

The value loaded for the' resec.· ':OHlfTland is 0.

Control specification:----------------------v----------------------%0110000 enable. "Read"%1010000 load. "write"%1110000 load; enable. "Modify"----------------------~----------------------

'TopLevel\TopLevel\C",re8051\RAMunit\AS1\LR';I~\S2R1'is a register.

This register is 8 bits wide and is ·:ontr,olled by an unnamed control input.The default function is 'hold'.This register is loaded with unkn,:own values aft~r a system reset.

The value loaded for the 'reset' =ommand is O.

Control specification:----------------------v----------------------%0110001 enable. "Read"%1010001 load. "Write"%1110001 load; enable. "Modify'______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\S2RZ' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with unkn0wn values after a system reset.

The value load02d for the' reset' ·':C·!Tlffi.:tJld is O.

Control specification:----------------------v----------------------%0110010 enable. "Read"%1010010 load. ·Write"%1110010 load; enable. "Modify"______________________ A _

'TopLevel\TopLevel\Core80S1\RAMunit\ASALRAH\B2R3' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.

- 86 -

Enhanced 8051 Core


The default function is 'hold'.This register is loaded with unknown values after a system reset.


Control specification:----------------------v----------------------%0110011 enable. "Read"%1010011 load. "Write"%1110011 load; enable. ·Modify·______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\B2R4' is a register.


The value l'Jaded for the 'reset' command is O.

Control specification:----------------------v----------------------%0110100 enable. "Read·%1010100 load. "Write"%1110100 load; enable. "Modify"______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\B~R5' is a register.

This register is 8 bits wide and is controlled l~ an unnamed control input.The default function is 'hold'.This register is loaded with unknown valu~s after a Syst€ffi r~set.

The value loaded for the ·reset' com~and is O.

Control specification:----------------------v----------------------%0110101 enable. "Read"%1010101 load. "Write·%1110101 load; enable. ·Modi fy·______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\B~R6' is a register.



Control specification:----------------------v----------------------%01101lC' enable. "Read"%1010110 load. "Write·%1110110 load; enable. "Me.dif:i"______________________ A _

'TopLevel\TopLevel\Core8051\Rl-.Munit\AS!ILR;>.M\B2R7' is a register.

This register is 8 bits wide .:md is contr<;)lled by an unnamed control input.The default function is 'hold'.This register is loaded with unknown values after a system reset.

The value loaded for the 'reset' ~ommand is O.

Control specification:---·------------------v-----~----------------

%0110111 enable. "Read·%1010111 load. "Write"%1110111 load; enable. "Modify·----------------------~----------------------

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\B3RO' is a register.




- 87 -

Enhanced 805 I Core


----------------------v----------------------%0111000 enable. ·Read·%1011000 load. ·Write"%1111000 load; enable. "Modi fy·----------------------~----------------------

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\E3Rl' is a register.

This register is 8 bits wide and is contr011~d by an unnamed control input.The default function is 'hold'.This register is loaded witt: unJ.:rl":J1A'n values 3t~er a system reset.


Control specification:----------------------v----------------------%0111001 enable. ·Read·%1011001 load. "Write·%1111001 load; enable. ·Modify·______________________ A _


This register is 8 bits wide and is c0ntr·:,11ed by an unnamed cvnt.rol input.The default function is 'hold'.This register is loaded with unr:.n0v,:n valu~s a:L-2r a syst.em raset.

The value loaded for the 'reset' ·~e·mmand is O.

Control specification:----------------------v----------------------%0111010 enable. "Read"%1011010 load. "Write·%1111010 load; enable. "Modify"______________________ A _

'TopLevel\TopLevel\CoreSOS1\RAMur,it\ASALRAM\B3R3' is a register.

This register is 8 bits wide ancl is c0ntr0ll~d I~ an unnamed control input.The default function is 'h·)lrl·.This register is loaded with un~n0wn valu~s ~it~r a system reset.

The value load-e-d. for the 'l."es·?t· G,:·rnrr,.::tIlC: is O.


----------------------v----------------------%0111011 enable. "Read·%1011011 load. "Write"U111011 load; enable. "He·diry·______________________ A _

'TopLev.eI\TopLevel\Core80S1\RAMunit\ASALRFo.H\B3R4' is a register.

This register is 8 bits wide "'nd is c·:·ntr·:·llerJ bj' ar, unnamed control input.The default function is 'hold'.This register is load'?rJ with uny.n·.)wn valu~s aft~r a system reset.

The value loaded for the 'reset' command is 0.

Control specification:----------------------v----------------------%0111100 enable. ·Read·%1011100 load. ·Write·%1111100 load; enable. "Modify·______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\ASALRAM\B3RS' is a register.

This register is 8 bits wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with unkn·:·wn values after a system reset.

The value loaded for the 'reset' ·~orr,mand is O.

Control sr.~cification:

----------------------v----------------------%0111101 enable. ·Read"%1011101 load. "Writ~"

%1111101 load; en"ble. "H·:·dif:,'"______________________ A _

- 88 -

Enhanced 8051 Core



This register is 8 bits wide and is controlled by an unnamed control input,The default function is 'hold'.This register is loaded with unknown values after a system reset.

The value loaded for the 'reset' ce·mmand is O.

Control specification:----------------------v----------------------'t0111110 enable. 'Read''t1011110 load. 'Write''t1111110 load; enable. 'Modify"______________________ A _




Concrol specification:----------------------v----------------------'tOll1111 enable. 'Read''tl011111 load. 'Write'%1111111 l,~ad: enabl·". "M,:·:Ii ty"---------------------_ .... _---------------------

'TopLevel\TopLevel\Core80S1\RAMunit\BUSIMPL' is a schematic.

Designer comments:----------------------v----------------------This schematic contains a control inputdriven RAM, as it should be inserted ina design before transfer to ASA.

The synthesized result will have the samebehaviour as BUSSIMU, which shc'uld be usedduring simulation of the system.______________________ A _

Bidirectional connectc,r 2 bits) with f16fjle 'c'Bidirectional connector 8 bits) with name 'ra'Bidirectional connect0r 8 bits) with name 'rd'Bidirectional connector 8 bits) with name 'wa'Bidirectional connector 8 bits) with name 'wd'

'TopLevel\TopLevel\Core8051\RAMunit\BUSIM?L\RAM' is a RAM.

This RAM contains 224 words of 8 bits each and is controlled by an unnamed control input.There is no contents file atta·ohed.This RAM is loaded with unknown values after a system reset.

Control specification:----------------------v----------------------%10 Write.'tOl Enable______________________ A _

'TopLeve 1\ TopLeve 1\C·;·re8051 \P.AMur, i t \Busy' is a reg i ster.

This register is 1 bit wide and is controlled by an unnamed control input.The default function is 'hold'.This register is loaded with value 0 following system reset.


Control specification:----------------------v----------------------"RAM busy flag control."'tOO load.%01 reset.%10 reset.'tIl reset.----------------------~----------------------

============================================='TopLevel\TopLevel\Core8051\RAMunit\Busyop' is an operator.

This operator has 2 functions.

- 89 -


The default function is 'Normal'.

Enhanced 8051 Core


2 bits) with nam~ 'ovi'2 bits) with name 'OVo'

Text for function 'Normal' of 'To»Lev~I\T.:.pLev~I\Core8051\RAMunit\Busyop':

----------------------v----------------------'Throughput data valid signal.'DVo := DVi.----------------------~----------------------

Text for function 'RET' of 'TopLevel\TopLevel\Core8051\RAMunit\Busyop':----------------------v----------------------'Continu stack pop action.'DVo := 1 zeroes, 1 ones.______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\DVop' is an operator.


Control connector ( 3 bits) ~!thout a name

Control specification:----------------------v----------------------'If indirect register read, no data valid flags.'(2)%1 Indirect.______________________ A _

Input connector 2 bits) with name 'c'Output conne'~tor 2 bits) with name 'DV'

Input connector 2 bits) with naro-= ' HI-IR'Input connector 7 bits) with nam02 . U":R'

Text for function 'Indirect' of 'TopLevel\TopLevel\Core8051\RAMunit\DVop':----------------------v----------------------'Indirect register read. OV = %00.'DV : = 2 zeroes.______________________ A _

Text for function 'N·ormal' .:.[ 'T"·!oLevel\T·,vL-,v,,,I\Core8051\RAMunit\DVop':----------------------v----------------------·Compose data valid flags.-DV : = (LWR fre·m: 5 te·: E.) \/ (1 ~·,r·~es, (iH-IR at: 0») \/ «(..0 at: 1), 1 zeroes).______________________ A _

'TopLeve I \ TopLeve I \C·:-re8051 \RAI~un i t \H.;DuRbu f' is a reg ister.

This register is 8 bits wide.The default function is 'h·~ld'.

This register is l'~arj.ed with unkn·:,wn valuo?s .a.fter a system res€'t.

The value loaded for the' res",t' ·;·~rnrnand is (I.

'TopLevel \T.~pLevel\C:-reSOSl \?Mlur,it \HRAM' is an c,perator.

This operator has 2 funct ic·ns and is contr·:,1 led by an unnamed control input.The default function is 'Normal'.


Control specification:----------------------v------------ R

---------

(1)%0 Normal.%1 Modi fy. 'Modi fy ope rat ion.'______________________ A _

Output connector 2 bits) with name 'c'In»ut conne·.:tor 8 bi ts) with narrl~~ 'HADDR'In»ut connector 8 bits) with name . H.'IDDRbuf'Input connector 2 bits) with narTle , HWrflod'

InlOut connector 2 bits) with name 'HWR'Output ..:onnector 8 bits) with nam..? 'ra'Output ":0nnector 8 bits) with nafTI~ 'wa'

Text for Eunct i·)n 'M·yl i fy' 0: 'T'rL·::ve I \ T:r·Lev"" I \C·:-re8051 \RAMun i t \HRAM' :----------------------v---------------- ---wa : = HADDRbu f .ra :~ HAODRbuf.c := HWmod.

- 90 -


______________________ A _

Text for function 'Normal' of 'TopLevel\TopLevel\Core8051\RAMunit\HRAM':----------------------v----------------------wa := HADDR.ra := HADDR.c := HWR.______________________ A _

'TopLevel\TopLevel\Core8051\RAMunit\HWmc·d' is a register.

This register is 2 bits wide.The default function is 'load'.This register is loaded with value 0 following system reset.


'TopLevel\TopLevel \Core8051 \RAMunit\HWR' is a register.

This register is 2 bits wide.The default function is 'load'.This register is loaded with value 0 following system reset.

The value loaded for the' reset' c·:,rr,manrj is O.

'TopLevel\TOpLevel\Core8051\RAMunit\IADDF.' is a register.

This register is 8 bits wide and is c,~ntro:,lled by an unnamed control input.The default function is 'hold'.This register is lo~r::1erJ witr. V3.1u-? I) f·:·ll..:·wing system reset.

The value loaded for th02 'l'"~g-=t.' ',;c·m~n3nrJ is O.


----------------------v----------------------·Store indirect address.·(2 )

%1 load.______________________ A _

'TopLevel \TopLevel \C·ne8051 \RAMunit \IWR' is a register.

This register is 3 bits wide.The default function is 'load'.This register is loaded with value 0 following system rese:.

The value loaded for the 'reset' cc·mmand is O.

'TopLevel\TopLevel\Core805l\RAMunit\RAMDATobuf' is a schematic.

Enhanced 8051 Core

Bidirectional connectorBidirectional connectorBidirectional connector

2 bits) with name 'DV'8 bits) with name 'in'a bits) with name 'out'

'TopLevel \TopLevel \Core8051 \RAMunit \RAMDATc·buf \DATobuf' is a register.

This register is 8 bits wide and is controlled by control input 'DV'.The default function is 'hold'.This register is loaded with uny.nown values after a system reset.


Control specification:----------------------v------ ----------------·Store RAM output data if valid.'(0)%1 load. ·Buffer RAM output.'--------------------~-~----------------------

'TopLevel\TopLevel\Core8051\RAMunit\RAMDATobuf\DATobufop' is an operator.

This operator has 2 functions and is controlled by control input 'DV'.The default function is 'BUF'.


Control connector

8 bits) with name 'Buf'8 bits) with name 'DAT'2 bits) with name 'DV'

Control specification:----------------------v----------------------·Output RAM data if valid else buffer data.·

- 91 -

Section of Digital Inform:Jtion Systems

(0)

%1 RAM.______________________ A _

Output connector ( 8 bits) with name 'out'

Enhanced 8051 Core

Text for function 'BUF' of 'TopL~vel\TopLevel\Core80S1\R~~unit\RAHDATobuf\DATobufop':

----------------------v----------------------"RAM output buffer."out : = Buf.______________________ A _

Text for function 'RAM' of 'TopLevel\TopLevel\Core80S1\RAMunit\RAMDATobuf\DATobufop':----------------------v----------------------"RAM output."out := DAT.______________________ A _

============================================='TopLevel\TopLevel\Core80S1\RAHunit\RAMiMUX' is an operator.

This operator has 3 functions and is controlled by an unnamed control input.The default function is 'STACK'.

Control conn~ctor (10 bits) without a nam€

Control spe~ification:

--- ---- --- -- ------- - --'J-- - -- - ---- - - - _. - - - - - --

"Select RAM data input."%1011000000, "PUSH dir"%010000011", "INC @Ri"%010001011x, "DEC @Ri"%010111011x, "MOV @Ri,Mdata"%101010011x, "HOV @Ri,dir"%011100011x, "Y,CH A,@Ri"%011101011x, "XCHD A,@Ri"%011111011x, "HOV ',Ri, A"%0100001xxx, "INC Rn"%0100011xxx, "DEC Rn"%0101111xxx, "MOV Rn, Mdata"UOI0I0lxxx, "MOV Rn, dir"%0111001xxx, "XCH A,Rn"%0111011xxx, "DJNZ Rn, reI"%0111111xxx ALU. "HOV Rn,A"%0100010000, "JBC bit, rei"%0111010000, "POP dir"%010100001:<, "ORL dir,A So. #data"%010101001x, "ANL dir,A & Mdata"%010110001x, "XRL dir, A & Mdata"%0110010010, "MOV bit, C"%0110110010, "CPL bit"%0111000010, "CLR bit"%0111010010, "SETB bit"%0100000101, • INC dir"%0100010101, "DEC dir"%0101110101. "MOV di r. Mdata"%1010000101, "MOV dir,dir"%0111000101, "XCH A,dir"%0111010101, "DJNZ dir,rel"%0111110101, "MOV dir,A"%101000011:<, "HOV dir,@Ri"%1010001xxx Direct. "MOV dir,Rn"---------------------- ~ ---------_. -----------

Input connector 3 bits) with naITl~ , ALUc,ut 1 'Input connector S bits) with name 'Direct'Input connector 8 bits) with name 'FCdat'

Output connector S bits) with name 'RAM'

Text for function 'ALU' of 'TopLevel \TopLevel\Core8051 \RAMunit\RAHiMUX' :----------------------v----------------------"Data from ALU."RAM : = ALUout 1.----------------------~----------------------

Text for function 'Direct' of 'TopLevel\TopLevel\Core8051\RAMunit\RAMiMUX':----------------------v----------------------"Direct addressing."RAM : = Direct.______________________ A _

Text for funct ion 'STACK' of 'TopLevel \TopLevel \CoreSOSI \RAMuni t \RAMiHUX' :----------------------v----------------------"PUSH stack data,"

- 92-


RAM := PCdat.______________________ A _

======================~======================

'TopLevel\TopLevel\CoreBOS1\RAMunit\RAMOp' is an operator.

This operator has 2 functions and is c~,ntrolled by an unnamed control input.The default function is 'Busy'.

Enhanced 8051 Core

control connector ( bit ) without a name

Control specification:----------------------v-----------------------RAM access control.-%0 IWR. " RAM accessable."%1 Busy. "No RAM access until data valid signal is detected."______________________ A _

Output connectorOutput connector


1 bit) with name 'Busy'3 bits) with name 'IWR'3 bits) with name 'RAMIWR'2 bits) with name 'WR'

Text for function 'Busy' of 'TopLevel\TorLevel\Core80S1\RAMunit\RAMop':----------------------v-----------------------RAM is busy; no acc~ss.·

IWR := 3 zeroes.WR := 2 zeroes.Busy := 1 ones.______________________ A _

Text for funct ion' IWR' of 'T·cpLevel \T·,·pL·ov~'\C0re30S1 \RAMunit \RAMop':----------------------v-----------------------Indirect register addressing.·IWR : = (RMIIWR at: 2) i fO: 3 Z02[(·es

if 1: R."..MIWF:. ·St·)re indir-?·:t action.WR : = (RAM I\-JR at: 2) if (, : (RAI·ll\oiR Erom: (l t c·: 1)

if 1: 1 zeroes, 1 0n~s. -Read indirect address.Busy:= (RAMIWRat: 0) \/ (RAMIViRat: 1).

'TopLevel\TopLevel\Core805l\RhMunit\RAMSelect' is an operator.

This operator has 2 fur.ctions awl is cor,trolled by an unnamed control input.The default function is 'Nom,al'.

Concrol connector ( 3 bits) without a name

Control specification:----------------------v----------------------'Detect indirect addressing."(2)%1 Indirect.----------------------~----------------------

Output connector 8 bits) with name 'ADDR'Input connector B bits) with name 'IADDR'Input connector 3 bits) with name ' IWR'Input connector B bits) with name 'F-AMADDR'Input connector 2 bits) with name 'WR'

Output connector 2 bits) with narrle 'WRo'

Text for function 'Indirect' of 'TopLevel\TopLevel\Core80SI\RAMunit\RAMSelect':----------------------v----------------------'Select indirect RAM address."WRo := IWR from: 0 to: I.ADDR : = IADDR.----------------------~----------------------

Text fc,r funct ion 'Norma l' c,f 'T0,'Leve 1\T,opLev·o I \C0re80S 1 \RAMun i t \RAMSe Iect' :----------------------v----------------------·Select normal RAM address."WRo := WR.ADDR := «WR at: 0) \/ (WR at: 1») iEO: 8 ::e1"0eS

ifl: RAHADDR.______________________ A _

'TopLevel\TopLevel\Core805l\SP_CTRL' is a sch~matic.

Bidirect ional connector ( 8 bits) with rJetm-e 'DirDat'Bidit-ectional connectc'r ( 1 bit ) with n2tHl"? 'f\.023dy'Bidirectional connector (10 bits) with nam~? 'SFR'Bidirectional connector (16 bits) with nam: 'SPaddr'Bidirectional conn-:ctor ( 8 bits) with narrl{J , SF·~,'

- 93 -


Bidirectional connector ( 2 bits) with name 'SPWR'=========================================

'TopLevel\TopLevel\Core805l\SP_CTRL\POPop' is an operator,

This operator has 5 functions and is controlled by an unna~ed control input.The default function is 'five'.


Control specification:----------------------v----------------------"Select POP address code."%0000000000000000 one.%0000000000000001 two.%OOOOOOOOOOOOOOlx two.%OOOOOOOOOOOOOlxx two.%OOOOOOOOOOOOlxxx two.%OOOOOOOOOOOlxxxx two.%0000000000100000 three.%0000000000100001 four.%000000000010001x four.%00000000001001xx four.%0000000000101x%x four.%OOOOOOOOOOllxxxz four.%OOOOOOOOOlxxxxxz four.%OOOOOOOOlxxxxxxx four.----------------------~----------------------

Output connector ( 3 bits) with name 'Qut'

Text for function 'five' of 'T·:>pL""J·Jl\T':'l,L,?';,?I\C,jre8051\SF_CTRL\POPop':----------------------v----------------------"POP address = $lOO .. $FFFF"out := lones, 1 zero~s, 1 ones.----------------------~----------------------

Text for funct ion' four' 0f 'T.~pLevcl\T,:,pLev-a1 \Core8051 \SP_CTRL\POPop':----------------------v----------------------"POP address = S21 .. SFF"out := lones, 2 zeroes.______________________ A _

Text for function 'one' of 'TopLevel\TopLevel\Core8051\SP_CTRL\FOPop':----------------------v----------------------'POP address = $0"out := 2 zeroes, 1 ones.______________________ A _

Text for function 'three' of 'TopLevel \TopLevel\Core8051 \SP_CTRL\POPop' :----------------------v----------------------'POP address = S20"out := 1 zeroes, 2 ones.______________________ A _

Text for function 'tw'J' vf 'T'JpLevel\TopLo?vo?l\Core805l\SP_CTRL\POPop':----------------------v----------------------"POP address = Sl .. SlF"out : = 1 zeroes, 1 ,:·n-as. 1 :::-?ro-?s.

'TopLevel\TopLevel\C0re8051\SP_CTRL\POPreg' is a register.

This register is 3 bits wide and is contr·olled by an unnamed control input.The default function is 'hold'.This register is loaded with value 0 following system reset.

The value loaded for the 'reso?t' command is O.

Control specification:----------------------v----------------------(0)

%1 load. "Load POP address code,"______________________ A _

'TopLevel\TopLevel\Core8051\SP_CTRL\SP_POP' is an operator.

This operator has 2 functions.The default function is 'Nonr,al'.

Enhanced 8051 Core


2 bits) with name 'wRi'2 bits) with name 'WRo'

- 94-


Text for function 'NoDec' of 'TopLavel\TopLaval\Core80S1\SP_CTRL\SP_POP':----------------------v----------------------"No decrement for POP SPL or SPH."WRo := 2 zeroes.______________________ A _

Text for function 'N·~rmal' of 'TopLevel\TopLe'Jel\Core80Sl\SP_CTRL\SP_POP':----------------------v----·------------------Increment or decrement stack rointer.-WRo : = WRi.______________________ A _

'TopLevel\TopLevel\Core80S1\SP_CTRL\SP_reg' is a register,

This register is 16 bits wide.The default function is 'l-:·ad'.This register is loaded with Value 7 following system reset.


'TopLevel\TopLevel\Core80S1\SP_CTRL\SP_Sel' is an operator.

This operator has 2 functions and is contrc-ll",el by an unnamed control input,The default function is 'SPL'.


Control specification:----------------------v----------------------"Select stack pointer low or high byte for c-peration."(0 •• 7)%10000101 SPH. "SPH"______________________ A _

Input connector (16 bits) with name 'SP16i'Output connector (16 bits) with name ' SP16o'

Input connector ( 8 bits) with narne 'SPi'Output connector ( 13 bits) with name 'SPa'

Text for function 'SPH' of 'TopL-2vel\T·~pLevel\Ce·reS051\SP_CTRL\SP_Sel':

----------------------v----------------------SPo := SP16i from: 8 to: 15.SP160 := SPi, (SP16i from: 0 to: 7).______________________ A _

Text for fun~tion 'SF-V ·:·f 'T·e·pLe':el \Te-pLevel .. c.:·re80S1 \SP_CTRL\SP_Se!':----------------------v----------------------SPa := SP16i from: 0 to: 7.SP160 := (SP16i from: 3 t·~: E.), Sri.______________________ A _

'TopLevel \ TopL-2ve 1 \Core80S1 \SP_CTRL \SF'op' is an e-perator.

This operator has 2 functie·ns and is contre,lled by an unnamed control input.The default function is 'OLD_SP'.

Cc-ntrol connector (10 bits) without a !lam",

Control specification:----------------------v----------------------%xll0000xOl NEW_SP. ·Write"______________________ A _

Input connector (16 bits) with name 'in'Output connector (16 bits) with name 'out'

Input connector (16 bits) with name 'SP'

Text for function 'NEW_SP' of 'TopLevel\TopLevel\Core8051\SP_CTRL\SPop':----------------------v-----------------------Load new s~ack pointer.-out := SP,

Text for function 'OLD_SP' of 'TopLevel\TopLevel\Core80S1\SP_CTRL\SPop':----------------------v----------------------"No stack pointer change."out := in.______________________ A _

'TopLevel \TopL",vel \C,c,r",oOSl \SI'_CTF:L\ST.L.Cl;' is an operator.

This operator has 3 functi0ns.The default function is 'N-:onnal'.

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Enhanced 8051 Core


Output connector ( 2 bits) with name 'WR'

Text for function 'Normal' of 'TopLevel\TopLevel\Core8051\SP_CTRL\STACK':----------------------v----------------------"No stacK operation."WR := 2 zeroes.______________________ A _

Text for function 'POP' of 'TopLevel\T0t:'Level\Cor",80S1\SP_CTRL\STACK':----------------------v----------------------"POF from stack.·WR := 1 zeroes, 1 ones.______________________ A _

Text for function 'PUSH' of 'TopLevel\TopLevel\Core8051\SP_CTRL\STACK':----------------------v----------------------·PUSH onto stack."WR := 1 ones, 1 zeroes.______________________ A _

'TopLevel\TopLevel\Core8051\SP_CTRL\STACKop' is an operator.

This 0p€'ra~or has 3 functions and is c.:,ntrc·lll?d by an unna.med control input.The default function is 't!·:·rrr,al·.

Control connector ( 2 bits) with0Ut a na~~

Control specification:----------------------v----------------------%01 POP.%10 PUSH.----------------------~----------------------

Output connector (16 bits) with r:ame ..•.DDR·~'Input connector (16 bits) with name 'Sri'

Output connector (16 bits) with name 'SP·~'

Text for funct ion 'N·~rmal' of 'T0pLev"l \T'~pLevel\Core8051 \SP_CTRL\STACKop':----------------------v----------------------·Throughput stack pointer.·SPa := Spi.ADDRo : = SPi.---------------------_ .... _---------------------

Text for funct ion 'FOF' of 'T0pLevel \T-:rLevol \Cc·re8051 IS?_CTRL\STACKop' :----------------------v----------------------·Pop from sta~k.·

SPo := SPi + 16 0rl~S.

ADDRo : = spi.

Text for fun·~t ion . PUSH' of 'T-:·pL",vel \T-:·pL,~·~el \C·~r",8051 \SF_CTF:L\STACKop' :----------------------v------------------··--"Push onto stack."_inc := SPi + (15 zeroes, 1 ones).SPo:= inc.ADDRo:= lnc.

'TopLevel\TopLevel\Core8051\SF_CTRL\SV' is a register.


The value loaded for the 'reset' command is 0.

'TopLevel\TopLevel\Core8051\SF_CTRL\SVop' is an operator.

This operator has 2 functions and is controlled by an unnamed control input.The default function is 'Ready'.


Control specification:----------------------v----------------------(8 .. 15) ·Internal RAM."%00000000 SET.

Output C0n~ector ( 1 bit I wit:! li51rfl02 "Fl2tg'Input connector ( 1 bit) with name 'Ready'

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Enhanced 805 I Core


Text for function 'Ready' of 'Tc'pLev",1 \Tr~pLev",l \Core80S1 \SP_CTF,L\SVop':----------------------v----------------------Flag := Ready.----------------------~----------------------

Text for function 'SET' of 'TopLevel\TopLevel\core80S1\SP_CTRL\SVop':----------------------v----------------------Flag := 1 ones.______________________ A _

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Enhanced 8051 Core

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