IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 5 , AUGUST 1993 571

Effects of Parylene Coating on the Thermal Fatigue Life of Solder Joints in Ceramic Packages Ho-Ming Tong, Lawrence S . Mok, K. R. Grebe, Helen L. Yeh, Kamalesh K. Srivastava, and Jeffrey T. Coffin

Abstruct- A study was undertaken to determine the effec- tiveness of a thin layer (9.4 pm in thickness) of a chemical vapor deposited polymer, Parylene, in enhancing the solder lifetime of a ceramic package containing large-DNP (distance to neutral point) test chips. Both coated and uncoated (control) packages with chips joined via C4 Pb/Sn solder technology were thermally cycled between near room temperature and liq- uid nitrogen temperature (-196°C). At every 50 or 100 cycles, electrical resistances of solder joints were measured at room temperature for the nondestructive detection of solder failures based on a solder electrical resistance criterion. The thermal cycling experiment and electrical measurement were continued until solder failure was first noticed in coated packages. The number of cycles to first failure for coated packages was found to be twice the corresponding number of uncoated packages. To interpret this twofold solder life enhancement associated with Parylene, an elasto-plastic finite-element model was developed and used to determine the thermal strain and stress distributions near failed solder joints for coated and uncoated packages at liquid nitrogen temperature. Based on the results provided by this model and a low-temperature solder lifetime model, we were able to attribute the extended solder life to the modification of the strain and stress fields in the solder joints by the Parylene coating. The model also suggests that the solder life can be prolonged significantly with a Parylene coating as thin as 3 pm.

I. INTRODUCTION N a recent paper [l], we have stated the advantages of I operating CMOS devices at liquid nitrogen temperature

(LNT, -196’ C) and evaluated the compatibility of ceramic packages containing Pb/Sn solder joined test chips operated at LNT. After thermally cycling the uncoated ceramic packages between near room temperature and LNT, we found that a fraction of the largest-DNP (distance to neutral point) solder joints failed after a large number of LNT cycles, while solder joints with smaller DNP’s remained intact.

The present work was undertaken to establish the effective- ness of a chemical vapor deposited polymer, Parylene (from Union Carbide), in enhancing the LNT cycling lifetime of the largest-DNP solder joints in the ceramic packages. In contrast

Manuscript received June 18, 1992; revised January 20, 1993. This paper was presented at the 40th Electronics Components and Technology Conference, Las Vegas, NV, May 21-23, 1990.

H. M. Tong, K. K. Srivastava, and J. T. Coffin are with IBM Microelec- tronics, IBM Corporation, Hopewell Junction, NY 12533.

L. S . Mok is with the Thomas J. Watson Research Center, IBM Research Division, Yorktown Heights, NY 10598.

H. L. Yeh is with the Personal System Division, IBM Corporation, Somers, NY 10589

K. R. Grebe was with the Thomas J. Watson Research Center, IBM Corporation, Yorktown Height, NY. He is now retired.

IEEE Log Number 9209857.

to the common notion of flip-chip package encapsulation using a thick polymer coating (for instance, a silicone for a Si-on- Si module [2], or a “thermal expansion matched” resin for a soda-lime glass substrate with LSI devices [3]), we chose to use a thin layer (9.4 pm in thickness) of Parylene in this work not only to shorten the processing time and expense, but also to utilize the unique pinhole-free ultrathin coating capability of Parylene which is often used for encapsulation of printed wiring boards [4].

In the ensuing sections, we will first describe the process and advantages of Parylene encapsulation. This is followed by a brief description of the thermal cycling experiment and failure analyses including solder resistance measurement and scanning electron microscopy (SEM) performed in this study. The experimental results are shown next and are discussed with the help of a solder lifetime prediction and a finite- element model. Finally, the theoretical predictions provided by the model at different thicknesses of Parylene are presented.

11. PARYLENE ENCAPSULATION Parylene is produced by vapor-phase deposition and poly-

merization of para-xylylene or its substituted derivatives via a three-step vacuum process consisting of vaporization of the solid dimer, cleavage of the dimer, and deposition onto a substrate typically at room temperature (Fig. 1; see [5] and [6]). In contrast to vacuum metallization which is a line-of- sight process, Parylene deposition takes place from a cloud of reactive vapor, forming a pinhole-free conformal coating as thin as 0.03 pm [7] even in fine crevices, or in the tiny gaps between chips and carrier [8]. This conformal coating property allows all exposed surfaces of the ceramic package to be equally protected against environmental corrosion. Other advantages of Parylene include 1) effectiveness as a barrier to oxygen, moisture, and carbon dioxide [5] which can affect the solder lifetime, 2) mechanical stability between -200 and 150” C (5, 9), 3) low or minimal impact on package cooling [SI, 4) low stress level [6], and 5) absence of trace contaminants [5].

According to a report by Hughes Aircraft [lo], a notable advantage of Parylene over other encapsulants such as sili- cones and epoxy resins is its ability to coat without forming thick fillets which can lead to high stresses and sites of crack initiation during heat treatment. The report also recommended that the high material and processing costs associated with the Parylene coating can be minimized by using a coating thinner than 0.5 mil (- 12 pm) and by processing parts in batches. Due to the advent of large-capacity Parylene deposition units,

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572 IEEE TRANSACTIONS ON COMPONENTS. HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 5, AUGUST 1993

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Fig. 1. Chemical vapor deposit of Parylene.

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Fig. 2. Cross-sectional view of a multilayer ceramic package.

the thinness of Parylene used as well as the absence of any post-deposition cure steps, the Parylene encapsulation process has become more cost competitive compared to the encapsulation processes using thick polymer films.

111. EXPERIMENTS

As in our previous work [l], the multilayer, multichip ceramic packages used in this study were built by joining test chips containing Pb/Sn solder balls to the Ni-Au top surface metallurgy of alumina based substrates using IBM’s controlled collapse chip connection (C4) technology (Fig. 2). The solder footprint of the chip was approximately symmetrical to the geometrical center (or neutral point) of the chip. Following package assembly, half of the packages were used as control, and the other half were coated with Parylene of about 9.4 pm thick using the process shown in Fig. 1, except over the connection pins on the opposite side of the ceramic substrate (not depicted in Fig. 2). Pin masking was achieved by covering the pins with a Kapton polyimide film glued to the ceramic through a double stick adhesive tape. The Kapton film and adhesive tape were removed after the Parylene coating.

Both the coated and uncoated packages were LNT cycled under identical conditions in an automated LNT cycler (Fig. 3; see also [l]). Again, as in our previous work [l], a typical LNT cycle lasted approximately 1 hour between near room temperature and LNT with a dwell time of 10 minutes or greater at both temperatures.

Room-temperature electrical resistance measurements were made before LNT cycling and at every 50 or 100 LNT cycles

Fig. 3. Schematic of an automatic LNT cycler.

to determine whether solder failure, indicated by a significant increase of resistance, had occurred. After completion of LNT cycling, the failed solder joints were cross-sectioned and examined by SEM. In addition, the chips were pulled from the uncoated packages to allow the inspection of the fracture modes of individual solder joints and the identification of those that were weakened by LNT cycling but did not fail the resistance criterion [l].

IV. RESULTS

Our room-temperature resistance data for the uncoated packages indicated that only the largest-DNP solder joints had failed and the cumulative solder failure rate steadily increases with increasing number of cycles. In contrast, no solder failure was observed in Parylene coated packages until near the end of LNT cycles when the first and only failure of a largest- DNP solder joint was noticed. Aside from the differences in solder failure rate, the nonfailed solder joints in Parylene coated packages exhibited much milder (actually negligible in almost all of the cases) resistance increases with number of LNT cycles compared to uncoated modules. This indicates that the coated packages could have exhibited a much slower increase in solder failure rate had one cycled these modules beyond the maximum number of LNT cycles adopted in this study.

After LNT cycling, the failed solder joints in both coated and uncoated packages were cross sectioned and examined by SEM. Fig. 4 shows the SEM micrograph of a failed largest- DNP solder joint in an uncoated package. The solder failure can be seen to be associated with a crack initiated at the solder surface and propagated across the solder joint near the ceramic substrate. The presence of a crack not only altered the cross-sectional (electrically conducting) area of the solder joint in a plane nearly parallel to the ceramic surface but also allowed the newly exposed crack surface to be oxidized [ll]. Both factors led to an increase of the solder resistance. The cracking and solder deformation behaviors shown in Fig. 4 are characteristics of failed solder joints in uncoated packages during LNT cycling as found previously [l]. The only failed

TONG et al.: EFFECTS OF PARYLENE COATING ON THE FATIGUE LIFE OF SOLDER JOINTS 573

Fig. 4. Cross-sectional SEM micrograph of a failed solder joint in an Fig. 6. SEM micrograph (top view) of the fracture surface of a solder joint uncoated package. on a ceramic substrate in an uncoated package after chip pull.

temperature TmaX. The shear strain amplitude E can be estimated using

E = h L m , . (as - a,) dT.

In the above, h is the solder joint height, T,,, the minimum cycling temperature, a the temperature dependent thermal expansion coefficient, and the subscripts s and c denote ceramic and chip properties, respectively. According to (1) and (2), a solder joint with a higher DNP is characterized by a

(2) DNP Tmax

PARYLENE

-CERAMIC

Fig. 5. Cross-sectional SEM micrograph of a failed solder joint in a coated package.

solder joint (at the largest DNP) in coated packages was found to be devoid of any sign of cracking (Fig. 5). Solder failure in this case was probably due to the presence of a crack which resided in a planar segment of the solder parallel to that shown in Fig. 5.

The fracture surfaces of solder joints in uncoated modules after chip pull indicated extensive cycling damage at or near the largest-DNP solder joints. Shown in Fig. 6 is the fractured surface of a solder joint on the ceramic substrate. Although this solder joint passed the failure criterion, its fracture surface was quite similar to the crack surface shown in Fig. 4. This indicates that this solder joint might have been weakened during LNT cycling.

A. Solder Lifetime and Finite-Element Modeling To explain why Parylene coated packages had an extended

solder life, it is important to know the strain field in the largest- DNP solder joints for both coated and uncoated packages. The modified Coffin-Manson formula [ 11 predicts the number of thermal cycles N to a given cumulative solder failure rate as follows:

shorter lifetime in N , keeping other conditions constant. This is consistent with the fact that only the largest-DNP solder joints failed in both coated and uncoated packages during LNT cycling.

In this study, we have determined the magnitude of E as well as the associated strain and stress fields near the failed solder joint for both coated and uncoated packages using a finite- element model which utilized two-dimensional isoparametric solid elements to represent the structure of the chip and substrate along the diagonal of the chip. As shown in Fig. 7(a) for an uncoated package, only two solder joints along the diagonal of the chip were used in accordance with the actual solder footprint, and the joint farther away from the center of the chip was characterized by the largest DNP. A blown- up view of the largest-DNP solder joint can be seen in Fig. 7(b). For coated packages, three more layers of elements were added to the surfaces of the chip, solder joints, and ceramic [Figs. 8(b) and 9(b)] to represent Parylene which conformally coated all these surfaces. Perfect adhesion between Parylene and the surface underneath it was assumed.

The stress and strain computations of the model were carried out using a finite-element program called ANSYS [12]. A simplified elasto-plastic stress-strain curve which did not include the time-dependent creep effect was used for the solder and the zero-stress (or zero-strain) temperature was taken at room temperature. The changes in stress or strain were all assumed to be thermal in origin.

V. DISCUSSION

where C is an empirical constant, E the plastic shear strain amplitude, f the cycling frequency, and an empirical function which decreases with increasing maximum cycling

To account for an extended solder lifetime associated with a coating, it is customary to resort to the argument of stress or strain reduction in the presence of the coating [3]. Fig. 8

574 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 5, AUGUST 1993

CENTER OF CHIP CHIP

CERAMIC

(a)

CHIP

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(b) Fig. 7. (a) A two-dimensional finite element model. (b) A blown-up view of

(a) around the largest-DNP solder joint.

shows the contours of shear strain amplitude near the largest- DNP solder joint for both uncoated and coated packages at LNT where the stresses and strains are the highest. The shear strain here was calculated by dividing the difference between the local displacement and the displacement at the solderkhip interface [point X in Fig. 8(a) and (b)] by the solder height (h). For both uncoated and coated packages, lines A, B, and C corresponded to shear strains of 2.5, 1.4, and 0.5%, respectively, and the maximum shear strain amplitude in the solder occurred near the solder/ceramic interface with its magnitude being 3.7% for uncoated packages and 2.8% for coated packages. According to (l), the difference in shear strain here could have accounted for 1.75 out of a factor of 2 in solder life enhancement achieved with Parylene encap- sulation. Note here that the maximum shear strain amplitude for the uncoated packages compared well to what (3.3%) we calculated previously [l] by (2). It is also worth noting that the largest-DNP solder joint for both the uncoated and coated packages was deformed, consistent with SEM observations (Figs. 4 and 5).

The stress counterparts of Fig. 8 are plotted in Fig. 9 where the principal stresses (at LNT) were plotted in vector form for the left-hand portion of the largest-DNP solder. In these figures, vectors with arrow heads pointing outward indicate tensile stresses while those with arrow heads pointing inward

PAR

T CERAMIC

@) Fig. 8. Contours of shear strain near the largest-DNP solder joint at LNT for(a) an uncoated package and (b) a coated package, where A , B, and Cdenote 2.5. 1.4. and 0.5%. resoectivelv.

signify compressive stresses. Moreover, the length of each vector is proportional to the magnitude of the stress. Because the thermal expansion coefficient of Parylene (69 ppm/OC; see [5]) is much higher than that of the solder (30.4 ppm/OC; [13]), the Parylene coating contracts more than does the solder as the temperature decreases. The contraction of Parylene modifies the stress field in the solder quite significantly particularly near the solderParylene interface. Furthermore, with Parylene coating, the tensile stresses in the solder near the ceramic have their directions altered. Such stress modification behavior of Parylene quite possibly participated in promoting the solder life during LNT cycling. For uncoated packages, the cracks in the solder joints near the ceramic may have been initi- ated and propagated by these tensile stresses in the presence of the solder intermetallics [ l ] which make the principal solder deformation mechanism, i.e., grain boundary sliding, difficult.

Apart from the strain and stress modification behaviors, the barrier and conformal coating characteristics of Parylene could have also enhanced the solder life. As a coating on the solder, Parylene substantially slowed down the attack of the solder by deleterious gases such as water vapor, carbon dioxide, and oxygen. While moisture and carbon dioxide are known to corrode Pb/Sn solders particularly in the presence of chloride ions [14], oxygen can react with the solders to form oxides. These gases might lead to the formation of a brittle surface layer on the solder, which upon thermal cycling could crack, due to the thermal expansion mismatch between virgin solder and surface layers. Berriche et al. [15] noted that the life of

I

TONG et al.: EFFECTS OF PARYLENE COATING ON THE FATIGUE LIFE OF SOLDER JOINTS

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the bulk cast 95 Pbl5 Sn alloy was higher in vacuum than in air. At small strain amplitudes, they attributed the difference between the two environments to the increased diffusion of oxygen along the grain boundaries in the air environment. In addition to suppressing the formation of surface crack nuclei, Parylene might also fill cracks which might have existed at the solder surface prior to Parylene deposition.

In order to determine the effect of Parylene thickness on solder lifetime for LNT operation, we have used the finite-element model to calculate the maximum shear strain amplitude at the largest-DNP solder joint for a coated package at different Parylene thicknesses. The results are shown in Fig. 10. From this figure, one can see that the shear strain decreases with increasing coating thickness. But the rate of decrease slows after a thickness of about 3 pm. Based on (l), we think that the lifetime of the largest-DNP solder joint will probably not be significantly prolonged beyond such a thickness.

Fig. 10. Predicted maximum shear strain amplitude at the largest DNP solder joint as a function of parylene thickness.

VI. SUMMARY

With the use of Parylene, a chemical vapor deposited polymer, to encapsulate multichip ceramic packages, we were able to extend the lifetime of the largest-DNP (distance to neutral point) solder joints by at least twofold during thermal cycling between near room temperature and liquid nitrogen temperature (-196°C). In this paper, we also found that the extension of the solder life by means of Parylene coating is primarily due to its capability of modifying the stress and strain fields in the solder joints.

ACKNOWLEDGMENT Thanks are due to A. Aldridge for providing the test chips

and to A. J. Daley for performing the SEM analysis. We would also like to thank S. Purushothaman and K. Saenger for kindly reviewing this paper.

REFERENCES

H. M. Tong, H. Yeh, R. Goldblatt, K. Srivastava, J. Coffin, W. Rosenberg, and J. Jaspal, IEEE Trans. Electron Devices (Special Issue on Low-Temperature Semiconductor Electronics), vol. 36, no. 8, p. 1521, 1989. T. Yamada, K. Otsuka, K. Okutani, and K. Sahara, Proc. Fiph Ann. Int. Electronics Packaging Conf, Orlando, FL,, Oct. 21-23, 1985. T. Soga, F. Nakano, and M. Fuyama, Trans. Inst. Electron. Inform. Commun. Eng. C (Japan), vol. J70C, no. 12, p, 1575, 1987. R. A. Dunaetz, D. M. Davis, et aL, “Repair of conformally coated printed wiring board assemblies,” vols. 1 and 2, Hughes Aircraft Co., Tech. Rep. AFWAL-TR-80-4086. Parylene Conformal Coatings, Union Carbide. B. J. Bachman, 1st Int. SAMPE Electronics Conf, vol. 1, pp. 431-440, 1987. M. A. Spivack, Rev. Sei. Instrum., vol. 41, p. 1614, 1970. E. Bemdlmaier, B. T. Clark, and J. A. Dorler, “Heat transfer structure for integrated circuit package,” U. S. Patent 4 323 914, Apr. 6, 1982. J. T. Yeh, private communication (this mncems no crack development in Parylene during thermal cycling between room temperature and -269O

‘Aybrid Parylene coating study,” Hughes Aircraft Co., HAC Ref. C- 774612, Aug. 1972. R. N. Wild, Proc. Tech. Program+VEPCON, Anaheim, CA, Feb. 2628, 1974; see also Welding J., vol. 51, p. 521S, 1972. ANSYS finite-element program is licensed from Swanson Analysis Systems Inc., Houston, PA 15342. T. Nishio, private communication. R. J. K. Wassink, Soldering in Electronics. Scotland: Electrochemical, 1989, p. 280. R. Bemche, S. Vaynman, M. E. Fine, and D. A. Jeannotte, Proc. ASM Third Con$ Electronic Packaging: Materials and Processes and Corrosion in Microelectronics, ASM, M. E. Nicholson, Ed., 1987, p. 169.

576 IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 16, NO. 5, AUGUST 1993

Ho-Ming Tong received the B.S. degree in chemical engineering from the National Taiwan University in 1976, and the M.S., M.Ph., and Ph.D. degrees in chemical engineering from Columbia University.

In 1982, he joined IBM’s Thomas J. Watson Research Center as a Research Staff Member. Cur- rently, he is a Senior Engineering Manager with IBM. He has done extensive research in the fields of electronics packaging and polymer thin films, and is the editor of two books on the latter subject. He currently holds 12 U. S. and international patents.

Lawrence S. Mok received the B.S. degree in electrical engineering from the University of Tulsa, OK, in 1977, and the M.S. and Ph.D. degrees in nuclear engineering from the University of Illinois at Urbana-Champaign, in 1979 and 1984, respectively.

In 1984, he joined IBM’s Thomas J. Watson Research Center, where he has worked on various topics related to electronic packaging, including thermal management and thermal-mechanical anal- ysis. He has published several papers and currently holds 6 U. S. and international patents.

K. R. Grebe, photograph and biography not available at time of publication.

Helen L. Yeh received the B.A. degree in physics from National Taiwan University, Republic of China, the M.A. degree in physics from the State University of New York at Stony Brook, and the Ph.D. degree in metallurgy and materials science from the University of Pennsylvania, Philadelphia.

She has done research on the surface analysis of various alloys and improved lead acid battery with the Research and Development Laboratory, International Nickel Co. In 1980, she joined IBM’s

Yorktown Manufacturing Research Laboratory, where her work has been in the areas of contamination control, multilayer thin films, dry bonding process (chemical fluxless) in the first level packaging, such as C4 chip joining, pin brazing, and seal pretinning and capping. She has held several positions of responsibility with IBM, including Research Staff MembedManager with the Thomas J. Watson Research Center, Member of the Technical Planning Staff, Research Division Headquarters, Program Manager of Advance Packaging Facility, and Manager of the Low Temperature Packaging, VLSI Packaging Applications in Yorktown. Currently, she is a Market Development Program Manager, Personal System Line of Business, IBM.

Dr. Yeh,is a member of Sigma Xi.

Kamalesh K. Srivastava received the B.Tech. and M.Tech. degrees in metallurgical engineering from the Indian Institute of Technology, Kanpur, India, in 1969 and 1972, respectively, and the Ph.D. de- gree in metallurgical engineering from McMasters University, Canada, in 1980.

From 1972 to 1975, he was with Bharat Elec- tronics Limited, India, where he worked on the development of low-loss dielectric materials. From 1980 to 1982, he was with the Beryllia Corporation, working on the development of beryllia-based elec-

tronic packages. From 1982 to 1984, he was with the Westinghouse Electric Corporation, where he worked on the development of high temperatures sealing glasses for high intensity sodium lamps. In 1984, he joined IBM’s East Fishkill Facility, where he has held responsibilities in the areas of controlled collapse chip connection development, synthetic flux development, and low cost pin attachment process development. Currently, he is involved with thin film work relating to interconnections in DRAM memory chips at the Advanced Semiconductor Technology Center, IBM, East Fishkill, NY.

Jeffrey T. Coffin received the B.S. degree in metallurgy and material science from Columbia University in 1983, and the M.S. degree in metallurgical engineering from the Polytechnic Institute of New York in 1986.

He joined IBM’s Eat Fishkill Facility in 1983, where he is currently- a Staff Engineer working in the Packaging Reliability Engineering Department