effects of on-chip inductance on power distribution grid
DESCRIPTION
Effects of On-chip Inductance on Power Distribution Grid. Atsushi MuramatsuKyoto Univ. Masanori HashimotoOsaka Univ. Hidetoshi OnoderaKyoto Univ. [email protected]. chip. bonding wire. bump ball. chip. Inductance in power grid analysis. Advance in packages. Conventionally - PowerPoint PPT PresentationTRANSCRIPT
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Effects of On-chip Inductance on Power Distribution GridAtsushi Muramatsu Kyoto Univ.Masanori Hashimoto Osaka Univ.Hidetoshi Onodera Kyoto [email protected]
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Inductance in power grid analysis Conventionally
Inductance of package and bonding dominant considered
Inductance of on-chip wire many elements yet small not considered
Recently Increase in clock freq.
higher freq. component of noise L increases as freq. increases
Reduction in L of package and bonding Relatively on-chip L increases
Q: on-chip inductance important?
Advance in packages
QFP
FCBGA( Bump Array)
chip
bonding wire
bump ball
chip
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Previous works
[Mezhiba, Kluwer 2004] Outline of on-chip inductance aware analysis Noise propagates as a wave
[Y.-M. Lee, TCAD02] Fast simulation based on transmission line theory
[W.H. Lee, ISQED04] Discussion on wire structures
[C.W. Fok, Int’l Journal of High Speed Elec. & Sys 02] Discussion on error due to ignoring on-chip inductance Effect of on-chip inductance becomes significant when package
impedance is small.
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Contribution of this work
Experimental studiesTo evaluate effect of on-chip inductance unde
r various power consumption distributionTo reveal that decap. position is important to
mitigate on-chip inductance effect as well as to suppress power noise
To study robustness of power grid with respect to grid pitch, wire area and PG spacing
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Power grid structure
Power and ground wires are routed in pairs. Only topmost power/ground grid is considered. Bumps are uniformly attached at some of crossing points.
PowerGround
Grid pitch
Wire widthSpacing between powerand ground wires
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Equivalent circuit model
Cell parasitic capacitance
and well capacitance
Power IO
Load current source that
models switching gates
PowerGround
Grid pitch
Wire widthSpacing between powerand ground wires
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Experimental setup(single current source) A single current source excited
All NAND2 gates in 3,000m2 switch Tr: 50, 66, 100ps (constant power dissipation)
P/G wire: 10m wide, 1m thick, 100m pitch 130nm technology, supply voltage 1.2V 2x2mm2 chip, 9+9 bumps for P/G Each bump 0.5nH, 1 Full PEEC model: all mutual inductances consid
ered. Half area is occupied by NAND2 gates
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Difference between w/ and w/o on-chip inductance
Big difference between w/ and w/o on-chip inductance
Without on-chip inductance, not strong dependence on Tr.
0
5
10
15
20
25
30
40 50 60 70 80 90 100 110
Current transition time Tr [ps]
4.3x104/Tr2Simulation result
1.18
1.185
1.19
1.195
1.2
1.205
1.21
1.215
0 50 100 150 200 250Time [ps]
With on-chip inductanceTr = 100ps
With on-chip inductanceTr = 66ps
With on-chip inductanceTr = 50ps
Without on-chipinductance
With on-chip L,quadratic dependence on Tr
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Decap size, position and noise amplitude
Decap 100m far hardly works.
Decap at current source works well.
1.18
1.185
1.19
1.195
1.2
1.205
1.21
1.215
0 50 100 150 200 250Time [ns]
Without decoupling capacitance
68.4pFat current source position
68.4pF100um far from current source
684pF100um far from current source
Decap position is important for noise suppressionwhen on-chip inductance is significant.
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Experimental setup(realistic power consumption) 0.13m technology, 1.2V supply voltage Chip size 6x6mm2, 100+100 bumps for P/G Each bump 0.5nH, 1 PG wires: pitch 300m, width 30m, thickness 1m Full PEEC model: all mutual inductances considered Half area is occupied by NAND2 gates Power consumption models
Uniform: 20% of transistors switching uniformly Unbalance: 50% of transistors switching at center, and 10% at perip
hery. Total power consumption is the same with uniform case Current transition time Tr: 50ps
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Power consumption distribution and power noise
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
25 25.5 26 26.5 27Time [ns]
Without on-chipinductance
With on-chipinductance
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
25 25.5 26 26.5 27Time [ns]
Without on-chipinductance
With on-chipinductance
Uniform power dissipation Unbalance power dissipation
on-chip L effect small on-chip L effect significant
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Why on-chip L hardly affects voltage fluctuation
When load currents are the same orenough decap is available at each grid,
current flowing through branch is very small.
These inductances hardly affect voltage fluctuation.
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Decap placement and power noise
1
1.05
1.1
1.15
1.2
1.25
1.3
25 25.2 25.4 25.6 25.8 26Time [ns]
Decoupling capacitance 100%
Decoupling capacitance 25%
Solid line: without on-chip inductanceDashed line: with on-chip inductance
1
1.05
1.1
1.15
1.2
1.25
1.3
25 25.2 25.4 25.6 25.8 26Time [ns]
Decoupling capacitance 25%
Decoupling capacitance 100%
Solid line: without on-chip inductanceDashed line: with on-chip inductance
Uniform decap placement Adaptive decap placement
not work efficientlyon-chip L effect large
work wellon-chip L effect small when decap is enough
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Comparison between PEEC and decoupled models
0.85 0.9
0.951
1.05 1.1
1.15 1.2
1.25 1.3
1.35 1.4
25 25.5 26 26.5 27Time [ns]
PEECDecoupled
Uniform powerconsumption
Unbalanced powerconsumption
When paired PG wires arecoupled perfectly, self-inductance L-M,mutual-inductance 0(decoupled model)
Difference exists, yet not significant.Decoupled model is used for larger grid analysis.
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Grid pitch and power noise
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
25 25.5 26 26.5 27Time [ns]
300um pitch
50um pitch
Wire area is fixed to 20%.
240
250
260
270
280
290
300
310
50 100 150 200 250 300N
oise
vol
tage
[m
V]
Grid pitch [um]
Noise voltage is reduced as grid pitch decreases.
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Wire area and power noise
Wire area increase reduces noise, yet not drastically.
Finer grid is more efficient than large wire area.
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
25 25.5 26 26.5 27Time [ns]
20%
50%
20%50%
With on-chipinductance
Without on-chipinductance
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
25 25.5 26 26.5 27Time [ns]
20%
50%20%
50%With on-chipinductance
Without on-chipinductance
Grid pitch 300m Grid pitch 50m
10% reduction 7% reduction
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Conclusion
Evaluated effects of on-chip inductanceDecap position is importantNon-uniform power consumption distribution i
ncreases effects of on-chip L Adaptive decap insertion based on local powe
r consumption mitigates on-chip L effectsGrid pitch is more important than wire area for
improving power grid robustness.