SETIT 2005 3rd International Conference: Sciences of Electronic,

Technologies of Information and Telecommunications March 27-31, 2005 – TUNISIA

Effects of electrical stress on switching behaviour of VDMOSFETs *C. SALAME, **R. HABCHI, **P. MIALHE

* CEA-LPSE, Faculty of SciencesII, 90656 Jdeidet El Mten, Lebanon ** LP2A, 52 av de Paul Alduy, 66860 Peprignan cedex, France

salame@ieee.org mialhe@univ-perp.fr

** LP2A, 52 av de Paul Alduy, 66860 Peprignan cedex, France habchi_7@hotmail.com

Abstract: The aim of this paper is to provide specific information on the effects of DC voltage stress on the current, rise time (Tr) and fall time (Tf), at switching between on and off state of a power n-MOSFET devices. A constant positive electrical stress voltage technique is used to study the devices in this work by positively bias the gate with respect to source and short circuit the drain with the grounded source. Voltage stress is gradually increased by automatic 1 volt step until reach the max tolerated value by the gate dielectric (70V for device studied in this paper). Response of the device for electrical stress were measured for different doses (stress t ime) The experimental results show that the rise time increases the beginning of stress dose and then it almost stabilised with time, while fall time decreases at first then starts to increase for higher stress time. The Modification of the device switching time parameters were associated to positive oxide charges and interface states Si/SiO2 effects. This paper offers new information concerning very important field in microelectronic devices where the switching speed of the components become a major requirement. The technique used to improve the device speed has a very low cost and a simple feasibility. Key words: Switching time, electrical stress, MOSFET, oxide charges

1 Introduction Although the problem of electron transport through broken down dielectric layers in metal–oxide–semiconductor (MOS) devices has been studied for more than about four decades [1],[2], no one has ever discussed the effect of this degradation on the switching delay times in power MOSFETs. In [3] E. Miranda and J.Suné have given an overview of a variety of available degradation models and aspects of breakdown mechanisms. However, despite more than 30 years of research on this subject, even the basic mechanisms of degradation remains an essentially empirical process [4]. Even with the huge amount of publications [5], [6], [7], no consensus has been reached and no clear and convincing theory has been established yet to explain the real mechanism of oxide and channel degradation. Many stress techniques have been proposed by various researchers, but in this paper we will present experimental results on the effects of electrical constant voltage stress (CVS) on the switching delay times in power VDMOSFETs devices witch could be essential to predict device lifetime in high frequency functioning circuits.

2 Experimental set-up Studied devices were BUZ 71 n-channel VDMOSFETs commercialized in a TO220 package, with a drain-source breakdown voltage of 50V, and a gate to source voltage of 20V. Devices were tested with a constant voltage stress (CVS) up to 63 V on the gate electrode while source and drain electrodes were grounded. Voltage transient times were measured both before and after each time of stress. The circuit in this measurement is presented in figure 1. A square signal of 10V was applied on the gate electrode, the 10V are considered enough to induce a conductive channel between drain and source, and a 30V constant voltage was applied on the drain electrode, witch represents 60% of the breakdown voltage, with the source grounded. A function generator supplied the gate signal with a frequency of 400 Hz.

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Figure1. Switching time test circuit

Figure1. Switching time test circuit

2.2 Results and discussions

When gate signal is at 0V, no accumulation occurs in the channel below the oxide region, so drain-source voltage is stable at 50V. But when gate signal reaches 10V, the channel is created and current flows from drain to source, witch leads the drain-source voltage to decrease down to 0V. The time between 90% and 10% of this of this fall, or the current rise time, is measured for different times of stress and plotted in figure 2. The rise time is increasing at the first dose of stress indicating a positive charge building up in the oxide bulk. The accumulated positive charge leads to a larger channel witch increases the time needed to fill it with electrons. Then interface degradation becomes dominant and Tr starts to stabilize.

Figure 2. Drain to source current rise time versus

stress time Figure 3 shows the current fall time variation versus stress time. It is shown for the studied device that Tf begins to decrease at the first 30 minutes of degradation because the wider channel created by the oxide positive charges evacuates charges faster when gate tension is cut off. But with stress time increasing, interface states begin to dominate and then charges mobility is decreasing, leading to an increase in Tf values.

figure3. Drain to source current fall time versus stress time Td (on) witch is defined to be the time between 90% of V (ds) fall and 10% of V (gs) rise, is plotted in figure 4. Also Td (off) witch is defined to be the time between 90% of V (gs) fall and 10% of V (ds) rise, is measured and plotted in figure 5. Variations of both Td (on) and Td (off) indicate a large accumulation of positive charges in thick oxide (IRF520) at the beginning of stress and interface degradation for larger stress doses.

Figure 4. Td (on) versus stress time

Figure 5. Td (off) versus stress time

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In order to investigate the effect of oxide thickness on MOSFET characteristics, the same measurements were performed on another device with a thinner gate oxide layer. The second device is an IRL3215 with a gate to source maximum voltage of 16V. The evolution of the second device’s rise time is shown in figure 6. For IRL3215, the initial increasing in Tr is not observed. This means that in thinner oxide, positive charge accumulation is less observed. Transport in thin oxides is ballistic witch means that most of the electron energy is deposed at the electrode and not in the oxide bulk. In this case, the principal defects are created at the interface region were negative charges are accumulated.

Figure 6. Drain to source current rise time versus stress time

The fall time represented in fig.7 also indicates that oxide charge accumulation in thin oxides is not very much observed. It is shown for IRL3215 that Tf begins to increase at the first moments of degradation, and measurements are not revealing physical evidence of an oxide positive charge

Figure7. Drain to source current fall time versus

stress time Td (on) and Td (off) are shown for thin oxide in figures 8 and 9.

Figure 8. Td (on) versus stress time

Figure 9. Td (off) versus stress time

Conclusion This study shows the device switching time variation with different doses of constant voltage stress. Two devices with different oxide thicknesses were studied. In thicker oxide, the current rise time increase indicates a large accumulation of oxide charges in the early stages of stress witch is also indicated by the decrease of the current fall time. Larger doses of stress generate interfacial states leading to the increase of Tf. In the thinner oxide device, it is shown that the current fall time is beginning to increase from the first doses of stress witch indicates the absence of oxide accumulation and the beginning of the interface degradation. It can be concluded that degradation of power MOSFETs is mainly due to the built up of charges in thick gate oxides, while in thinner oxides the degradation is caused by the deterioration of the interfacial properties.

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References [1] G. Dearnaley. Stored charge in oxide layer structures. Int. J. Electronics 29 (1970) 299-300 [2] Electrical breakdown of MOS structures and its dependence upon the oxidation process. Int. J. Electronics 26 (1969) 471-476 [3] E. Miranda, J. Suné. Electron transport through broken down ultra-thin SiO2 layers in MOS devices. Microelectronics Reliability 44 (2004) 1-23 [4] Hess K et al. Theory of channel hot-carrier degradation in MOSFETs. Physica B 272 (1999) 527-531 [5] R. Degraeve, B. Kaczer, G. Groeseneken. Degradation and breakdown in thin oxide layers: mechanisms, models and reliability prediction. Microelectronics Reliability 39 (1999) 1445-1460 [6] J.H.Chen, C.T.Wei, D.M.Hung, S.C.Wong, Y.H.Wang, Breakdown and stress induced oxide degradation mechanisms in MOSFETs. Solid-State Electronics 46 (2002) 1965-1974 [7] O.Ohata. Evaluation of performance degradation factors for high-k gate dielectrics in N-channel MOSFETs. Solid-State Electronics 48 (2004) 345-349