ees424 study unit 1

EES424 Specialisation © Johan Schoeman 2012 7/24/12 (1)

Study Unit 1: Digital Design Using VHDL and PLDs

Outcomes for the study unit

● Discuss digital systems and their modeling.● Discuss the various levels of abstraction using the Y-chart.● Discuss the VHDL/PLD design methodology.● Discuss the advantages of the VHDL/PLD design

methodology.● Discuss the concepts of VHDL for synthesis and VHDL for

simulation.


What is VHDL and why is it useful?

● An international IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide

● Acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

● Enable hardware modeling from the gate to the system level

● Provides a mechanism for digital design and reusable design documentation



Historical overview

● Early 1980's – VHSIC program by the U.S. DoD● VHDL originated from VHSIC● 1985 – U.S. DoD released VHDL for public use● 1987 – Modified version is standardized IEEE Std 1076-1987● 1988 – MilStd454 required that all ASICs be described in

VHDL● IEEE standard 1164 included signal drive strengths● IEEE standard 1076.1 for analog/mixed-signal extension● IEEE standard 1076.2 for real/complex data types● IEEE standard 1076.3 for signed/unsigned types (arithmetic)● 1993 – Second issue of IEEE 1076 with further updates in

2000, 2002, 2006 and 2008● 1997 – IEEE std 1076.6-1999 for RTL synthesis



Digital systems modeling

● What is a digital system?➢ Processes and stores data➢ Hierarchically composed system

● What are the advantages of this systematic approach?➢ Design independence of components➢ Design/information simplicity

● The term model➢ Our understanding of a system➢ Represents relevant information and abstracts away from

the irrelevant



Advantages of modeling digital systems

● Clarify user's requirements for the design engineer● Communicate understanding of the system's function to the

user● Allows for testing and verification of a design using

simulation● Allows for automatic synthesis of circuits● Allows for formal verification requiring a mathematical

statement describing the function of the system

We aim to achieve maximum reliability for minimum cost and design time



Levels and domains of abstraction



Levels and domains of abstraction (example)

Consider a single-chip microcontroller system used as the controller for some measurement instrument, with data input connections and some form of display for the outputs. The output is a scaled version of the input.



Example (cont.)

A possible functional/behavioral description on an algorithmic level could be



Example (cont.)

A possible structural description on a Processor-Memory-Switch (PMS) level could be



Example (cont.)

A possible geometrical description on the top level could be a silicon die floorplan



Example (cont.)

Second level of abstraction

Register Transfer Language Register Transfer



Component model of a digital (sub)system described by VHDL

Generics PortsEntity

Architecture

(Dataflow)

Architecture

(Behavioral)

Architecture

(Structural)

ConcurrentStatements

Process

Sequential Statements

ConcurrentStatements

Package



VHDL/PLD design methodology uses:

● VHDL to describe systems and testbenches

● Software simulation tool

● Software synthesis tool

● Software place-and-route tool

● PLD implementation

● Information in the configuration file to program the PLD



VHDL/PLD design flow



Advantages of the VHDL/PLD design methodology

● Ease the management of complex designs

● A single comprehensive design language

● A non-proprietary language

● Wide selection of tools

● Device independent design

● Rapid prototyping



Lexical elements: IdentifiersThey are used to name items

● May only contain alphabetic letters ('A' to 'Z' and 'a' to 'z'), decimal digits ('0' – '9') and the underline character ('_')

● Must start with an alphabetic letter (Port_1 vs 1_Port vs _Port)

● May not end with an underline character (Port_A vs PortA_)

● May not include two successive underline characters (Port__A)

Note that VHDL is not case sensitive



Lexical elements: Reserved wordsSome identifiers that are reserved for special use



Lexical elements: Special symbolsReserved and special symbols

● “ # & ' ( ) * + - , . / : ; < = > ? @ [ ] ` |

● => ** := /= >= <= <> ?? ?= ?/= ?> ?< ?>= ?<= << >>

Lexical elements: NumbersReal and integer literals exist

● 230, 45E3, 2#1101#

● 0.5, 5E-1, 8#0.4#, 3.141_592_6



Lexical elements: CharactersAny printable character enclosed in single quotation marks

● 'A', 'q'

● '@', '5'

Lexical elements: StringsAny printable characters enclosed in double quotation marks

● ''A string with printing characters (e.g., %$@&*)''● '''' -- an empty string● ''A string in a string: ''''A string''''. ''● ''If a string is too long, ''

& ''we can split it into separate lines. ''



Lexical elements: Bit StringsA string of bits

● B for binary● O for octal (base 8)● D for decimal (base 10)● X for hexadecimal (base 16)

Examples:

● B''0100011''● O''372'' -- equivalent to B''011_111_010''● D''23'' -- equivalent to B''10111''● X''A3--'' -- equivalent to B''10100011--------'' with don't cares


ees424 study unit 1

Documents

digital design

study unit

vhdl ieee standard

design engineer

digital hardware

dod vhdl

concepts of vhdl

vhdlpld design methodology