eel-3705 tps quizzes chapter 4. quiz 4-1 using the 2x4 decoder shown below and two-input or gates,...

EEL-3705TPS QUIZZES

Chapter 4

Quiz 4-1

Using the 2x4 Decoder shown below and two-input OR gates,

design a logic circuit which implements

,F a b a b

Solution

1 2,F a b ab ab m m

Quiz 4-2



, ,F a b c ab bc

Solution

, ,F a b c ab bc

F ab c c a a bc

F abc abc abc abc

, , 2, 4,5,6F a b c m

Solution

, , 2, 4,5,6F a b c m

Quiz 4-3



, , 0, 2,3,5,7F a b c M

Solution

, , 0, 2,3,5,7F a b c M , , 1, 4,6F a b c m

Quiz 4-4a

Using 3x8 Decoders with Active LOW Enables and NOT gates,

design a logic circuit which implements a 4x16 decoder

Solution

Quiz 4-4b

Using standard two-input and three-input logic gates, design an encoder

circuit that implements the following truth table

a b c y1 y0

1 d 1 0 1

d 1 0 1 0

0 0 d 1 1

Solution

abc 00 01 11 10

0

1

111

1

1Y ab bc

Y1

1Y ab bc

Solution

abc 00 01 11 10

0

1 11

1

1

0Y ab ac

Y0

0Y ab ac

Quiz 4-5

Using standard two-input logic gates, design a 2X1 MUX which

implements

0 1F SD SD Your circuit should have three inputs, Data inputs D0 and D1, and control input S.

Hint: Develop the truth table first

Solution

D1 D0 S F

d D0 0 D0

D1 d 1 D1

0 1F sD sD

Solution

Demonstrations

1 bit deep 2x1 MUX

2 Logical Data Inputs 1 bit deep

1 Control Input

1 Logical Output 1 bit deep

1 bit deep 4x1 MUX

4 Logical Data Inputs 1 bit deep

2 Control Inputs

1 Logical Output 1 bit deep

2 bits deep 2x1 MUX2 Logical Data Inputs 2 bits deep

1 Control Input

1 Logical Output 2 bits deep

2 bits deep 4x1 MUX

4 Logical Data Inputs 2 bits deep

2 Control Inputs


4 bits deep 2x1 MUX

2 Logical Data Inputs 4 bits deep

1 Control Input


Quiz 4-6

Using the 2X1 MUX shown below and NOT gates, design a logic

circuit which implements:

,F a b a b

Solution

F ab ab

0 1F sD sD

We need

We have

Let a=s, D0=b, D1=b

Quiz 4-7

Using standard two-input logic gates, design a 2X1 MUX with

Enable which implements

0 1n nF E SD E SD Your circuit should have four inputs, Data inputs D0 and D1, and control inputs E and S.

Solution

D1 D0 E S F

d d 0 d 0

d D0 1 0 D0

D1 d 1 1 D1

0 1n nF E SD E SD

Solution

Quiz 4-8

Design a 4x1 MUX using the 2x1 MUX with enable shown below,

NOT, and OR gates

0 1 2 3F D AB D AB D AB D AB Your design should implement this equation

Solution

Quiz 4-9

Using the 4x1 MUX shown below and NOT gates, design a logic

circuit which implements

F ab bc

Solution F ab a a bc

ab abc abc

1 0F ab ab c ab ab c

Quiz 4-10

Using the 4x1 MUX shown below and NOT gates, design a logic

circuit which implements

F a b c

Solution

F abc abc abc abc

3 2 1 0F m c m c m c m c ccccab

F

Class Design Project

Quiz 4-11

Module A

Design a logic circuit (let’s call this module A) which converts a three bit signed magnitude input into its

equivalent three bit two’s complement output. Let X2=0 indicate a positive number and X2=1 indicate a negative

number.X1 and X0 represent the magnitude of the number.

For example

Hint: Really this is a hint !!!, Develop the truth tablefor all possible input combinations

2 1 0 10 2101 1 111X X X

2 1 0 10 2011 3 011X X X

INPUT: X[2..0] OUTPUT: A[2..0]

Module A

SolutionX2 X1 X0 A2 A1 A0

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 0 0 0

1 0 1 1 1 1

1 1 0 1 1 0

1 1 1 1 0 1

Solution

2 2 1 2 0A X X X X

1 2 1 1 0 2 1 0A X X X X X X X

0 0A X

Solution

x2x1x0 00 01 11 10

0

1

11

11

1 2 1 1 0 2 1 0A X X X X X X X

Quiz 4-12

Module B

Design a logic circuit (let’s call this module B) which computes

where A is a three bit two’s complement input with a domain of -3 to 3.

Hint: This is really another hint!!!, Precompute B in decimal for each possible A and develop a truth table relating B to A in binary. Assume don’t care for B when |A| > 3.

2 1B A

How many bits are you going to need for B?

INPUT: A[2..0] OUTPUT: B[??..0]Module B

SolutionA2 A1 A0 B B3 B2 B1 B0

0 0 0 -1 1 1 1 1

0 0 1 1 0 0 0 1

0 1 0 3 0 0 1 1

0 1 1 5 0 1 0 1

1 0 0 D d d d d

1 0 1 -7 1 0 0 1

1 1 0 -5 1 0 1 1

1 1 1 -3 1 1 0 1

Solution

3 2 2 1 0 2 1 0B A A A A A A A

2 1 0B A A

0 1B

1 0B A

Solution

x2x1x0 00 01 11 10

0

1

11

1 1

2 1 0 1 0 1 0B A A A A A A

Quiz 4-13

Module C

Using Half Adders and NOT gates, design a logic circuit which will compute the 2’s comp of a 4-bit

signed binary number

INPUT: B[3..0] OUTPUT: C[3..0]Module C

Hint:

Calculate the 1’s complement and add 1.

Solution

Quiz 4-14

Module D

Using Module C (i.e. 2’s comp module) and the 4-bit wide 2X1 MUX shown below, design a logic circuit which will calculate the sign magnitude of a 4-bit 2’s complement number. You may assume maximum magnitude is 7. Your design should also havean output labeled sign which is sign=1 for negative values.

101111 1 001 1B D Sign

100011 3 011 0B D Sign

F sA sB Y A

INPUT: B[3..0] OUTPUT: D[2..0] Sign

Module D

Solution

Quiz 4-15

Class Design Project

We have the design for four modules:A: 4-bit Sign Magnitude to 2’s complementB: y=2x-1 for |X|<4C: 4-bit 2’s complement generatorD: 4-bit 2’s complement to Sign Magnitude

Team with two other groups.One group (X) should implement module AOne group (Y) should implement module BOne group (Z) should implement module C,DPick your groups and decide who is X,Y, and Z.

I will give a series of inputs to Group X, who should compute A =A[2..0] and give it to group Y, who then needs to compute B=B[3..0] and give it to group Z who then needs to compute D=D[2..0] and Sign. Group D should convert the result to decimal using a minus sign to represent a negative number and record it on the board. Use the index card to pass data from one module to the next.

Block Diagram

A B C/DX[2..0] A[2..0] B[3..0] D[2..0]

RecordResultsOn Board

FromDr. Perry Sign

X=000

1

X=100

2

X=001

3

X=101

4

X=011

5

X=111

6

Quiz 4-16

Let tgate=15ns, calculate the worst case delay for a 32-bit adder for the

three circuits below.

Circuit Delay

Ripple

Carry

(2n+1)tgate

Fully

Parallel

2*tgate

Carry

Look

Ahead

4*tgate

Let tgate=15ns, calculate the worst case delay for a 32-bit adder.

Circuit Delay Delay

Ripple

Carry

(2n+1)tgate 65*15ns=975ns

Fully

Parallel

2*tgate 2*15ns=30ns

Carry

Look

Ahead

4*tgate 4*15ns=60ns

Quiz 4-17

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ADD=0,

what is S in ADDER module in hex and decimal?

ADDER

INV2x1MUX

A

B

S

B

B

A

S Cin

A

Add

Given the 4-bit add/sub module shown below, let A=$D, B=$F, ,

what is S?

ADDER

INV2x1MUX

A

B

S

B

B

A

S Cin

A

Add

$D+$F=$C-3+(-1)=-4

0_______

ADD

Quiz 4-18


what is S in hex and decimal?

ADDER

INV2x1MUX

A

B

S

B

B

A

S Cin

A

Add


what is S?

ADDER

INV2x1MUX

A

B

S

B

B

A

S Cin

A

Add

$D-$F=$E-3-(-1)=-2

Quiz 4-19

Overflow/Underflow Detection

, 1 , 1in n out nV c c

• Recall

• That is, if for the MSB carry_in is not equal to carry_out, overflow or underflow has occurred.

Given a 4-bit adder, indicate whether each operation below gives an overflow(O), underflow(U), or correct (OK) answer.

• 1. $D+$4

• 2. $6 +$4

• 3. $7 + $A

• 4. $F + $F

• 5. $8 + $F


• 1. $D+$4 = $1 (OK)

• 2. $6 +$4 = $A (O)

• 3. $7 + $A = $1 (OK)

• 4. $F + $F = $E (OK)

• 5. $8 + $F = $7 (U)

Quiz 4-20


• 1. $D-$7

• 2. $6 -$4

• 3. $7 - $A

• 4. $F - $F

• 5. $8 - $1


• 1. $D-$7=$6 (U)

• 2. $6 -$4 = $2 (OK)

• 3. $7 - $A = $D (O)

• 4. $F - $F = $0 (OK)

• 5. $8 - $1 =$7 (U)

Quiz 4-21

Develop the truth table fora 2 bit signed comparator?

• Your truth table should have four inputs • b1 b0 a1 a0 and three outputs• F1= (A<B)• F2 = (A > B)• F3 = (A = B)

• Assume 2-bit signed (i.e. 2’s comp) values• Hint: convert to decimal and compare

Solutionb1 b0 a1 a0 A<B A>B A=B

0 0 0 0 0 0 1

0 0 0 1 0 1 0

0 0 1 0 1 0 0

0 0 1 1 1 0 0

0 1 0 0 1 0 0

0 1 0 1 0 0 1

0 1 1 0 1 0 0

0 1 1 1 1 0 0

Solutionb1 b0 a1 a0 A<B A>B A=B

1 0 0 0 0 1 0

1 0 0 1 0 1 0

1 0 1 0 0 0 1

1 0 1 1 0 1 0

1 1 0 0 0 1 0

1 1 0 1 0 1 0

1 1 1 0 1 0 0

1 1 1 1 0 0 1

Quiz 4-22

Let A=$C and B=$7and S[1..0]=00, what is F in hex?

OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

F[3..0]

Let A=$C and B=$7and S[1..0]=00, what is F?

OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

F[3..0]

AND OperationF=$04

Quiz 4-23

Let A=$C and B=$7and S[1..0]=10, what is F in hex?

OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

F[3..0]


OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

F[3..0]

NOT A OperationF=$03

Quiz 4-24

Let A=$C and B=$7and S[1..0]=11, what is F hex?

OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

F[3..0]


OR

NOT

XOR

AND

A

B

C

D

4X1

F

S[1..0]

S1 S0

A

A

B

F

A

B

F

A

B

F

A F

B

F[3..0]

XOR OperationF=$0B

Quiz 4-25

Let A=$3 and B=$4,S[1..0]=00, What is F in hex?

Add/SubModule

S0

A

B

Add

S

S

2X1

A

B

FVDD

S1

B

A

S


Add/SubModule

S0

A

B

Add

S

S

2X1

A

B

FVDD

S1

B

A

S

F=A+BF=$070 0

Quiz 4-26


Add/SubModule

S0

A

B

Add

S

S

2X1

A

B

FVDD

S1

B

A

S


Add/SubModule

S0

A

B

Add

S

S

2X1

A

B

FVDD

S1

B

A

S

F=A+1F=$040 0

eel-3705 tps quizzes chapter 4. quiz 4-1 using the 2x4 decoder shown below and two-input or gates,...

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