eee 416 lecture one

8/2/2019 Eee 416 Lecture One

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Introduction to VLSI DesignEEE 416

Dr. Mohammad Al Hakim


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Module Aims Introduction to VLSI Technology

Process Design

Trends

Chip Fabrication

Real Circuit Parameters Circuit Design

Electrical Characteristics

Configuration Building Blocks

Switching Circuitry

Translation onto Silicon CAD

Practical Experience in Layout Design


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Learning Outcomes

Understand the principles of thedesign and implementation of

standard MOS integrated circuitsand be able to assess theirperformance taking into account

the effects of real circuitparameters


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Laboratory

Microwind layout and simulationpackage

DSCH logic level simulator

Dedicated to training in sub-micronCMOS VLSI design

Layout editor and electrical circuitextractor


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Why VLSI?

Integration improves the design

Lower parasitics = higher speed

Lower power consumption

Physically smaller

Integration reduces manufacturing

cost - (almost) no manualassembly


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Moores Law

Gordon Moore: co-founder of Intel

Predicted that the number of

transistors per chip would growexponentially (double every 18months)

Exponential improvement intechnology is a natural trend:

e.g. Steam Engines - Dynamo -

Automobile


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What is a Silicon Chip?

A pattern of interconnected switches and gates on thesurface of a crystal of semiconductor (typically Si)

These switches and gates are made of

areas of n-type silicon

areas of p-type silicon

areas of insulator

lines of conductor (interconnects) joining areas together

Aluminium, Copper, Titanium, Molybdenum, polysilicon,

tungsten The geometryof these areas is known as the layout of

the chip

Connections from the chip to the outside world aremade around the edge of the chip to facilitate

connections to other devices


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Semiconductors and

Doping Adding trace amounts of certain materials to

semiconductors alters the crystal structure and canchange their electrical properties in particular it can change the number of free electrons

or holes N-Type

semiconductor has free electrons dopant is (typically) phosphorus, arsenic, antimony

P-Type semiconductor has free holes dopant is (typically) boron, indium, gallium

Dopants are usually implanted into thesemiconductor using Implant Technology, followedby thermal process to diffuse the dopants


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Metal-oxide-semiconductor(MOS) and related VLSI

technology

pMOS

nMOS CMOS


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Basic MOS Transistors

Minimum line width

Transistor cross section

Charge inversion channel

Source connected to substrate

Enhancement vs Depletion modedevices

pMOS are 2.5 time slower thannMOS due to electron and holemobilities


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Fabrication Technology

Silicon of extremely high purity

chemically purified then grown into large crystals

Wafers

crystals are sliced into wafers wafer diameter is currently 150mm, 200mm, 300mm

wafer thickness


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Fabrication Technology

Different parts of each die will bemade P-type or N-type (small

amount of other atomsintentionally introduced - doping-implant)

Interconnections are made withmetal

Insulation used is typically SiO2.SiN is also used. New materials

being investigated (low-k


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Typical fabrication centre


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Different MOS architectures

eee 416 lecture one

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