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EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1

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Page 1: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

EECS 388: Embedded Systems

4. I/O Interface

Heechul Yun

1

Page 2: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Agenda

• Memory mapped I/O

• I/O interfaces

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Page 3: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Input/output (I/O) Devices

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Page 4: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Input/output (I/O) Devices

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Page 5: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Input and Output (I/O) Interfaces

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CPUCore

MemoryDevices

I/OControllers

Interconnect

Computer

Input devices(e.g. sensor)

Output devices(e.g., motor)

OtherComputers

External:GPIO, UART, USB, I2C, SPI, CAN, ATA, PCI, WiFi, Ethernet, …

Internal:AXI, TileLink, …

Page 6: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

How Does CPU Talk to Devices?

• CPU talks to device controllers

– Via memory mapped I/O

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CPUCore

MemoryDevices

I/OControllers

Interconnect

Computer

Input devices(e.g. sensor)

Output devices(e.g., motor)

OtherComputers

Page 7: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Memory Mapped I/O

• Parts of physical memory space are mapped to hardware controllers (peripherals)

– Mapped to control registers and buffers

• Reading/writing from/to the memory mapped regions in peripheral specific ways

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Page 8: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Memory Mapped I/O

• Via system bus (CPU – memory or I/O device)

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Address Signals

Data Signals

Control Signals

AddressDecoder

ControlCircuitry

Data,Status, and

Control Registers

I/O Device

I/O Interface

Bus{

}

Page 9: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

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Memory Map ofSiFive FE310

CPU: 32 bit RISC-VClock: 320 MHzSRAM: 16 KB (D)Flash: 4MB

Memory mapped I/O regions

Page 10: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

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Memory Map ofSiFive FE310

GPIO registers are mapped at0x10012000 – 0x10012FFF

Page 11: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Memory Mapped I/O: Example

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Page 12: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

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Memory Map ofSiFive FE310

UART0 registers are mapped at0x10013000 – 0x10013FFF

Page 13: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Volatile in C

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a4 = 0x10013000

Branch to .L17 if a5 < zero

a5 = *a4

Page 14: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Volatile in C

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Is this correct?

a4 = 0x10013000

Branch to .L17 if a5 < zero

a5 = *a4

Page 15: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Input and Output (I/O) Interfaces

15

CPUCore

MemoryDevices

I/OControllers

Interconnect

Computer

Input devices(e.g. sensor)

Output devices(e.g., motor)

OtherComputers

External:GPIO, UART, USB, I2C, SPI, CAN, ATA, PCI, WiFi, Ethernet, …

Internal:AXI, TileLink, …

Page 16: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

External I/O Interfaces

16HiFive1 Rev B Pinout

Page 17: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

General Purpose I/O (GPIO)

• Programmable digital input/output pins

• Use voltage levels to represent digital signals

– 5V = logic 1 (for 5V CPUs)

– 0V = logic 0

• Can be configured as

– Input or output

• Useful to interact withexternal devices

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Page 18: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

3V VDD

Example: Turn on an LED

• Assume a GPIO pin can draw up to 18mA, and when the LED is on, it has a voltage drop of 2V

• Ohm’s law: 𝐼 × 𝑅 = 𝑉

• What registor is needed?

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Page 19: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

3V VDD

Example: Turn on an LED

• Assume a GPIO pin can draw up to 18mA, and when the LED is on, it has a voltage drop of 2V

• Ohm’s law: 𝐼 × 𝑅 = 𝑉

• What registor is needed?

I = V / R = 1 / R < 18mA

R > 1V/18mA

= 1000mV/18mA= 56 ohm

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Page 20: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Serial vs. Parallel

• Serial communication

– use single line

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01001001

010010010 1 0 0 1 0 0 1

Sender Receiver

Page 21: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Serial vs. Parallel

• Parallel communication

– use multiple lines

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01001001

01001001

Sender Receiver

01001001

Page 22: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Serial vs. Parallel Interfaces

• Serial interfaces– RS-232: serial communication standard– USB: universal serial bus– I2C: inter-integrated circuit– SPI: serial peripheral interface bus– SATA: serial ATA– …

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SATA USB RS-232I2C

Page 23: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Serial vs. Parallel Interfaces

• Parallel interfaces

– Parallel ATA: advanced technology attachment

– SCSI: small computer system interface

– PCI: peripheral component interface

– …

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PCI SCSI PATA Parallel port

Page 24: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Serial vs. Parallel Interfaces

• Are parallel interfaces better?++ better performance for the same clock speed

--- synchronization among the wires at high speed

• Serial interfaces are increasingly popular for external i/o (e.g., USB, SATA, PCIe, …)

• Parallel interfaces are dominant for internal interconnect within chip where clock synchronization is easier (e.g., AXI, TileLink, ..)

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Synchronous vs. Asynchronous

• Synchronous communication– Requires a common shared clock– Higher throughput, low overhead. – All parallel communications are synchronous – Synchronization difficulties.

• Asynchronous communication– No shared clock.– Asynchronous start/stop – Self clocked w.r.t. agreed up on speed– High overhead

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Page 26: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

RS-232

• Asynchronous serial communication standard from 1960s, but still widely used

26This Photo by Unknown Author is licensed under CC BY-SA

Page 27: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

UART

• Universal asynchronous receiver/transmitter

• Convert parallel data to serial data (vice versa)

• Can be configured to implement various serial protocol (e.g., RS-232)

• Require at least TX and RX lines to function

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Page 28: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

UART Speed (Baudrate)

• Both sender and receiver must use agreed upon transmission speed (baudrate)

• Up on detecting the start bit, the receiver sample 8 more times before stop

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Page 29: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Point-to-Point vs. Bus

• Point-to-point– 1:1 communication

• Bus– Shared among multiple devices

– Need an arbitration mechanism

– Master• An entity who initiates the data transfer

– Slave• An entity who cooperates with the master

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Page 30: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

I2C

• Inter-integrated circuit protocol (I2C), by NXP• Synchronous serial communication protocol• Use two wires (SCL - clock, SDA - data)• Multi-master, multi-slave support• Use 7bit ID. Connect up to 127 devices.• Half duplex, relatively slow

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This Photo by Unknown Author is licensed under CC BY-SAThis Photo by Unknown Author is licensed under CC BY-SA

Page 31: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

SPI

• Serial peripheral interface (SPI), by Motorola

• Synchronous serial communication protocol

• Use 4 lines, full-duplex, (relatively) fast

• Single master, multi-slave

• No start/stop bits

• Good for fast, short distance communication

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This Photo is licensed under CC BY-SA

Page 32: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

USB

• Universal serial bus• One host, multiple devices, can form a tree• Use two wires for single differential signal

– Reduce noise caused by electromagnetic interference

• Device needs to process the protocol messages

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https://commons.wikimedia.org/wiki/File:USB_signal_example.svg#/media/File:USB_signal_example.svg

Page 33: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

I/O Considerations

• Digital vs. analog

• Serial vs. parallel

• Wired vs. wireless

• Speed (throughput, latency)

• Real-time/QoS guarantees

• Power/Electrical requirements

• Reliability, Security

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Page 34: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Summary

• Memory mapped I/O– Parts of physical memory space are mapped to

hardware controllers (peripherals)

– Reading/writing from/to the memory mapped regions in peripheral specific ways

• I/O interfaces– GPIO, UART, SPI, I2C, USB, …

– Serial vs parallel

– Asynchronous vs synchronous

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Page 35: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Quiz

• Suppose you are sending data over a UART channel at a baud rate of 115200 bps. How long does it take to send a single 8 bit character over the channel?

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Page 36: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Quiz

• How many CPU cycles would be needed to execute the busy-wait loop in the worst-case? Assume that that the CPU is running at 1 MHz and the baud rate is set at 9600 bps?

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a4 = 0x10013000

Branch to .L17 if a5 < zero

a5 = *a4

Page 37: EECS 388: Embedded Systemsheechul/courses/eecs388/W4.ioif.pdf · EECS 388: Embedded Systems 4. I/O Interface Heechul Yun 1. Agenda •Memory mapped I/O •I/O interfaces 2. Input/output

Acknowledgements

• Some slides are based on the material originally developed by

– Edward A. Lee and Prabal Dutta (UCB) for EECS149/249A

– Rodolfo Pellizzoni (U. Waterloo) for ECE224

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