eecs 312 discussion
TRANSCRIPT
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Overview
• Reminder
– HW 2: Due Oct 10
– Midterm: 8 October 19:00–20:30 in 1670 BBB
– Close book. One sheet note.
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NMOS
G
S D
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A unified model
1. If VDS is minimum: Linear region
2. If VGT is minimum: Saturation Region 3. If VDSAT is minimum : Velocity saturated region
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NMOS
G
S D
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CMOS Process
Cross-Sectional View
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3 Dimensional View
Layout View
Width
Channel Length
Channel Length
Width
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Inverter Layout
Width
Channel Length
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NMOS
G
S D
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5 Important MOSFET Capacitances
DS
G
B
CGDCGS
CSB CDBCGB
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Gate-to-channel Capacitance (CGC)
S D
G
CGC
S D
G
CGC
S D
G
CGC
Cut-off Resistive Saturation
CGCB
CGCS
CGCD
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Properties of Static CMOS gates
• Voltage swing=supply voltage (full swing)
• Logic level is not dependent upon the relative device sizes (ratioless)
• A path with finite resistance between the output and VDD or GND
• Input resistance is extremely high
• No direct path exists between supply and ground under steady-stage
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CMOS inverter- Intuitive Perspective
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Power
• Dynamic Power
• Static Power
• Short-Circuit Power *
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Power