EECS 150 Fa04 Lecture 2

1

1

EECS 150 - Components and Design Techniques for Digital Systems

Lec 02 – CMOS Technology9-2-04

David CullerElectrical Engineering and Computer Sciences

University of California, Berkeley

http://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs150

2

Outline

• Summary of last time• Overview of Physical Implementations• CMOS devices• Announcements/Break• CMOS transistor circuits

– basic logic gates– tri-state buffers– flip-flops

» flip-flop timing basics» example use» circuits

3

We will learn in CS 150 …

• Language of logic design– Logic optimization, state, timing, CAD tools

• Concept of state in digital systems– Analogous to variables and program counters in software systems

• Hardware system building– Datapath + control = digital systems

• Hardware system design methodology– Hardware description languages: Verilog– Tools to simulate design behavior: output = function (inputs)– Logic compilers synthesize hardware blocks of our designs– Mapping onto programmable hardware (code generation)

• Contrast with software design– Both map specifications to physical devices– Both must be flawless…the price we pay for using discrete math

4

What is logic design?

• What is design?– Given problem spec, solve it with available components– While meeting criteria for size, cost, power, beauty, elegance, etc.

• What is logic design?– Choose digital logic components to perform specified control, data

manipulation, or communication function and their interconnectio n– Which logic components to choose?

Many implementation technologies (fixed -function components, programmable devices, individual transistors on a chip, etc.)

– Design optimized/transformed to meet design constraints

5Source: Microsoft Encartasense

sensedrive

AND

What is digital hardware?

• Devices that sense/control wires carrying digital values (physical quantity interpreted as “0” or “1”)– Digital logic: voltage < 0.8v is “0”, > 2.0v is “1”– Pair of wires where “0”/“1” distinguished by which has higher

voltage (differential)

– Magnetic orientation signifies “0” or “1”

• Primitive digital hardware devices– Logic computation devices (sense and drive)

» two wires both “1” - make another be “1” (AND)» at least one of two wires “1” - make another be “1” (OR)» a wire “1” - then make another be “0” (NOT)

– Memory devices (store)

» store a value» recall a value previously stored

6

Overview of Physical Implementations

• Integrated Circuits (ICs)– Combinational logic circuits, memory elements, analog interfaces.

• Printed Circuits (PC) boards– substrate for ICs and interconnection, distribution of CLK, Vdd, and

GND signals, heat dissipation. • Power Supplies

– Converts line AC voltage to regulated DC low voltage levels. • Chassis (rack, card case, ...)

– holds boards, power supply, provides physical interface to user or other systems.

• Connectors and Cables.

The stuff out of which we make systems.

EECS 150 Fa04 Lecture 2

2

7

Integrated Circuits• Primarily Crystalline Silicon• 1mm - 25mm on a side• 100 - 200M transistors

• (25 - 50M “logic gates")• 3 - 10 conductive layers• 2002 - feature size ~ 0.13um = 0.13 x 10 -6 m • “CMOS” most common -

complementary metal oxide semiconductor

• Package provides:– spreading of chip-level signal paths to

board -level – heat dissipation.

• Ceramic or plastic with gold wires.

Chip in Package

8

Printed Circuit Boards

• fiberglass or ceramic• 1-20 conductive layers • 1-20in on a side • IC packages are soldered

down.

Multichip Modules (MCMs)

• Multiple chips directly connected to a substrate. (silicon, ceramic, plastic, fiberglass) without chip packages.

9

Integrated Circuits

• Moore’s Law has fueled innovation for the last 3 decades.

• “Number of transistors on a die doubles every 18 months.”

• What are the side effects of Moore’s law? 10

Integrated Circuits

• Uses for digital IC technology today:– standard microprocessors

» used in desktop PCs, and embedded applications» simple system design (mostly software development)

– memory chips (DRAM, SRAM)

– application specific ICs (ASICs)» custom designed to match particular application» can be optimized for low-power, low -cost, high-performance» high-design cost / relatively low manufacturing cost

– field programmable logic devices (FPGAs, CPLDs)» customized to particular application after fabrication

» short time to market» relatively high part cost

– standardized low-density components» still manufactured for compatibility with older system designs

11

close switch (if A is “1” or asserted)and turn on light bulb (Z)

A Z

open switch (if A is “0” or unasserted)and turn off light bulb (Z)

Switches: basic element of physical implementations

• Implementing a simple circuit (arrow shows action if wire changes to “1”):

Z ≡ A

AZ

12

CMOS Devices

Cross Section

The gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a voltage exists between the source and drain a current will flow. In its simplest approximation the device acts like a switch.

Top View

• MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

nFET

pFET

EECS 150 Fa04 Lecture 2

3

13

What Complementary about CMOS?

• Complementary devices work in pairs

n-channelopen when voltage at G is low

closes when:voltage(G) > voltage (S) + ε

p-channelclosed when voltage at G is low

opens when:voltage(G) < voltage (S) – ε

G

S D

G

S D

14

Transistor-level Logic Circuits (inv)

• Inverter (NOT gate):Vdd

Gnd

Vdd

Gnd0 volts

in out

3 volts

what is the relationship

between in and out?

15

Logical Values

• Threshold– Logical 1 (true) : V > Vdd –V th– Logical 0 (false) : V < Vth

• Noise margin?

V

+3

0

Logic 1

Logic 0

V out

+3

0

Logic 0Input Voltage

Logic 1Input Voltage

V in+5

F

in out

T

T

F

not( out, in)

16

Big idea: Self-restoring logic

• CMOS logic gates are self-restoring– Even if the inputs are imperfect, switching time is fast and

outputs go rail to rail– Doesn’t matter how many you cascade

» Although propagation delay increases

• Manage fan-out to ensure sharp and complete transition

17

Element of Time

• Logical change is not instantaneous• Broader digital design methodology has to make it appears

as such– Clocking, delay estimation, glitch avoidance

V out

+3

0V in

+5

Propagation delay

18

Announcements

If you are on the wait list and would like to get into the class you must:

• Turn in an appeal for on third floor Soda• Attend lectures and do the homework, the first two

weeks.

• In the second week of classes, go to the lab section in which you wish to enroll. Give the TA your name and student ID.

• Later, we will process the waitlist based on these requests, and lab section openings.

EECS 150 Fa04 Lecture 2

4

19

AnnouncementsuReading assignment for this week.uKatz and Boriello, Chap 1uChap 4 pp. 157-170

uHomework 1 is posted - due week from friday

20

AND

OR

Z ≡ A and B

Z ≡ A or B

A B

A

B

Computing with Switches

• Compose switches into more complex (Boolean) functions:

Two fundamental structures: series (AND) and parallel (OR)

21

Transistor-level Logic Circuits - NAND

• Inverter (NOT gate): • NAND gate

• Logic Function: – out = 0 iff both a AND b = 1

therefore out = (ab)’– pFETnetwork and nFET

network are duals of one another.

How about AND gate?

a b out

0 0 1

0 1 1

1 0 1

1 1 0

nand (out, a, b)

22

Transistor-level Logic Circuits

• nFET is used only to pass logic zero.

• pFet is used only to pass logic one.• For example, NAND gate:

Simple rule for wiring up MOSFETs:

Note: This rule is sometimes violated by expert designers under special conditions.

23

Transistor-level Logic Circuits - NOR

• NAND gate • NOR gate

• Function: – out = 0 iff both a OR b = 1 therefore

out = (a+b)’– Again pFET network and nFET

network are duals of one another.– Other more complex functions are

possible. Ex: out = (a+bc)’

a b out

0 0 1

0 1 0

1 0 0

1 1 0

nor (out, a, b)

24

Transistor-level Logic Circuits

• Transistor circuit for inverting tri-state buffer:

“high impedance” (output disconnected)

• Variations

• Tri-state Buffer

“transmission gate”Inverting buffer Inverted enable

Tri-state buffers are used when multiple circuits all connect to a common bus.Only one circuit at a time is allowed to drive the bus. All others “disconnect”.

EECS 150 Fa04 Lecture 2

5

25

Transmission Gate

• Transmission gates are the way to build “switches” in CMOS.

• Both transistor types are needed:– nFET to pass zeros.– pFET to pass ones.

• The transmission gate is bi-directional (unlike logic gates and tri-state buffers).

• Functionally it is similar to the tri-state buffer, but does not connect to Vdd and GND, so must be combined with logic gates or buffers.

Is it self restoring?26

Transistor-level Logic Circuits - MUX

• Multiplexor

If s=1 then c=a else c=b

• Transistor Circuit for inverting multiplexor:

27

Interactive Quiz

mux (c, s, a, b)• Generate truth table for MUX• Boolean expression?• Can you build an inverter out

of a MUX?• How about AND?

c

universality28

inputs outputssystem

Combinational vs. sequential digital circuits• Simple model of a digital system is a unit with

inputs and outputs:

• Combinational means "memory-less"– digital circuit is combinational if its output values

only depend on its inputs

29

easy to implementwith CMOS transistors(the switches we haveavailable and use most)

Combinational logic symbols

• Common combinational logic systems have standard symbols called logic gates

– Buffer, NOT

– AND, NAND

– OR, NOR

Z

AB

Z

Z

A

AB

30

Sequential logic

• Sequential systems– Exhibit behaviors (output values) that depend

on current as well as previous inputs

• All real circuits are sequential– Outputs do not change instantaneously after an input change– Why not, and why is it then sequential?

• Fundamental abstraction of digital design is to reason (mostly) about steady-state behaviors– Examine outputs only after sufficient time has elapsed for the

system to make its required changes and settle down

EECS 150 Fa04 Lecture 2

6

31

Synchronous sequential digital systems• Combinational circuit outputs depend only on

current inputs– After sufficient time has elapsed

• Sequential circuits have memory– Even after waiting for transient activity to finish

• Steady-state abstraction: most designers use it when constructing sequential circuits:– Memory of system is its state– Changes in system state only allowed at specific times

controlled by an external periodic signal (the clock)– Clock period is elapsed time between state changes

sufficiently long so that system reaches steady-state before next state change at end of period

32

Recall: What makes Digital Systems tick?

Combinational

Logic

time

clk

33

D-type edge-triggered flip-flop

• The edge of the clock is used to sample the "D" input & send it to "Q” (positive edge triggering).

– At all other times the output Q is independent of the input D (just stores previously sampled value).

– The input must be stable for a short time before the clock edge.

34

Parallel to Serial Converter Example

• 4-bit version:

• Operation:– cycle 1: load x, output x0

– cycle i: output xi

if LD=1 load FF from xielse from previous stage.

• Each stage:

35

Parallel to Serial Converter Example

• timing:

36

Transistor-level Logic Circuits - Latch

• Positive Level-sensitive latch

• Transistor Level • Positive Edge-triggered flip-flop built from two level-sensitive latches:

clk’

clk

clk

clk’

D FlipFlop

EECS 150 Fa04 Lecture 2

7

37

scope of CS 150

Summary: Representation of digital designs

• Physical devices (transistors, relays)• Switches

• Truth tables• Boolean algebra

• Gates• Waveforms

• Finite state behavior• Register-transfer behavior

• Concurrent abstract specifications

more depth than 61C

focus on building systems

38

Technology State 0 State 1

Relay logic Circuit Open Circuit ClosedCMOS logic 0.0-1.0 volts 2.0-3.0 voltsTransistor transistor logic (TTL) 0.0-0.8 volts 2.0-5.0 voltsFiber Optics Light off Light onDynamic RAM Discharged capacitorCharged capacitorNonvolatile memory (erasable) Trapped electrons No trapped electronsProgrammable ROM Fuse blown Fuse intactBubble memory No magnetic bubble Bubble presentMagnetic disk No flux reversal Flux reversalCompact disc No pit Pit

Mapping from physical world to binary world

Sense the logical value, manipulate in s systematic fashion.