ee309 microprocessors and embedded systems

EE309 Microprocessors and Embedded Systems

Internal Architecture of 8085

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed byIntel in 1977 using NMOS technology.

It has the following configuration −

8-bit data bus

16-bit address bus, which can address up to 64KB

A 16-bit program counter

A 16-bit stack pointer

Six 8-bit registers arranged in pairs: BC, DE, HL

Requires +5V supply to operate at 3 MHZ single phase clock

It is used in washing machines, microwave ovens, mobile phones, etc.

8085 Microprocessor – Functional Units

8085 consists of the following functional units −

Accumulator

It is an 8-bit register that is part of the ALU. The register is used to store 8 bit data and to performarithmetic and logical operations. The result of an operation is stored in the accumulator. Theaccumulator is also identified a register A

Arithmetic and logic unit (ALU)

As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND,OR, etc. on 8-bit data. It includes the accumulator, the temporary register, the ALU circuits & five flags.The temp register is used to hold data during an arithmetic and logical operation. The result is stored inthe accumulator and the flags are set or reset according to the result of the operation.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold8-bit data. These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,D-E & H-L. The programmer can use these registers to copy or store data into the register by using datacopy instructions.

Program counter

1 Module 1 Notes prepared by srikanth

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It is a 16-bit register used to store the memory address location of the next instruction to be fetched.Microprocessor increments the program whenever an instruction is being executed, so that the programcounter points to the memory address of the next instruction that is going to be fetched and executed.

Stack pointer

It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during push& pop operations. It points to the top of the stack. The beginning of the stack is defined by loading a 16bit address in the stack pointer.

Temporary register

2 additional registers, W and Z are included in the register array. These registers are used to hold 8 bitdata during the execution of some instructions. They are not available to the programmer.

Flag register

It is an 8 bit register. It consists of 5 flip flops which changes its status according to the result stored inan accumulator. 3 bits are not used. It is also known as status register. It is connected to the ALU.The five flag bits are: Sign(S), zero (z), Auxiliary carry (AC), Parity (P), Carry(C)The bit position of the flip flop in flag register is:

D7 D6 D5 D4 D3 D2 D1 D0S Z x AC x P x CY

Sign flag (S) - This flag is used with signed numbers. If D7 of the result in accumulator is 1 then signflag is set otherwise reset. As we know that a number on the D7 always decides the sign of the number.If D7 is 1: the number is negative and if D7 is 0: the number is positive. It is irrelevant for operations ofunsigned numbers.Zero flag (Z) - If the result stored in an accumulator is zero then this flip flop is set otherwise it is reset. Auxiliary Carry (AC) - If any carry goes from D3 to D4 in the output then it is set otherwise it isreset. Significant in BCD addition and subtractionParity flag (P) - If the no of 1's is even in the output stored in the accumulator then it is set otherwise itis reset for the odd. Carry flag (C) - If the result stored in an accumulator generates a carry from D7 in its final output thenit is set otherwise it is reset. Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory, it is loaded in the Instructionregister. Instruction decoder decodes the information present in the Instruction register. The instructionregister not programmable and cannot be accessed through any instruction.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations. Following are thetiming and control signals, which control external and internal circuits −


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Control Signals: READY, RD’, WR’, ALE

Status Signals: S0, S1, IO/M’

DMA Signals: HOLD, HLDA

RESET Signals: RESET IN, RESET OUT

Interrupt control

As the name suggests it controls the interrupts during a process. When a microprocessor is executing amain program and whenever an interrupt occurs, the microprocessor shifts the control from the mainprogram to process the incoming request. After the request is completed, the control goes back to themain program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, and TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID (Serial input data) andSOD (Serial output data).

Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the address buffer andaddress-data buffer to communicate with the CPU. The memory and I/O chips are connected to thesebuses; the CPU can exchange the desired data with the memory and I/O chips.

Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location towhere it should be stored and it is unidirectional.


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8085 PINS and their Functions - 40 pin DIP chip


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The device has 40 pins Requires a +5V single power supply, and can operate with a 3 MHz single phase clock.

The above figure shows the logic pinout of the 8085 microprocessor. All the signals can beclassified into 6 groups. (1)Address bus (2) Data bus (3) Control and status signals (4) power supplyand frequency signals (5) Externally initiated signals and (6) Serial I/O ports

Address & Data Bus8085 has 16 signal lines that are used as the address bus. These lines are split into 2 segments

A15-A8 and AD7-AD0 (multiplexed address/data bus). A15-A8 – unidirectional and used for the mostsignificant bits called the high order address of 16 bit address. AD7-AD0 – bidirectional and they areused as the low order address bus as well as the data bus.

Control & Status SignalsThese signals are used to identify the nature of operation. There are 3 control signals and 3 statussignals.Control Signals

1. ALE (output) - Address Latch Enable. Indicate a valid address on the bus. It is a positive goingpulse used to latch the address on the bus.

2. RD (Active low) - Read memory or IO device. This indicates that the selected memory

location or I/O device is to be read and that the data bus is ready for accepting data from thememory or I/O device

3. WR (Active low) - Write memory or IO device. This indicates that the data on the data bus is

to be written into the selected memory location or I/O device.


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Status Signals

1. IO/ M - Select memory or an IO device. This signal indicates that the read / write

operation relates to whether the memory or I/O device. It goes high to indicate an I/O operation and goes low for memory operations.

2. S1, S0 -It is used to know the type of current operation of the microprocessor.

Power Supply & Frequency Signals

Vcc: + 5 volt power supply and Vss:Ground X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal

clock generator. The frequency is internally divided by two. Since the basic operating timingfrequency is 3 MHz, a 6 MHz crystal is connected externally.

CLK (output)-Clock Output is used as the system clock for peripherals and devices interfaced

with the microprocessor.

Externally Initiated Signals, Including Interrupts

Direct Memory Access (DMA) signals: Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly.

1. HOLD signal is generated by the DMA controller circuit which request the control of systembus.

2. HLDA (Hold Acknowledge): On receipt of the HOLD signal, the microprocessoracknowledges the request by sending out HLDA signal and leaves out the control of the buses.After getting the HLDA signal the DMA controller starts the direct transfer of data.

READY (input): Memory and I/O devices will have slower response compared to

microprocessors. Ready input indicates that whether the memory or IO device is ready for a datatransfer. 1 indicates memory or IO device is ready for a data transfer and 0 indicate that they arenot ready. The microprocessor enters into WAIT state while the READY pin is 0.


IO/

M

S1 S0 OPERATION

0 1 1 Opcode fetch0 1 0 Memory read0 0 1 Memory write1 1 0 I/O read1 0 1 I/O write1 1 1 Interrupt acknowledgeZ 0 1 HaltZ x x HoldZ x x Reset

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Rest∈¿

¿ : This signal is used to reset the microprocessor. The program counter (PC) inside the

microprocessor is set to zero. Reset Out : It indicates CPU is being reset. It is used to reset all the connected devices when

the microprocessor is reset.

Serial Input Output Control signals- There are two pins in this unit. Used for serial datacommunication.

1. SID (input) - Serial input data line2. SOD (output) - Serial output data line

Interrupt control SignalsInterrupts are the signals generated by external devices to request the microprocessor to perform a task.There are 5 interrupt signals (hardware interrupts), i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

1. TRAP (Non Maskable, vectored interrupt)2. RST 7.5 (Maskable, vectored interrupt)3. RST 6.5 (Maskable, vectored interrupt)4. RST 5.5 (Maskable, vectored interrupt)5. INTR (Maskable, Non vectored interrupt)

INTA − It is an interrupt acknowledgment signal.

Instruction Set 8085

Data Transfer Instructions

Opcode Operand Explanation of Instruction

Description

MOVMOVMOV

Rd, RsM, RsRd, M

Copy data from the source (2nd operand) to destination (1st operand).

2 operandsCan be register or memory. The contents of the source arenot altered. If one of the operands is M (memorylocation), then the location is specified by the HL registerpair. Eg: MOV B, C ; B←CMOV B, M; B←(HL)(HL) = data in the memory location pointed by HL pair

MVIMVI

Rd, dataM, data

Move immediate 8-bit data to the destination specified

The source is always an 8-bit data. Destination can be aregister or memory. If the operand is a memory location,its location is specified by the contents of the HL registers.Example: MVI B, 57H ; B←57MVI M, 57H ; (HL)←57(HL) = memory location pointed by HL register pair

LDA 16-bit address Load accumulator with data given

Load – from memory to registerThe contents of a memory location, specified by a 16-bitdirect address in the operand, are copied to the


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inside the 16 bitaddress location

accumulator. The contents of the source are not altered.Example: LDA 2034H ; A← (2034)

LDAXLDAXLDAX

Reg. pairBD

Load accumulator with data from the memory location pointedby register pair.

The contents of the memory location pointed bydesignated register pair is copied into the accumulator.The contents of either the register pair or the memorylocation are not altered.Eg: LDAX B ; A←(BC)

LXI Reg. pair, 16-bit data Load register pair with immediate data

The instruction loads 16-bit data in the register pairdesignated in the operand.

Example: LXI H, 2034H ; H=20h L=34h

LHLD 16-bit address Load H and L registers with content of the memory location

The instruction copies the contents of the memorylocation pointed out by the 16-bit address into register Land copies the contents of the next memory location intoregister H.

Example: LHLD 2040HL= content of the memory location 2040hH= content of the memory location 2041h

STA 16-bit address Store the content of A in memory location given by 16-bit address

The contents of the accumulator are copied into thememory location specified by the operand. This is a 3-byte instruction, the second byte specifies the low-orderaddress and the third byte specifies the high-order address.

Eg: STA 4350H

STAX Reg. pair Store accumulator in the memory location pointedby reg pair (indirect)

The contents of the accumulator are copied into thememory location specified by the contents of the operand(register pair). The contents of the accumulator are notaltered.

Example: STAX B

SHLD 16-bit address Store H and L registers to the memory location whose address is specified directly

The contents of register L are stored into the memorylocation specified by the 16-bit address in the operand andthe contents of H register are stored into the next memorylocation by incrementing the operand. The contents ofregisters HL are not altered. Example: SHLD 2470H

XCHG -(no operand)

Exchange the content of H and L with D and E

The contents of register H are exchanged with the contentsof register D, and the contents of register L are exchangedwith the contents of register E.

Example: XCHG


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SPHL -(no operand)

Copy H and L registers to the stack pointer

The instruction loads the contents of the H and L registersinto the stack pointer register, the contents of the Hregister provide the high-order address and the contents ofthe L register provide the low-order address. The contentsof the Hand L registers are not altered. Example: SPHL

XTHL -(no operand)

Exchange H andL with top of stack

The contents of the L register are exchanged with thestack location pointed out by the contents of the stackpointer register. The contents of the H register areexchanged with the next stack location (SP+1); however,the contents of the stack pointer register are not altered.

Example: XTHL

PUSH Reg. pair Push register pair onto stack

The contents of the register pair designated in the operandare copied onto the stack in the following sequence. Thestack pointer register is decremented and the contents ofthe higher order register (B, D, H, A) are copied into thatlocation. The stack pointer register is decremented againand the contents of the low-order register (C, E, L, flagreg) are copied to that location.

Example: PUSH B or PUSH A

POP Reg. pair Pop off stack to register pair

The contents of the memory location pointed by the stackpointer register are copied to the low-order register (C, E,L, flag reg) of the operand. The stack pointer isincremented by 1 and the contents of that memorylocation are copied to the high-order register (B, D, H, A)of the operand. The stack pointer register is againincremented by 1.Example: POP H or POP A

OUT 8-bit port address Output data from accumulator to a port with 8-bitaddress

The contents of the accumulator are write to the outputport designated in the operand (8 bit address port)Example: OUT 80H

IN 8-bit port address Input data to accumulator from a port with8-bit address

The contents of the input port designated in the operandare read and loaded into the accumulator.

Example: IN 8CH

Arithmetic Instructions

Opcode

Operand Explanation of Instruction

Description

ADDADD

RM

Add register or memory, to accumulator

The contents of the operand (register or memory) are addedto the contents of the accumulator and the result is stored inthe accumulator. If the operand is a memory location, its


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location is specified by the contents of the HL registers. Allflags are modified to reflect the result of the addition.Example: ADD B ; A←A+BADD M ; A← A+ (HL)

(HL) = data in the memory location pointed by HL pair

ADCADC

RM

Add register to accumulator with carry

The contents of the operand (register or memory) and theCarry flag are added to the contents of the accumulator andthe result is stored in the accumulator. If the operand is amemory location, its location is specified by the contents ofthe HL registers. All flags are modified to reflect the resultof the addition. Eg: ADC B or ADC M

ADI 8-bit data Add immediate toaccumulator

The 8-bit data (operand) is added to the contents of theaccumulator and the result is stored in the accumulator. Allflags are modified to reflect the result of the addition.

Example: ADI 45H

ACI 8-bit data Add immediate toaccumulator with carry

The 8-bit data (operand) and the Carry flag are added to thecontents of the accumulator and the result is stored in theaccumulator. All flags are modified to reflect the result ofthe addition. Eg: ACI 45H

DAD Reg. pair Add register pair to H and L registers

The 16-bit contents of the specified register pair are addedto the contents of the HL register and the sum is stored inthe HL register. The contents of the source register pair arenot altered. If the result is larger than 16 bits, the CY flag isset. No other flags are affected. Eg: DAD H

SUB RM

Subtract register or memory from accumulator

The contents of the operand (register or memory) aresubtracted from the contents of the accumulator, and theresult is stored in the accumulator. If the operand is amemory location, its location is specified by the contents ofthe HL registers. All flags are modified to reflect the resultof the subtraction. Eg: SUB B or SUB M

SBB RM

Subtract source and borrow from accumulator

The contents of the operand (register or memory) and theBorrow flag are subtracted from the contents of theaccumulator and the result is placed in the accumulator. Ifthe operand is a memory location, its location is specifiedby the contents of the HL registers. Flags are modified toreflect the result of the subtraction. Eg: SBB B or SBB M

SUI 8-bit data Subtract immediate from accumulator

The 8-bit data (operand) is subtracted from the contents ofthe accumulator and the result is stored in the accumulator.All flags are modified to reflect the result of the subtraction.

Example: SUI 45H


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SBI 8-bit data Subtract immediate from accumulator with borrow

The 8-bit data (operand) and the borrow flag are subtractedfrom the contents of the accumulator and the result is storedin the accumulator. All flags are modified to reflect theresult of the addition. Eg: SBI 45H

INR RM

Increment register or memory by 1

The contents of the designated register or memory areincremented by 1 and the result is stored in the same place.If the operand is a memory location, its location is specifiedby the contents of the HL registers. Example: INR B or INR M

INX R Increment register pair by 1

The contents of the designated register pair are incrementedby 1 and the result is stored in the same place.

Example: INX H

DCR RM

Decrement register or memory by 1

The contents of the designated register or memory are Mdecremented by 1 and the result is stored in the same place.If the operand is a memory location, its location is specifiedby the contents of the HL registers.

Example: DCR B or DCR M

DCX R Decrement register pair by 1

The contents of the designated register pair are decrementedby 1 and the result is stored in the same place.

Example: DCX H

DAA none Decimal adjust accumulator.Used after an addition operation to convert the result to BCD

If the value of the low-order 4-bits in the accumulator isgreater than 9 or if AC flag is set, the instruction adds 6 tothe low-order four bits.If the value of the high-order 4-bits in the accumulator isgreater than 9 or if the Carry flag is set, the instruction adds6 to the high-order four bits.

Logical instructions

Opcode

Operand Explanation of Instruction

Description

CMP RM

Compare register or memory with accumulator

The contents of the operand (register or memory) are subtracted from the contents of the accumulator. But both contents are preserved. The result of the comparison is shown by setting the flags of the PSW as follows:if (A) < (reg/mem): carry flag is setif (A) = (reg/mem): zero flag is setif (A) > (reg/mem): carry and zero flags are resetExample: CMP B or CMP M


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CPI 8-bit data Compare immediate with accumulator

The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by settingthe flags of the PSW as follows:if (A) < data: carry flag is setif (A) = data: zero flag is setif (A) > data: carry and zero flags are resetExample: CPI 89H

ANA RM

Logical AND register or memory with accumulator

The contents of the accumulator are logically ANDed withM the contents of the operand (register or memory), and theresult is placed in the accumulator. If the operand is amemory location, its address is specified by the contents ofHL registers. S, Z, P are modified to reflect the result of theoperation. CY is reset. AC is set.

Example: ANA B or ANA M

ANI 8-bit data

Logical AND immediate with accumulator

The contents of the accumulator are logically ANDed withthe8-bit data (operand) and the result is placed in theaccumulator. S, Z, P are modified to reflect the result of theoperation. CY is reset. AC is set.

Example: ANI 86H

XRA RM

Exclusive OR register or memory with accumulator

The contents of the accumulator are Exclusive ORed with Mthe contents of the operand (register or memory), and theresult is placed in the accumulator. If the operand is amemory location, its address is specified by the contents ofHL registers. S, Z, P are modified to reflect the result of theoperation. CY and AC are reset.

Example: XRA B or XRA M

XRI 8-bit data

Exclusive OR immediate with accumulator

The contents of the accumulator are Exclusive ORed withthe 8-bit data (operand) and the result is placed in theaccumulator. S, Z, P are modified to reflect the result of theoperation. CY and AC are reset.

Example: XRI 86H

ORA RM

Logical OR register or memory with accumulator

The contents of the accumulator are logically ORed with Mthe contents of the operand (register or memory), and theresult is placed in the accumulator. If the operand is amemory location, its address is specified by the contents ofHL registers. S, Z, P are modified to reflect the result of theoperation. CY and AC are reset.

Example: ORA B or ORA M


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ORI 8-bit data

Logical OR immediate with accumulator

The contents of the accumulator are logically ORed with the8-bit data (operand) and the result is placed in theaccumulator. S, Z, P are modified to reflect the result of theoperation. CY and AC are reset. Example: ORI 86H

RLC -(no operand)

Rotate accumulator left

Each binary bit of the accumulator is rotated left by oneposition. Bit D7 is placed in the position of D0 as well as inthe Carry flag. CY is modified according to bit D7 but CY isnot rotated. S, Z, P, AC are not affected.

RRC -(no operand)

Rotate accumulator right

Each binary bit of the accumulator is rotated right by oneposition. Bit D0 is placed in the position of D7 as well as inthe Carry flag. CY is modified according to bit D0 but CY isnot rotated. S, Z, P, AC are not affected.

RAL -(no operand)

Rotate accumulator left through carry

Each binary bit of the accumulator is rotated left by oneposition through the Carry flag. Bit D7 is placed in theCarry flag, and the Carry flag is placed in the leastsignificant position D0. CY is modified according to bit D7.S, Z, P, AC are not affected.

RAR -(no operand)

Rotate accumulator right through carry

Each binary bit of the accumulator is rotated right by oneposition through the Carry flag. Bit D0 is placed in theCarry flag, and the Carry flag is placed in the mostsignificant position D7. CY is modified according to bit D0.S, Z, P, AC are not affected.

CMA -(no operand)

Complement accumulator

The contents of the accumulator are complemented. Noflags are affected.

CMC -(no operand)

Complement carry The Carry flag is complemented. No other flags are affected.

STC -(no operand)

Set Carry Set Carry

Branching instructions

Opcode Operand Explanation of Instruction

Description

JMP 16-bit address

Jump unconditionally

The program sequence is transferred to the memorylocation specified by the 16-bit address given in theoperand.Example: JMP 2034H


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Conditional jumps

JCJNCJPJMJZ

JNZJPE

JPO

16-bitaddress

Jump on Carry (CF=1)

Jump on no Carry (CF=0)

Jump on positive (SF=0)

Jump on minus (SF=1)Jump on zero (ZF=1)

Jump on no zero (ZF=0)

Jump on parity even (PF=1)

Jump on parity odd (PF=0)

The program sequence is transferred to the memorylocation specified by the 16-bit address given in theoperand based on the specified flag of the PSW asdescribed below.

Example: JZ 2034H

CALL 16-bit address

Unconditional subroutine call

The program sequence is transferred to the memorylocation specified by the 16-bit address given in theoperand. Before the transfer, the address of the nextinstruction after CALL (the contents of the programcounter) is pushed onto the stack. Example: CALL 2034H

RET none Return from subroutine unconditionally

The program sequence is transferred from the subroutine tothe calling program. The two bytes from the top of the stackare copied into the program counter, and program executionbegins at the new address. Example: RET

Conditional subroutine call

CCCNCCPCMCZCNZCPECPO

16-bit address

Call on CarryCall on no CarryCall on positiveCall on minusCall on zeroCall on no zeroCall on parity evenCall on parity odd

The program sequence is transferred to the memorylocation specified by the 16-bit address given in theoperand based on the specified flag of the PSW (flag

register)

Return from subroutine conditionally

RCRNCRPRMRZRNZRPERPO

none

Return on CarryReturn on no CarryReturn on positiveReturn on minusReturn on zeroReturn on no zeroReturn on parityevenReturn on parity odd

The program sequence is transferred from the subroutine tothe calling program based on the specified flag of the PSWas described below. The two bytes from the top of the stackare copied into the program counter, and program executionbegins at the new address.

Example: RZ


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PCHL none Load program counter with HL contents

The contents of registers H and L are copied into theprogram counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte.

Example: PCHL

Restart Instructions (RST0 to RST7) – no operandsThe RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending uponthe number. The instructions are generally used in conjunction with interrupts and inserted using externalhardware. However these can be used as software instructions in a program to transfer program execution toone of the eight locations.

Instructions Restart addressRST 0 0000HRST1 0008HRST 2 0010HRST 3 0018HRST 4 0020HRST 5 0028HRST 6 0030HRST 7 0038H

Machine Control Instructions

Opcode Operand

Explanation ofInstruction

Description

NOP none No operation No operation is performed. The instruction is fetched anddecoded. However no operation is executed. Example: NOP

HLT none Halt and enter waitstate

The CPU finishes executing the current instruction and haltsany further execution. An interrupt or reset is necessary toexit from the halt state. Example: HLT

DI none Disable interrupts The interrupt enable flip-flop is reset and all the interruptsexcept the TRAP are disabled. No flags are affected. Eg: DI

EI none Enable interrupts The interrupt enable flip-flop is set and all interrupts areenabled. No flags are affected. After a system reset or theacknowledgement of an interrupt, the interrupt enable flipflop is reset, thus disabling the interrupts. This instruction isnecessary to re enable the interrupts (exceptTRAP).Example: EI

RIM none Read interrupt mask This is a multipurpose instruction used to read the status ofinterrupts 7.5, 6.5, 5.5 and to input serial data through theSID line. Example: RIM


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SIM none Set interrupt mask This is a multipurpose instruction and used to implement the8085 interrupts 7.5, 6.5, 5.5, and to output data serially fromthe SOD line. Example: SIM


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ee309 microprocessors and embedded systems

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