ee141- spring 2005 digital integrated circuits
TRANSCRIPT
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EE141EE141-- Spring 2005Spring 2005Digital Integrated Digital Integrated CircuitsCircuits
Lecture 20Lecture 20PowerPowerSequential CircuitsSequential Circuits
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Administrative StuffAdministrative Stuff
Hw 7 has been posteddue Fr. 5pm
Midterm 2: April 12th by popular demand!Material:
– Wires– Complex logic– Arithmetic
HW Lab this weekProject 1 has been gradedReview session on Th 6:30-8pm
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Project 1 ResultsProject 1 Results
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Class MaterialClass Material
Last lectureMultipliersShifters
Today’s lecturePowerIntro Sequential Circuits
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PowerPower
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The Power ChallengeThe Power Challenge400 million computers in the world
0.16 PW (PetaWatt = 1015 W) of power dissipationEquivalent to 26 nuclear plants!
Data centers represent the absolute challenge
1 single server rack is between 5 and 20 kW100’s of those racks in a single room!
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PowerPower--andand--Energy ChallengesEnergy ChallengesCourtesy of IBM
Power and energy management and minimizationhave emerged as some of the most dominant roadblocks. The best opportunity lies in a very aggressive scaling and adaptation of supply and threshold values in concert with a careful orchestration of the system activity.
138 W/cm2
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Portability:Portability:Battery storage the limiting factorBattery storage the limiting factor
Little change in basic technologystore energy using a chemical reaction
Battery capacity doubles every 10 yearsEnergy density/size, safe handling are limiting factor
Energy densityof material
KWH/kg
Gasoline 14
Lead-Acid 0.04
Li polymer 0.15
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Battery ProgressBattery Progress
020406080
100120140160
1940 1950 1960 1970 1980 1990 2000 2010
First Commercial Use
Energy Density(Wh/kg) Trend Line
NiCd SLA NiMH Li-Ion ReusableAlkaline
Li-Polymer
Facture 4 over the last 10 years!
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Power Dissipation in CMOSPower Dissipation in CMOSDynamic power
Charging capacitancesDominant today
Leakage powerLeaky transistorsConcern in low-activity, portable devices
Short circuit powerStatic power
E.g. pseudo-NMOS
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Dynamic Power ConsumptionDynamic Power Consumption
( ) ( ) ∫∫ ∫ ====→
DDV
DDLoutLDD
T T
DDDDDD VCdvCVdttiVdttPE0
2
0 010
( ) ( ) ∫∫ ∫ ====DDV
DDLoutoutL
T T
LoutCC VCdvvCdttivdttPE0
2
0 0 21
Vdd
Vout
iL
CL
PMOSNETWORK
NMOS
A1
AN
NETWORK
210 DDLVCE =→
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Dynamic Power ConsumptionDynamic Power Consumption
One half of the power from the supply is consumed in the pull-up network and one half is stored on CLCharge from CL is dumped during the 1→0 transition
Vdd
Vout
iL
CL
PMOSNETWORK
NMOS
A1
AN
NETWORK
210 DDLVCE =→
221
DDLR VCE =
221
DDLC VCE =
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Dynamic Power ConsumptionDynamic Power ConsumptionPower = Energy/transition • Transition rate
= CLVDD2 • f0→1
= CLVDD2 • f • P0→1
= CswitchedVDD2 • f
Power dissipation is data dependent – depends on the switching probabilitySwitched capacitance Cswitched = CL • P0→1
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Transition Activity and PowerTransition Activity and PowerEnergy consumed in N cycles, EN:
EN = CL • VDD2 • n0→1
n0→1 – number of 0→1 transitions in N cycles
fVCN
nfNEP DDLN
NNavg ⋅⋅⋅
=⋅= →
∞→∞→
210limlim
fN
nN
⋅= →
∞→→10
10 limα
fVCP DDLavg ⋅⋅⋅= →2
10α
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“Dynamic” or timing dependent component
Type of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)
Circuit Topology
Type of Logic Style (Static vs. Dynamic)
Signal StatisticsInter-signal Correlations
Signal Statistics and Correlations
Factors Affecting Transition ActivityFactors Affecting Transition Activity
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Type of Logic Function: NOR vs. XORType of Logic Function: NOR vs. XOR
011001010100
OutBA
Example: Static 2-input NOR Gate
Assume signal probabilitiespA=1 = 1/2pB=1 = 1/2
Then transition probabilityp0→1 = pOut=0 x pOut=1
= 3/4 x 1/4 = 3/16
α0→1 = 3/16
If inputs switch every cycle
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Type of Logic Function: NOR vs. XORType of Logic Function: NOR vs. XOR
011101110000
OutBA
Example: Static 2-input XOR Gate
Assume signal probabilitiespA=1 = 1/2pB=1 = 1/2
Then transition probabilityp0→1 = pOut=0 x pOut=1
= 1/2 x 1/2 = 1/4
α0→1 = 1/4
If inputs switch in every cycle
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Power Consumption of Dynamic GatesPower Consumption of Dynamic Gates
In1
In2 PDNIn3
Me
Mp
CLK
CLKOut
CL
Power only dissipated when previous Out = 0
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Dynamic Power Consumption is Dynamic Power Consumption is Data DependentData Dependent
011001010100
OutBA
Dynamic 2-input NOR Gate
Assume signal probabilitiesPA=1 = 1/2PB=1 = 1/2
Then transition probabilityP0→1 = Pout=0 x Pout=1
= 3/4 x 1 = 3/4
Switching activity always higher in dynamic gates!P0→1 = Pout=0
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Vdd
I
I
Vdd
IN
INB
OUTB OUT
Guaranteed transition for every operation!
α0->1 = 1
Dynamic CVSLDynamic CVSL
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Problem: Problem: ReconvergentReconvergent FanoutFanout
A
B
X
Z
Reconvergence
P(Z = 1) = P(B = 1) . P(X = 1 | B=1)
Becomes complex and intractable fast
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InterInter--Signal CorrelationsSignal Correlations
Logic withoutreconvergent fanout
Logic with reconvergent fanout
A
BZ
CA
Z
C
B
p0→1 = (1 – pApB) pApBP(Z = 1) = p(C=1 | B=1) p(B=1)
p0→1 = 0
Need to use conditional probabilities to model inter-signal correlationsCAD tools required for such analysis
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GlitchingGlitching in Static CMOSin Static CMOSA
B
X
CZ
ABC 101 000
X
Z
Gate DelayAlso known as
dynamic hazards
The result is correct,but there is extra power dissipated
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Example: Chain of NOR GatesExample: Chain of NOR Gates1
Out1 Out2 Out3 Out4 Out5
0 200 400 6000.0
1.0
2.0
3.0
Time (ps)
Volta
ge (V
)
Out8Out6
Out2
Out6
Out1
Out3
Out7
Out5
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Principles for Power ReductionPrinciples for Power ReductionPrime choice: Reduce voltage!
Recent years have seen an acceleration in supply voltage reductionDesign at very low voltages still open question (0.6 … 0.9 V by 2010!)Reducing thresholds to improve performance increases leakage
Reduce switching activityReduce physical capacitance
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Sequential Logic
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Sequential LogicSequential Logic
2 storage mechanisms• positive feedback• charge-based
COMBINATIONALLOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
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Latch versus RegisterLatch versus RegisterLatchstores data when clock is low
D
Clk
Q D
Clk
Q
Registerstores data when clock rises
Clk Clk
D D
Q Q
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Naming ConventionNaming Convention
In our book, latch is level sensitive, register is edge-triggeredThere are many different naming conventionsMany books call edge-triggered elements flip-flops
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LatchesLatches
In
clk
In
Out
Positive Latch
CLK
DG
Q
Out
Outstable
Outfollows In
In
clk
In
Out
Negative Latch
CLK
DG
Q
Out
Outstable
Outfollows In
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NLatch Logic
Logic
PLatch
φ
LatchLatch--Based DesignBased Design• N latch is transparentwhen φ = 0
• P latch is transparent when φ = 1
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Timing DefinitionsTiming Definitions
t
CLK
t
D
tc →q
tholdtsu
t
Q DATASTABLE
DATASTABLE
Register
CLK
D Q
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Characterizing TimingCharacterizing Timing
Register Latch
Clk
D Q
tC →Q
Clk
D Q
tC →Q
tD →Q
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Maximum Clock FrequencyMaximum Clock Frequency
FF’s
LOGIC
tp,comb
φ
Also:tcdreg + tcdlogic > thold
tcd: contamination delay = minimum delay
tclk-Q + tp,comb + tsetup = T
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Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1 Vo2
Vo2 = Vi1
Vo1 = Vi2
V
o
1
Vi1
A
C
B
V
i
2
5
V
o
1
Vo2
V
i
2
5
V
o
1
Vi1 = Vo2
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MetaMeta--StabilityStability
Gain should be larger than 1 in the transition region
A
C
d
B
Vi2
5V
o1
Vi1 5 Vo2
A
C
d
B
Vi2
5V
o1
Vi1 5 Vo2
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Writing into a Static LatchWriting into a Static Latch
CLK
CLK
CLK
D
Q D
CLK
CLK
D
Converting into a MUXForcing the state(can implement as NMOS-only)
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
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PseudoPseudo--Static LatchStatic Latch
D
CLK
CLK
D
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MuxMux--Based LatchesBased LatchesNegative latch(transparent when CLK= 0)
Positive latch(transparent when CLK= 1)
CLK
1
0D
Q 0
CLK
1D
Q
InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=
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MuxMux--Based LatchBased Latch
CLK
CLK
CLK
D
Q
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MuxMux--Based LatchBased Latch
CLK
CLK
CLK
CLK
QM
QM
NMOS only Non-overlapping clocks
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Storage MechanismsStorage Mechanisms
D
CLK
CLK
Q
Dynamic
CLK
CLK
CLK
D
Q
Static
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Next LectureNext Lecture
Sequential logic (cntd)