ee101_dgtl_3

8/13/2019 ee101_dgtl_3

1/123

EE101: Digital circuits (Part 3)

M. B. Patil [email protected]

Department of Electrical EngineeringIndian Institute of Technology Bombay

M. B. Patil, IIT Bombay
http://find/http://goback/

8/13/2019 ee101_dgtl_3

2/123

Binary numbers

3 1 7 = 3 102 + 1 101 + 7 100

101102 100

Decimal (base 10) system

8/13/2019 ee101_dgtl_3

3/123

Binary numbers

3 1 7 = 3 102 + 1 101 + 7 100

101102 100


* Digits: 0,1,2,..,9

* example: 4153

most signicantdigit least signicantdigit

8/13/2019 ee101_dgtl_3

4/123

Binary numbers

3 1 7 = 3 102 + 1 101 + 7 100

101102 100


* Digits: 0,1,2,..,9

* example: 4153


Binary (base 2) system

1 0 1 1 1 = 1 24 + 0 23 + 1 22 + 1 21 + 1 20

21 20222

324

= 23 (in decimal)
http://find/

8/13/2019 ee101_dgtl_3

5/123

Binary numbers

3 1 7 = 3 102 + 1 101 + 7 100

101102 100


* Digits: 0,1,2,..,9

* example: 4153



1 0 1 1 1 = 1 24 + 0 23 + 1 22 + 1 21 + 1 20

21 20222

324

= 23 (in decimal)

* Bits: 0,1

* example: 100110

most signicantbit (MSB)

least signicantbit (LSB)

http://find/

8/13/2019 ee101_dgtl_3

6/123

Addition of binary numbers

49111

9

5

7

1

1

1

0

3

8

weight

first number

second number

carry

sum

1

104 103 102 101 100

http://find/

8/13/2019 ee101_dgtl_3

7/123


49111

9

5

7

1

1

1

0

3

8

weight

first number

second number

carry

sum

1

104 103 102 101 100


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1

first number (dec. 11)

sum (dec. 25)

second number (dec. 14)

1

2021222324

http://find/

8/13/2019 ee101_dgtl_3

8/123


49111

9

5

7

1

1

1

0

3

8

weight

first number

second number

carry

sum

1

104 103 102 101 100


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1


sum (dec. 25)


1

2021222324


* 0 + 1 = 1 + 0 = 1 S = 1 , C = 0
http://goforward/http://find/http://goback/

8/13/2019 ee101_dgtl_3

9/123

8/13/2019 ee101_dgtl_3

10/123


49111

9

5

7

1

1

1

0

3

8

weight

first number

second number

carry

sum

1

104 103 102 101 100


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1


sum (dec. 25)


1

2021222324


* 0 + 1 = 1 + 0 = 1 S = 1 , C = 0

* 1 + 1 = 10 (dec . 2) S = 0 , C = 1

* 1 + 1 + 1 = 11 (de c . 3) S = 1 , C = 1

http://find/http://find/

8/13/2019 ee101_dgtl_3

11/123


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1

1

first number

second number

sum

example

2 02 12 22 32 4
http://find/

8/13/2019 ee101_dgtl_3

12/123


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1

1

first number

second number

sum

example

2 02 12 22 32 4 weight

first number

second number

carry

sum

general procedure

C N

2 0

A N

B N

C N 1

2 12 2

A 2

B 2

C 1

S 2 S1

C 0

B 1

A 1

2 N

A 0

B 0

S 0S N
http://find/

8/13/2019 ee101_dgtl_3

13/123


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1

1

first number

second number

sum

example

2 02 12 22 32 4 weight

first number

second number

carry

sum

general procedure

C N

2 0

A N

B N

C N 1

2 12 2

A 2

B 2

C 1

S 2 S1

C 0

B 1

A 1

2 N

A 0

B 0

S 0S N

A

B

S

FA

A

B

S

FA

A

B

S

HA

A

B

S

FA

C o CiC o Ci CoC o CiC N

B NA N

C N 1

B 2A 2

S 2

C 1

A 1 B 1

S 1

C 0

B 0A 0

S 0S N
http://find/

8/13/2019 ee101_dgtl_3

14/123


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1

1

first number

second number

sum

example

2 02 12 22 32 4 weight

first number

second number

carry

sum

general procedure

C N

2 0

A N

B N

C N 1

2 12 2

A 2

B 2

C 1

S 2 S1

C 0

B 1

A 1

2 N

A 0

B 0

S 0S N

A

B

S

FA

A

B

S

FA

A

B

S

HA

A

B

S

FA


B NA N

C N 1

B 2A 2

S 2

C 1

A 1 B 1

S 1

C 0

B 0A 0

S 0S N

* The rightmost block (corresponding to the LSB) adds two bits A0 and B 0 ; there is no inputcarry. This block is called a half adder.
http://goback/http://find/http://goback/

8/13/2019 ee101_dgtl_3

15/123


1

1

weight

carry

1 0 1 1

1 1 0

1

11 0 0 1

1

first number

second number

sum

example

2 02 12 22 32 4 weight

first number

second number

carry

sum

general procedure

C N

2 0

A N

B N

C N 1

2 12 2

A 2

B 2

C 1

S 2 S1

C 0

B 1

A 1

2 N

A 0

B 0

S 0S N

A

B

S

FA

A

B

S

FA

A

B

S

HA

A

B

S

FA


B NA N

C N 1

B 2A 2

S 2

C 1

A 1 B 1

S 1

C 0

B 0A 0

S 0S N

* The rightmost block (corresponding to the LSB) adds two bits A0 and B 0 ; there is no inputcarry. This block is called a half adder.

* Each of the subsequent blocks adds three bits ( Ai , B i , C i 1) and is called a full adder.


lf dd i l i
http://find/

8/13/2019 ee101_dgtl_3

16/123

Half adder implementation

A

B

S

HA

C o

BA S C o

C 0

S 0

B 0

A 0

1

0

1 0

1

0 0

1

0

0

0

1

1

1

0

0

H lf dd i l i
http://find/

8/13/2019 ee101_dgtl_3

17/123


A

B

S

HA

C o

BA S C o

C 0

S 0

B 0

A 0

1

0

1 0

1

0 0

1

0

0

0

1

1

1

0

0

S = A B + A B = A B

C o = A B

H lf dd i l t ti
http://find/

8/13/2019 ee101_dgtl_3

18/123


A

B

S

HA

C o

BA S C o

C 0

S 0

B 0

A 0

1

0

1 0

1

0 0

1

0

0

0

1

1

1

0

0

S = A B + A B = A B

C o = A B

Implementation 1

C o

A B

A B

A

B

A

B

S

http://find/

8/13/2019 ee101_dgtl_3

19/123


A

B

S

HA

C o

BA S C o

C 0

S 0

B 0

A 0

1

0

1 0

1

0 0

1

0

0

0

1

1

1

0

0

S = A B + A B = A B

C o = A B

Implementation 1

C o

A B

A B

A

B

A

B

S

Implementation 2

C o

A + B

A B

S

A

B


Full adder implementation
http://find/

8/13/2019 ee101_dgtl_3

20/123


A

B

S

FA

C i C oB

C o Ci

A S

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

http://find/

8/13/2019 ee101_dgtl_3

21/123


A

B

S

FA

C i C oB

C o Ci

A S

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

AB00 01 11 10C i

S:

1

1

1

1

1

S = A B C i + A B C i + A B C i + A B C i

0

0

0

0

0

http://find/

8/13/2019 ee101_dgtl_3

22/123


A

B

S

FA

C i C oB

C o Ci

A S

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

AB00 01 11 10C i

S:

1

1

1

1

1

S = A B C i + A B C i + A B C i + A B C i

0

0

0

0

0

C :o

AB00 01 11 10C i

1 1

1

1 1

C o = A B + B C i + A C i

00 0 0

0


Implementation of functions with only NAND gates
http://find/

8/13/2019 ee101_dgtl_3

23/123


The NOT, AND, OR operations can be realised by using only NAND gates:

http://find/

8/13/2019 ee101_dgtl_3

24/123



NOT

A

A = A A

A

http://find/

8/13/2019 ee101_dgtl_3

25/123

p y g


NOT

A

A = A A

A

AND

A B

A B = A B

A

B

http://find/

8/13/2019 ee101_dgtl_3

26/123

p y g


NOT

A

A = A A

A

AND

A B

A B = A B

A

B

OR

A + B

A

B

A + B = A B


http://find/

8/13/2019 ee101_dgtl_3

27/123

p y g

Implement Y=

A B+

B C D+

A D using only NAND gates.

http://find/

8/13/2019 ee101_dgtl_3

28/123

Implement Y=

A B+

B C D+


A B = A B

A = A A

A + B = A B

http://find/

8/13/2019 ee101_dgtl_3

29/123

Implement Y=

A B+

B C D+


A B = A B

A = A A

A + B = A B

Y = A B B C D A D

http://find/

8/13/2019 ee101_dgtl_3

30/123

Implement Y=

A B+

B C D+


A B = A B

A = A A

A + B = A B

Y = A B B C D A D

B C D

A B

Y

A D


8/13/2019 ee101_dgtl_3

31/123

Implement Y=

A B+

B C D+


A B = A B

A = A A

A + B = A B

Y = A B B C D A D

B C D

A B

Y

A D

A

B

http://find/

8/13/2019 ee101_dgtl_3

32/123

Implement Y=

A B+

B C D+


A B = A B

A = A A

A + B = A B

Y = A B B C D A D

B C D

A B

Y

A D

A

B

BC

D

http://find/

8/13/2019 ee101_dgtl_3

33/123

Implement Y = A B + B C D + A D using only NAND gates.

A B = A B

A = A A

A + B = A B

Y = A B B C D A D

B C D

A B

Y

A D

A

B

BC

D

A

D


http://find/

8/13/2019 ee101_dgtl_3

34/123

Implement Y = A + B + C using only 2-input NAND gates.

http://find/

8/13/2019 ee101_dgtl_3

35/123


A B = A B

A = A A

A + B = A B

http://find/

8/13/2019 ee101_dgtl_3

36/123


A B = A B

A = A A

A + B = A B

Y = ( A + B ) + C

= ( A + B ) C

http://find/

8/13/2019 ee101_dgtl_3

37/123


A B = A B

A = A A

A + B = A B

Y = ( A + B ) + C

= ( A + B ) C

Y

A + B

C

http://find/

8/13/2019 ee101_dgtl_3

38/123


A B = A B

A = A A

A + B = A B

Y = ( A + B ) + C

= ( A + B ) C

Y

A + B

CC

http://find/

8/13/2019 ee101_dgtl_3

39/123


A B = A B

A = A A

A + B = A B

Y = ( A + B ) + C

= ( A + B ) C

Y

A + B

CC

= A B C

http://find/

8/13/2019 ee101_dgtl_3

40/123


A B = A B

A = A A

A + B = A B

Y = ( A + B ) + C

= ( A + B ) C

Y

A + B

CC

= A B C

A + B

http://find/

8/13/2019 ee101_dgtl_3

41/123


A B = A B

A = A A

A + B = A B

Y = ( A + B ) + C

= ( A + B ) C

Y

A + B

CC

= A B C

A + B

A A

BB


Implementation of functions with only NOR gates
http://find/

8/13/2019 ee101_dgtl_3

42/123

The NOT, AND, OR operations can be realised by using only NOR gates:


8/13/2019 ee101_dgtl_3

43/123


NOT

A = A + A

AA

http://find/

8/13/2019 ee101_dgtl_3

44/123


NOT

A = A + A

AA

AND

A B

A

B

A B = A + B


8/13/2019 ee101_dgtl_3

45/123


NOT

A = A + A

AA

AND

A B

A

B

A B = A + B

OR

A + B

A + B = A + B

A

B

http://find/

8/13/2019 ee101_dgtl_3

46/123


NOT

A = A + A

AA

AND

A B

A

B

A B = A + B

OR

A + B

A + B = A + B

A

B

Implementation of functions with only NOR (or only NAND) gates is more than a theoreticalcuriosity. There are chips which provide a sea of gates (say, NOR gates) which can be

congured by the user (through programming) to implement functions.



8/13/2019 ee101_dgtl_3

47/123

Implement Y = A B + B C D + A D using only NOR gates.


8/13/2019 ee101_dgtl_3

48/123


A + B = A + B

A = A + A

A B = A + B


8/13/2019 ee101_dgtl_3

49/123


A + B = A + B

A = A + A

A B = A + B

Y = A B + B C D + A D


8/13/2019 ee101_dgtl_3

50/123


A + B = A + B

A = A + A

A B = A + B

Y = A B + B C D + A D

Y

A B

B C D

A D

http://find/

8/13/2019 ee101_dgtl_3

51/123


A + B = A + B

A = A + A

A B = A + B

Y = A B + B C D + A D

Y

A B

B C D

A D

= ( A + B ) + ( B + C + D ) + ( A + D )

http://find/

8/13/2019 ee101_dgtl_3

52/123


A + B = A + B

A = A + A

A B = A + B

Y = A B + B C D + A D

Y

A B

B C D

A D

= ( A + B ) + ( B + C + D ) + ( A + D )

A

B

A

B

http://find/

8/13/2019 ee101_dgtl_3

53/123


A + B = A + B

A = A + A

A B = A + B

Y = A B + B C D + A D

Y

A B

B C D

A D

= ( A + B ) + ( B + C + D ) + ( A + D )

A

B

A

B

C

D

C
http://find/

8/13/2019 ee101_dgtl_3

54/123

Multiplexers

8/13/2019 ee101_dgtl_3

55/123

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

Multiplexers
http://find/

8/13/2019 ee101_dgtl_3

56/123

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

* A multiplexer or data selector (MUX in short) selects one of the 2 N input lines, i.e., it makesthe ouput Z equal to one of the input lines. In other words, a MUX routes one of the inputlines to the output.

Multiplexers

8/13/2019 ee101_dgtl_3

57/123

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

I0

I1

I2

I3

S1 S0

Z

SW0

SW1

SW2

SW3


Multiplexers
http://find/

8/13/2019 ee101_dgtl_3

58/123

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

I0

I1

I2

I3

S1 S0

Z

SW0

SW1

SW2

SW3


* Conceptually, a MUX may be thought of as 2 N switches. For a given combination of theselect inputs, only one of the switches closes (makes contact), and the others are open.


Multiplexers
http://find/

8/13/2019 ee101_dgtl_3

59/123

I0

I1

I2

I3

Z

S1 S0

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3


Multiplexers
http://find/

8/13/2019 ee101_dgtl_3

60/123

I0

I1

I2

I3

Z

S1 S0

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

* A 4-to-1 MUX can be implemented as,Z = I 0 S 1 S 0 + I 1 S 1 S 0 + I 2 S 1 S 0 + I 3 S 1 S 0 .For a given combination of S 1 and S 0 , only one of the terms survives (the others being 0).

For example, with S

1 = 0, S

0 = 1, we have Z

=I 1 .


Multiplexers

8/13/2019 ee101_dgtl_3

61/123

I0

I1

I2

I3

Z

S1 S0

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

* A 4-to-1 MUX can be implemented as,Z = I 0 S 1 S 0 + I 1 S 1 S 0 + I 2 S 1 S 0 + I 3 S 1 S 0 .For a given combination of S 1 and S 0 , only one of the terms survives (the others being 0).For example, with S

1 = 0, S

0 = 1, we have Z = I

1.

* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.


Multiplexers

8/13/2019 ee101_dgtl_3

62/123

I0

I1

I2

I3

Z

S1 S0

I0

I1

I2

I3

Z

S1 S0

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

* A 4-to-1 MUX can be implemented as,Z = I 0 S 1 S 0 + I 1 S 1 S 0 + I 2 S 1 S 0 + I 3 S 1 S 0 .For a given combination of S 1 and S 0 , only one of the terms survives (the others being 0).For example, with S

1 = 0, S

0 = 1, we have Z = I

1.

* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.* ICs with arrays of multiplexers (and other digital blocks) are also available. These blocks

can be congured (wired) by the user in a programmable manner to realise thefunctionality of interest.


Active high and active low inputs/outputs
http://find/

8/13/2019 ee101_dgtl_3

63/123

I0

I1I2

I3

Z

S1 S0Select inputs are active high.

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

Active high and active low inputs/outputs

8/13/2019 ee101_dgtl_3

64/123

I0

I1I2

I3

Z

S1 S0Select inputs are active high.

S0S1 Z

1

0

1 0

1

0 0

1

I0

I1

I2

I3

I0

I1

I2

I3

Z

S1 S0Select inputs are active low.

S0 ZS1

11

1

0

0

1

00

I0

I1

I2

I3


Enable (E) pin
http://find/

8/13/2019 ee101_dgtl_3

65/123

inputs outputs

E

inputs outputs

EActive low enable pin.Active high enable pin.


Enable (E) pin
http://find/

8/13/2019 ee101_dgtl_3

66/123

inputs outputs

E

inputs outputs


* Many digital ICs have an Enable (E) pin. If the Enable pin is active, the ICfunctions as desired; else, it is disabled, i.e., the outputs are set to somedefault values.


Enable (E) pin
http://find/

8/13/2019 ee101_dgtl_3

67/123

inputs outputs

E

inputs outputs



* The Enable pin can be active high or active low.


Enable (E) pin
http://find/

8/13/2019 ee101_dgtl_3

68/123

inputs outputs

E

inputs outputs



* The Enable pin can be active high or active low.

* If the Enable pin is active low, it is denoted by Enable or E. When E = 0, the ICfunctions normally; else, it is disabled.


Using two 8-to-1 MUXs to make a 16-to-1 MUX
http://find/

8/13/2019 ee101_dgtl_3

69/123

S2 S1 S0

I0I1I2I3I4I5I6I7

E

Z74151

S2 S1 S0

I0

I1I2I3

I4I5I6I7

E

Z74151

S2 S1S3 S0

D15D14D13

D12D11D10D9D8D7D6D5D4

D3D2D1D0

X1

X2

X

S0 XS1S2S3

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

D1

D2

D3

D5

D9

D11

D15

0

0

1

1

1

1

0

0

0

0

1

1

1

D0

D4

D6

D7

D8

D10

D12

D13

D14


http://find/

8/13/2019 ee101_dgtl_3

70/123

S2 S1 S0

I0I1I2I3I4I5I6I7

E

Z74151

S2 S1 S0

I0

I1I2I3

I4I5I6I7

E

Z74151

S2 S1S3 S0

D15D14D13


D3D2D1D0

X1

X2

X

S0 XS1S2S3

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

D1

D2

D3

D5

D9

D11

D15

0

0

1

1

1

1

0

0

0

0

1

1

1

D0

D4

D6

D7

D8

D10

D12

D13

D14

* When S 3 is 0, the upper MUX is enabled, and the lower MUX is disabled (i.e., X 2=0).


http://find/

8/13/2019 ee101_dgtl_3

71/123

S2 S1 S0

I0I1I2I3I4I5I6I7

E

Z74151

S2 S1 S0

I0

I1I2I3

I4I5I6I7

E

Z74151

S2 S1S3 S0

D15D14D13


D3D2D1D0

X1

X2

X

S0 XS1S2S3

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

D1

D2

D3

D5

D9

D11

D15

0

0

1

1

1

1

0

0

0

0

1

1

1

D0

D4

D6

D7

D8

D10

D12

D13

D14

* When S 3 is 0, the upper MUX is enabled, and the lower MUX is disabled (i.e., X 2=0).* When S 3 is 1, the lower MUX is enabled, and the upper MUX is disabled (i.e., X 1=0).


Using MUXs to implement logical functions

Implement X = A B C D + A B C D using a 16-to-1 MUX
http://find/

8/13/2019 ee101_dgtl_3

72/123

Implement X = A B C D + A B C D using a 16-to-1 MUX.


Implement X = A B C D + A B C D using a 16-to-1 MUX
http://find/

8/13/2019 ee101_dgtl_3

73/123

Implement X A B C D + A B C D using a 16 to 1 MUX.

S2S3 S1 S0

I0I1I2I3I4

I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1


http://find/

8/13/2019 ee101_dgtl_3

74/123

Implement X A B C D A B C D using a 16 to 1 MUX.

S2S3 S1 S0

I0I1I2I3I4

I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

* When A B C D = 1, we want X = 1.A B C D = 1 A = 1, B = 0, C = 0, D = 1,i.e., the input line corresponding to 1001 (I9)gets selected. Make I9 = 1.


http://find/

8/13/2019 ee101_dgtl_3

75/123

p g

S2S3 S1 S0

I0I1I2I3I4I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1



http://find/

8/13/2019 ee101_dgtl_3

76/123

p g

S2S3 S1 S0

I0I1I2I3I4I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1


* Similarly, when A B C D = 1, we want X = 1. Make I4 = 1.


http://find/

8/13/2019 ee101_dgtl_3

77/123

S2S3 S1 S0

I0I1I2I3I4I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1




http://find/

8/13/2019 ee101_dgtl_3

78/123

S2S3 S1 S0

I0I1I2I3I4I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1



* In all other cases, X should be 0. connect all other pins to 0.


http://find/

8/13/2019 ee101_dgtl_3

79/123

S2S3 S1 S0

I0I1I2I3I4I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0





http://find/

8/13/2019 ee101_dgtl_3

80/123

S2S3 S1 S0

I0I1I2I3I4I5I6

I7I8I9I10I11I12I13I14

I15

MUX

B C DA

Z X

D XCBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0




* In this example, since the truth table isorganized in terms of ABCD , with A as theMSB and D as the LSB (the same order inwhich A, B , C , D are connected to the selectpins), the design is simple: The expected outputfor 0000, 0001, 0010, etc. is applied to pins I0,I1, I2, etc., respectively.



Implement X = A B C D + A B C D using an 8-to-1 MUX.
http://find/

8/13/2019 ee101_dgtl_3

81/123
http://find/

8/13/2019 ee101_dgtl_3

82/123



8/13/2019 ee101_dgtl_3

83/123

D

D

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

C XBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D . connect the input line corresponding to 100 (I4) to D .



8/13/2019 ee101_dgtl_3

84/123

D

D

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

C XBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

D



http://find/

8/13/2019 ee101_dgtl_3

85/123

D

D

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

C XBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

D


http://find/

8/13/2019 ee101_dgtl_3

86/123



8/13/2019 ee101_dgtl_3

87/123

D

D

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

C XBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

D

D






C XBA

8/13/2019 ee101_dgtl_3

88/123

D

D

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

C XBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

D

D

0

0

0

0

0

0






C XBA

8/13/2019 ee101_dgtl_3

89/123

D

D

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

C XBA

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

D

D

0

0

0

0

0

0




* Home work: Implement the same function ( X ) with S 2 = B , S 1 = C , S 0 = D .

M B Patil IIT Bombay


Implement the function X with the following truth table using an 8-to-1 MUX.

D XCBA

8/13/2019 ee101_dgtl_3

90/123

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

00

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1



D XCBA

0 000 1

8/13/2019 ee101_dgtl_3

91/123

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

11

0

0

1

1

0

0

1

1

00

0

0

0

0

0

0

0

1

1

1

1

1

1

1

11

0

0

0

1

1

1

0

1

1

1

1

0

0

0

00

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C



D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

92/123

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

11

0

0

1

1

0

0

1

1

00

0

0

0

0

0

0

0

1

1

1

1

1

1

1

11

0

0

0

1

1

1

0

1

1

1

1

0

0

0

00

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

1

0



D XCBA

0 000 1

1

8/13/2019 ee101_dgtl_3

93/123

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

00

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

1

0

* When ABC = 000, X = D I0 = D .



D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

94/123

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

00

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

0

D

* When ABC = 000, X = D I0 = D .



D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

95/123

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

0

D

1

1

* When ABC = 000, X = D I0 = D .



D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

96/123

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

0

D

1

1

* When ABC = 000, X = D I0 = D .* When ABC = 001, X = 1 I1 = 1, and so on.



D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

97/123

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

0

D

1

1

1




D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

98/123

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

0

D

1

1

1

0

D

D

1

0

0

0

0

0

1

1

0

1

1

0

0

0

0




D XCBA

0 000 1

1
http://find/

8/13/2019 ee101_dgtl_3

99/123

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

Z X

I7

I6

I5

I4

I3

I2

I1

I0

S2

MUX

S1 S0

A B C

0

D

1

1

1

0

D

D

1

0

0

0

0

0

1

1

0

1

1

0

0

0

0

* When ABC = 000, X = D I0 = D .* When ABC = 001, X = 1 I1 = 1, and so on.* Home work: repeat with S2 = B , S1 = C , S0 = D .


Demultiplexers
http://find/

8/13/2019 ee101_dgtl_3

100/123

O0

O1

O2

O3

O4

O5

O6

O7

S2 S1 S0

I

S2

O0

O1

O2

O3

O4

O5

O6

O7S1 S0

DEMUXI

S0 O0 O1 O2 O3 O4 O5 O6 O7S1S2

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0 0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

1

1

1

1


Demultiplexers
http://find/

8/13/2019 ee101_dgtl_3

101/123

O0

O1

O2

O3

O4

O5

O6

O7

S2 S1 S0

I

S2

O0

O1

O2

O3

O4

O5

O6

O7S1 S0

DEMUXI

S0 O0 O1 O2 O3 O4 O5 O6 O7S1S2

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0 0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

1

1

1

1

* A demultiplexer takes a single input (I) and routes it to one of the output lines(O0, O1, ).


Demultiplexers
http://find/

8/13/2019 ee101_dgtl_3

102/123

O0

O1

O2

O3

O4

O5

O6

O7

S2 S1 S0

I

S2

O0

O1

O2

O3

O4

O5

O6

O7S1 S0

DEMUXI

S0 O0 O1 O2 O3 O4 O5 O6 O7S1S2

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0 0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

1

1

1

1


* For N Select inputs (S0, S1, ), the number of output lines is 2 N .


Demultiplexers
http://find/

8/13/2019 ee101_dgtl_3

103/123

O0

O1

O2

O3

O4

O5

O6

O7

S2 S1 S0

I

S2

O0

O1

O2

O3

O4

O5

O6

O7S1 S0

DEMUXI

S0 O0 O1 O2 O3 O4 O5 O6 O7S1S2

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0 0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

0

I

0

0

0

0

0

0

I

0

0

0

1

1

1

1


* For N Select inputs (S0, S1, ), the number of output lines is 2 N .

* Conceptually, a DEMUX can be thought of as 2 N switches. For a given combination of theSelect inputs, only one of the switches is closed, all others being open.


Demultiplexer: gate-level diagram

O0I
http://find/

8/13/2019 ee101_dgtl_3

104/123

S2 S1 S0

O1

O2

O3

O4

O5

O6

O7

S2

O0

O1

O2

O3

O4

O5

O6

O7S1 S0

DEMUXI


Decoders
http://find/

8/13/2019 ee101_dgtl_3

105/123

M outputsN inputs Decoder

A 0A 1

O 0O 1

O M-1A N-1


Decoders
http://find/

8/13/2019 ee101_dgtl_3

106/123


A 0A 1

O 0O 1

O M-1A N-1

* For each input combination, only one output line is active (which means 0 or 1,depending on whether the outputs are active low or active high).


Decoders
http://find/

8/13/2019 ee101_dgtl_3

107/123


A 0A 1

O 0O 1

O M-1A N-1

* For each input combination, only one output line is active (which means 0 or 1,depending on whether the outputs are active low or active high).

* Since there are 2 N input combinations, there could be 2 N output lines, i.e.,M = 2 N . However, there are decoders with M < 2N as well.


3-to-8 decoder (1-of-8 decoder)
http://find/

8/13/2019 ee101_dgtl_3

108/123

O0

O1

O2

O3

O4

O5

O6

O7

A1

A0

A2

Decoder

A0 O7O6O5O4O3O2O1O0A1A2

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0 0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

1

1

1

1


BCD-to-decimal decoder

Active output

0

0

0

1

0

0

0

0

O 0

O 1

A 0A 1A 2A 3
http://find/

8/13/2019 ee101_dgtl_3

109/123

7442

none

none

none

none

none

no ne

0

0

1

1

1

1

0

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

1

1

1

O 0O 1O 2O 3O 4O 5O 6O 7O 8O 9

O2

O 3

O 4

O 5

O 6

O 7

O 8

O 9

A 0A 1A 2A 3


BCD-to-decimal decoder

Active output

0

0

0

1

0

0

0

0

O 0

O 1

A 0A 1A 2A 3

8/13/2019 ee101_dgtl_3

110/123

7442

none

none

none

none

none

no ne

0

0

1

1

1

1

0

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

1

1

1

O 0O 1O 2O 3O 4O 5O 6O 7O 8O 9

O2

O 3

O 4

O 5

O 6

O 7

O 8

O 9

A 0A 1A 2A 3

* Note that the combinations A3A2A1A0 = 1010 onwards are dont care conditions since aBCD (binary coded decimal) number is expected to be less than 1010 (i.e., decimal 10).


BCD-to-7 segment decoder

acommonanode

a

b

VCC
http://find/

8/13/2019 ee101_dgtl_3

111/123

D

C

B

A

b

ce

d

f

g

7446

MSB

LSB

b

c

d

e

f

g

0001 0010 0011 0100 0101 0110 0111 10000000 1001 1010 1011 1100 1101 1110 1111



acommonanode

a

b

VCC
http://find/

8/13/2019 ee101_dgtl_3

112/123

D

C

B

A

b

ce

d

f

g

7446

MSB

LSB

b

c

d

e

f

g

0001 0010 0011 0100 0101 0110 0111 10000000 1001 1010 1011 1100 1101 1110 1111

* The resistors serve to limit the diode current. For V CC = 5 V , V D = 2 V , andI D =10 m A, R = 300 .



acommonanode

a

b

VCC
http://find/

8/13/2019 ee101_dgtl_3

113/123

D

C

B

A

b

ce

d

f

g

7446

MSB

LSB

b

c

d

e

f

g

0001 0010 0011 0100 0101 0110 0111 10000000 1001 1010 1011 1100 1101 1110 1111

* The resistors serve to limit the diode current. For V CC = 5 V , V D = 2 V , andI D =10 m A, R = 300 .

* Home work: Write the truth table for c (in terms of D , C , B , A). Obtain aminimized expression for c using a K map.

http://find/

8/13/2019 ee101_dgtl_3

114/123

Encoders

A 0 O 0

8/13/2019 ee101_dgtl_3

115/123

M inputs N outputsEncoder

0A 1

0O 1

A M-1 O N-1

* Only one input line is assumed to be active. The (unique) binary numbercorresponding to the active input line appears at the output pins.


Encoders

A 0 O 0
http://find/

8/13/2019 ee101_dgtl_3

116/123


0

A 1

0

O 1

A M-1 O N-1


* The N output lines can represent 2 N binary numbers, each corresponding to oneof the M input lines, i.e., we can have M = 2 N . Some encoders have M < 2N .


Encoders

A 0 O 0
http://find/

8/13/2019 ee101_dgtl_3

117/123


A 1 O 1

A M-1 O N-1


* The N output lines can represent 2 N binary numbers, each corresponding to oneof the M input lines, i.e., we can have M = 2 N . Some encoders have M < 2N .

* As an example, for N = 3, we can have a maximum of 2 3 = 8 input lines.


Encoders

8to3 encoder example A0 A1 A2 A3 A4 A5 A6 A7 O0O1O2

1 0 0 0 0 0 0 0 000
http://find/

8/13/2019 ee101_dgtl_3

118/123

O0

O1

O2

A0A1

A2

A3

A4

A5

A6

A7

Encoder

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0 0 0 0 0

00000

0

0

0

0

0

0

0

0

0 0 0 0

00

0

0 0 0 0

0

0

0

0

00

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0


Encoders


1 0 0 0 0 0 0 0 000

8/13/2019 ee101_dgtl_3

119/123

O0

O1

O2

A0A1

A2

A3

A4

A5

A6

A7

Encoder

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0 0 0 0 0

00000

0

0

0

0

0

0

0

0

0 0 0 0

00

0

0 0 0 0

0

0

0

0

00

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

* Note that only one of the input lines is assumed to be active.


Encoders


1 0 0 0 0 0 0 0 000

8/13/2019 ee101_dgtl_3

120/123

O0

O1

O2

A0A1

A2

A3

A4

A5

A6

A7

Encoder

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0 0 0 0 0 0

00000

0

0

0

0

0

0

0

0

0 0 0 0

00

0

0 0 0 0

0

0

0

0

00

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

* Note that only one of the input lines is assumed to be active.

* What if two input lines become simultaneously active?

There are priority encoders which assign a priority to each of the input lines.


74147 decimal-to-BCD priority encoder

A 9A 8A 7A 6A 5A 4A 3A 2A 1 O 3 O 2 O 1 O 0

1 1 1 1 1 1 1 1 1

X X 0X X X X X X

1 1 1 1

0 01 1A 1

8/13/2019 ee101_dgtl_3

121/123

74147

0

0

0

0

0

0

0

0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

11

0 111

01 00

1 0 0 1

1 0 01

1 0 1 1

1

1

1

1

1

1 1 0

0 1

0 0

O 0O 1O 2O 3

A 2A 3A 4A 5A 6A 7A 8A 9



A 9A 8A 7A 6A 5A 4A 3A 2A 1 O 3 O 2 O 1 O 0

1 1 1 1 1 1 1 1 1

X X 0X X X X X X

1 1 1 1

0 01 1A 1
http://find/

8/13/2019 ee101_dgtl_3

122/123

74147

0

0

0

0

0

0

0

0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

11

0 111

01 00

1 0 0 1

1 0 01

1 0 1 1

1

1

1

1

1

1 1 0

0 1

0 0

O 0O 1O 2O 3

A 2A 3A 4A 5A 6A 7A 8A 9

* Note that the higher input lines get priority over the lower ones.For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low), the binaryoutput is 1000 (i.e., 0111 inverted bit-by-bit) which corresponds to decimal 7, irrespective of A1 , A2 , A3 , A4 , A5 , A6 .



A 9A 8A 7A 6A 5A 4A 3A 2A 1 O 3 O 2 O 1 O 0

1 1 1 1 1 1 1 1 1

X X 0X X X X X X

1 1 1 1

0 01 1A 1
http://find/

8/13/2019 ee101_dgtl_3

123/123

74147

0

0

0

0

0

0

0

0

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

11

0 111

01 00

1 0 0 1

1 0 01

1 0 1 1

1

1

1

1

1

1 1 0

0 1

0 0

O 0O 1O 2O 3

A 2A 3A 4A 5A 6A 7A 8A 9

* Note that the higher input lines get priority over the lower ones.For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low), the binaryoutput is 1000 (i.e., 0111 inverted bit-by-bit) which corresponds to decimal 7, irrespective of A1 , A2 , A3 , A4 , A5 , A6 .

* The lower input lines are therefore shown as dont care (X) conditions.

http://find/

ee101_dgtl_3

Documents