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  • EE 434 ASIC and Digital SystemsPhysical Design Automation of VLSI Circuits and Systems 2 VLSI Design System Specification Functional Design RTL Code (HDL) Synthesis Physical Design
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EE 434 ASIC and Digital Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Preliminaries

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  • EE 434 ASIC and Digital Systems

    Prof. Dae Hyun Kim

    School of Electrical Engineering and Computer Science Washington State University

    Preliminaries

  • 2 Physical Design Automation of VLSI Circuits and Systems

    VLSI Design

    System Specification

    Functional Design

    RTL Code (HDL)

    Synthesis

    Physical Design

    Fabrication

    64-bit integer multiplier / 1GHz / 0.1mm2 / 0.1mW Freq Area Power

    C/C++, Verilog, VHDL, …

    module imul_64 (a, b, clk, out64); input a, b, clk; output out64; … endmodule

    Netlist

    Layout

    Bare die

    Packaging Chip

  • 3 Physical Design Automation of VLSI Circuits and Systems

    From RTL Code to a Chip

    RTL Code (HDL)

  • 4 Physical Design Automation of VLSI Circuits and Systems

    From RTL Code to a Chip

    RTL Code (HDL)

    Synthesis

    Tech-specific logic gates

    Tech library (e.g., 45nm)

  • 5 Physical Design Automation of VLSI Circuits and Systems

    From RTL Code to a Chip

    RTL Code (HDL)

    Synthesis

    Physical Design

  • 6 Physical Design Automation of VLSI Circuits and Systems

    From RTL Code to a Chip

    RTL Code (HDL)

    Synthesis

    Physical Design

    Fabrication

  • 7 Physical Design Automation of VLSI Circuits and Systems

    From RTL Code to a Chip

    RTL Code (HDL)

    Synthesis

    Physical Design

    Fabrication

    Packaging

  • 8 Physical Design Automation of VLSI Circuits and Systems

    VLSI Design

    Full custom ASIC Design Manual Automatic

    TRs Manually drawn Standard-cell based Placement & Routing Custom Automatic

    Development time Several months A few days ~ weeks

  • 9 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    • Provides – good performance – low power – small area – …

    • Other design styles

    – FPGA – PLA – …

  • 10 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    • Standard cells – A set of logic gates – Have the same height. – Width varies. – Pre-characterized for timing and power analysis.

    INV NAND2

  • 11 Physical Design Automation of VLSI Circuits and Systems

    Standard Cells (Layout)

    in out

    p-welln-well

    n-wellp-well

    VDD

    GND

    poly (gate)

    metal 1

    contact

    n+ (n-implant)

    p+ (p-implant)

    cell bounrary

    in1

    p-welln-well

    n-wellp-well

    VDD

    GND

    in2

    out

    INV NAND2

    in outin1 outin2

  • 12 Physical Design Automation of VLSI Circuits and Systems

    Standard Cells (Layout)

    in out

    p-welln-well

    n-wellp-well

    VDD

    GND

    M3

    M2

    M1

    substrate

    p-epi

    n+ n+ p+ p+n-well

    p+ n+

    Top-down view Side view

  • 13 Physical Design Automation of VLSI Circuits and Systems

    Design Rules

    in out

    p-welln-well

    n-wellp-well

    VDD

    GND

    ①

    ①: Min. distance (poly, contact) ②: Min. distance (metal 1) ③: Min. distance (p-active, n-well boundary) ④: Min. width (poly) ⑤: Min. width (metal 1) ⑥: Min. distance (contact) ⑦: Min. distance (contact, n-well bounrary)

    ②

    ③

    ④ ⑤

    ⑥

    ⑦

  • 14 Physical Design Automation of VLSI Circuits and Systems

    Standard Cells (Layout)

    in out

    p-welln-well

    n-wellp-well

    VDD

    GND

    poly (gate)

    metal 1

    contact

    n+ (n-implant)

    p+ (p-implant)

    cell bounrary

    in1

    p-welln-well

    n-wellp-well

    VDD

    GND

    in2

    out

    INV NAND2

    in outin1 outin2

  • 15 Physical Design Automation of VLSI Circuits and Systems

    Standard Cells (Abstract)

    INV NAND2

    in outin1 outin2

    in out

    VDD

    GND

    in1

    VDD

    GND

    in2

    out

    metal 1

    cell bounrary

  • 16 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design in out

    in1outin2

    metal 1

    cell bounrary

    via12

    metal 2

    in1

    VDD

    GND

    in2

    out

    in out

    VDD

    GND

    in1 in2out

    VDD

    in out

  • 17 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    • Deal with – Standard cells (pre-drawn and pre-characterized) – Routing layers (M1, via12, M2, via23, …)

  • 18 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    • Intellectual Property (IP) blocks – Pre-created blocks

    • Memory • Arithmetic • Cryptographic • DSP • Controller • …

  • 19 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    I/O cell

    Macro

    Standard cells

  • 20 Physical Design Automation of VLSI Circuits and Systems

    Delay Calculation & Timing Analysis

    • Pre-characterized cells

    Input transition (ns) Output capacitance (fF)

    5th 3rd

    Delay (29ps)

    Index_1

    Index_2

  • 21 Physical Design Automation of VLSI Circuits and Systems

    Delay Calculation

    • Interconnect delay

    w

    t

    l

    s

    𝑅𝑅 = 𝜌𝜌𝑙𝑙

    𝑡𝑡 ∙ 𝑤𝑤 𝐶𝐶 = 𝜖𝜖𝑡𝑡 ∙ 𝑙𝑙𝑠𝑠 𝐷𝐷𝐷𝐷𝑙𝑙𝐷𝐷𝐷𝐷 ∝ 𝑅𝑅𝐶𝐶 ∝ 𝑙𝑙

    2

    modeling

  • 22 Physical Design Automation of VLSI Circuits and Systems

    Timing Analysis

    d1 d2

    d3 d4

    d5 d6 d7

    d8

    d9

    d10 d11

    d12 d13

  • 23 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    • What should we do? – Find the locations of the macros. – Find the locations of the standard cells. – Route the macros and the standard cells.

    • Power/ground • Signal • Clock • Bus

    – Extract parasitic RC. – Analyze the final layout.

    • Timing (clock frequency) • Power consumption (dynamic / leakage) • Area • Power integrity • Signal integrity • Thermal

  • 24 Physical Design Automation of VLSI Circuits and Systems

    Standard-Cell-Based Design

    Floorplanning (macro placement)

    Placement (standard cell placement)

    Pre-CTS optimization

    Clock-Tree Synthesis (CTS)

    Post-CTS optimization

    Routing

    Post-routing optimization

  • 25 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Layout (GDSII stream format)

    Foundry (Semiconductor manufacturing)

    TSMC, Global Foundries, …

    Bare dies

  • 26 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    • Input – Layout (GDSII stream format)

    • A set of geometric objects

    in out

    p-welln-well

    n-wellp-well

    VDD

    GND

    ①

    ①: Layer id 3, polygon { 50, 40, 70, 40, 70, 220, 50, 220, 50, 140, 20, 140, 20, 110, 50, 110, 50, 40 } ②: Layer id 7, rectangle { 10, 105, 40, 150 } ②

  • 27 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

  • 28 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    M3

    M2

    M1

    substrate

    p-epi

    n+ n+ p+ p+n-well

    p+ n+

  • 29 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    p+ substrate

    p-epi

  • 30 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Gate-oxide deposition

    SiO2

    p+ substrate

    p-epi

  • 31 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Photoresist

    SiO2

    p+ substrate

    p-epi

  • 32 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Mask

    SiO2

    p+ substrate

    p-epi

  • 33 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Expose (photolithography)

    SiO2

    p+ substrate

    p-epi

  • 34 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    After photolithography

    SiO2

    p+ substrate

    p-epi

  • 35 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Remove mask

    SiO2

    p+ substrate

    p-epi

  • 36 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Etching

    p+ substrate

    p-epi

  • 37 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Etching

    p+ substrate

    p-epi

  • 38 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Oxide deposition

    p+ substrate

    p-epi

  • 39 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Photoresist

    p+ substrate

    p-epi

  • 40 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Mask

    p+ substrate

    p-epi

  • 41 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Photolithography

    p+ substrate

    p-epi

  • 42 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    After photolithography

    p+ substrate

    p-epi

  • 43 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Etch

    p+ substrate

    p-epi

  • 44 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Doping

    p+ substrate

    p-epi p+ (p-well)

  • 45 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Doping

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

  • 46 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Poly

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

  • 47 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Etch

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

  • 48 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

    Doping

    p+ p+ n+ n+

  • 49 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

    Oxide deposition

    p+ n+ n+

    SiO2

    p+

  • 50 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

    Contact

    p+ n+ n+

    SiO2

    contact

    p+

  • 51 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

    p+ n+ n+

    SiO2

    contact

    p+

    Metal 1

  • 52 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    p+ substrate

    p-epi p+ (p-well) n+ (n-well)

    p+ n+ n+

    SiO2

    contact

    p+

    Via12

  • 53 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    Chemical-mechanical-polishing (CMP)

    p+ substrate

    p-epi

  • 54 Physical Design Automation of VLSI Circuits and Systems

    Semiconductor Manufacturing

    EE 434�ASIC and Digital Systems��Prof. Dae Hyun Kim�School of Electrical Engineering and Computer Science�Washington State UniversityVLSI DesignFrom RTL Code to a ChipFrom RTL Code to a ChipFrom RTL Code to a ChipFrom RTL Code to a ChipFrom RTL Code to a ChipVLSI DesignStandard-Cell-Based DesignStandard-Cell-Based DesignStandard Cells (Layout)Standard Cells (Layout)Design RulesStandard Cells (Layout)Standard Cells (Abstract)Standard-Cell-Based DesignStandard-Cell-Based DesignStandard-Cell-Based DesignStandard-Cell-Based DesignDelay Calculation & Timing AnalysisDelay CalculationTiming AnalysisStandard-Cell-Based DesignStandard-Cell-Based DesignSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor ManufacturingSemiconductor Manufacturing


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