ee 348: lecture supplement notes sn2 semiconductor diodes: concepts, models, & circuits 22...

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EE 348: EE 348: Lecture Supplement Notes SN2 Lecture Supplement Notes SN2 Semiconductor Diodes: Concepts, Models, & Circuits 22 January 2001

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EE 348:EE 348:Lecture Supplement Notes SN2Lecture Supplement Notes SN2

EE 348:EE 348:Lecture Supplement Notes SN2Lecture Supplement Notes SN2

Semiconductor Diodes:Concepts, Models, & Circuits

22 January 2001

Semiconductor Diodes:Concepts, Models, & Circuits

22 January 2001

EE 348 – Spring 2001

J. Choma,

Jr.Slide 2

Outline Of LectureOutline Of LectureOutline Of LectureOutline Of Lecture

• Rectification

• Semiconductor Diode Circuit Schematic Symbol Simplified Volt-Ampere Characteristic Model

Static Volt-Ampere RelationshipTime Domain Charge Control Model

• Diode Circuits Half Wave Rectifier Full Wave Rectifier Simple Limiter

EE 348 – Spring 2001

J. Choma,

Jr.Slide 3

Power Supply SystemPower Supply SystemPower Supply SystemPower Supply System

• System Voltage At “1” Has Given RMS Value And Zero Average Value Voltage At “2” Has Non-Zero Average Value; It Is A Time-Varying,

Harmonically Rich Half Or Full Wave Rectified Sinusoid Lowpass Filter Attenuates Harmonics At “2” To Produce Constant,

Time-Invariant Voltage At “3” Regulator Produces A Very Small Output Resistance Seen Looking

Back From “4”

• Load Effective Load Resistance Is VDC/IDC

Voltage Source Nature At “4” Produces Near Constant VDC, Regardless Of Current Value, IDC

S in u so id a lVo lta g eS o u rce

A C /D CC o n v erter(R ec tifie r )

L o w p a ssF ilte r

Vo lta g eR eg u la to r

LOAD

V D C

I D C1 2 3 4

EE 348 – Spring 2001

J. Choma,

Jr.Slide 4

AC To DC ConversionAC To DC ConversionAC To DC ConversionAC To DC Conversion

V

I

Linear

Netwo

rk Load

G e n e r a l S y s t e m

V

I

Load

T h é v e n i n M o d e l

V t h

Z t h

V

I

L i n e a r L o a d

V t h

Z t h Z l

V l

• Sinusoid Input:

• Output:

• Open Switch SW Whenever Vs < 0

• Plot Assumes Vs = 110 VRMS & Rl = 3Rs

SW

R l

R s

V s

V o

lo o s

l s

RV 0, when SW is open; V V , when SW is closed

R R

s pV V Sin t

-160

-120

-80

-40

0

40

80

120

160

0 90 180 270 360 450 540 630 720

Normalized Time, t (degrees)

I/O V

olt

age

(vo

lts)

Output Voltage

Input Voltage

EE 348 – Spring 2001

J. Choma,

Jr.Slide 5

Average Output VoltageAverage Output VoltageAverage Output VoltageAverage Output Voltage

• Average Value Calculation

• Conversion Efficiency Problem

SW

R l

R s

V s

V o

-160

-120

-80

-40

0

40

80

120

160

0 90 180 270 360 450 540 630 720

Normalized Time, t (degrees)

I/O V

olt

age

(vo

lts)

Output Voltage

Input Voltage

2l l

oavg p pl s l so o

1 R 1 RV V Sin x dx V Sin x dx

2 R R 2 R R

p l

oavgl s

V RV 37.1 volts

R R

EE 348 – Spring 2001

J. Choma,

Jr.Slide 6

Semiconductor Diode Semiconductor Diode Semiconductor Diode Semiconductor Diode

• Schematic Symbol

• Volt-AmpereCharacteristicEquation

• Parametric Definitions Qd(t) Excess Charge Stored In PN Junction

Qd(t) 0: Diode Is Forward BiasedQd(t) < 0: Diode Is Reverse Biased Or Back Biased

Storage Time Constant (nSec –to- pSec) vd(t) Diode Voltage (Generally < 800 mV) id(t) Diode Current (Value Depends On Junction

Area) Cj(vd) Junction Depletion Capacitance

d dd d

dd j d d

dQ ( t ) Q ( t )i ( t ) , for v ( t ) 0

dtdv ( t )

i ( t ) C ( v ) , for v ( t ) 0dt

i ( t)d

v (t)d

EE 348 – Spring 2001

J. Choma,

Jr.Slide 7

Semiconductor Diode ModelsSemiconductor Diode ModelsSemiconductor Diode ModelsSemiconductor Diode Models

• Charge Function

• Forward Bias

• Reverse Bias

d T

d d d d dd

d

v ( t ) nVd sd d

d T

dQ ( t ) Q ( t ) dQ ( t ) dv ( t ) Q ( t )i ( t )

dt dv ( t ) dt

dQ ( t ) IC ( v ) e

dv ( t ) nV

d Tv ( t ) nVd s TQ ( t ) I e 1 ; V kT q

jodd j d j d m

d

j

Cdv ( t )i ( t ) C ( v ) ; C ( v )

dtv ( t )

1V

i ( t)d

v (t)d

v (t)d

C (v )d d

i ( t)d

Q (t)d /

C (v )j d

i ( t)d

v (t)d

S ch em a ticD iagra m

F o rw a rdB ias

R everseB ias

EE 348 – Spring 2001

J. Choma,

Jr.Slide 8

Diode At DC Steady StateDiode At DC Steady StateDiode At DC Steady StateDiode At DC Steady State

• Steady State Input Voltage Is Constant Capacitances Behave As Open Circuits

• Forward Bias Current (VD 0)

• Reverse Bias Current (VD < 0) D TV nV

D s sI I e 1 I 0

D T D TV nV V nVdD s s

Q ( t )I I e 1 I e

i ( t)d

v (t)d

V D

Q (t)d / Q (V )d D /S ch em a ticD iagra m

S tea dy S ta teF o rw a rd B ias M od el

I D I D

S tea dy S ta te ,F o rw a rd B ias

V D

EE 348 – Spring 2001

J. Choma,

Jr.Slide 9

Diode DC V–I CharacteristicDiode DC V–I CharacteristicDiode DC V–I CharacteristicDiode DC V–I Characteristic

Is = 10 fA; T = 27 °C; n = 1

0

6

12

18

24

30

36

-0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 0.5 0.625 0.75

Forward Voltage (volts)

Fo

rwar

d C

urr

ent

(mA

)

0

6

12

18

24

30

36

-0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 0.5 0.625 0.75

Forward Voltage (volts)

Fo

rwar

d C

urr

ent

(mA

)

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 10

Piecewise Linear ApproximationPiecewise Linear ApproximationPiecewise Linear ApproximationPiecewise Linear Approximation

• Two Segment Approximation ID = 0 For VD V

ID – IQ = (VD – VQ)/rD For VD V

IQ Expected Quiescent, Or DC, Current Through DiodeVQ Corresponding Quiescent, Or DC, Diode Voltage

rD Incremental Diode Resistance At (IQ, VQ)

V Threshold Or Cut In Voltage Of Diode

• Operation For Diode Voltage Above Threshold Current

Slope

Threshold

Q TD T D T V nVV nV V nVD s s Q sI I e 1 I e ; I I e

Q T

Q

V nV QD s

D D T TV

IdI 1 Ie

dV r nV nV

D Q D Q D Q Q D

Q T Q

I I V V r 0 I V V r

V V nV V

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 11

Piecewise Linear DC Diode ModelPiecewise Linear DC Diode ModelPiecewise Linear DC Diode ModelPiecewise Linear DC Diode Model

• Model Parameters Threshold Voltage, V, Generally Around 700 mV For Silicon For Germanium Diodes, V Is Closer To 200 mV Diode Resistance, rD, Generally Around A Few Ohms

• Emulates Switch With Resistance And Offset Switch Closed For VD V; Switch Open For VD < V Generally rD Is Negligibly Small For Large Applied Voltages, V Can Often Be Ignored

I D

I D V D

V D

|

V

V D

I = 0D

r D0

6

12

18

24

30

36

-0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 0.5 0.625 0.75

Forward Voltage (volts)

Fo

rwa

rd C

urr

en

t (m

A)

Actual

P iecewise

L inear

0

6

12

18

24

30

36

-0.5 -0.375 -0.25 -0.125 0 0.125 0.25 0.375 0.5 0.625 0.75

Forward Voltage (volts)

Fo

rwa

rd C

urr

en

t (m

A)

Actual

P iecewise

L inear

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 12

Half Wave RectifierHalf Wave RectifierHalf Wave RectifierHalf Wave Rectifier

• Reverse Bias

• Forward Bias

s

lo s

s D l

V V

RV V V

R r R

s pV V Sin t

R l

R s

V s

V o

I DD V

R l

R s

V s

V o

D V

D VI D

V r D

R s

V s R l

V o

S ch em a ticD iagra m

F o rw a rd-B ia sedD iode

R everse -B iasedD iode

D s D s o s o D s

D o s

V V I R V V V V V I R

I 0 V 0, whenever V V

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 13

Filtered Half Wave RectifierFiltered Half Wave RectifierFiltered Half Wave RectifierFiltered Half Wave Rectifier

• Load Resistance, Rl, Is Ratio Of Desired DC Output Voltage –To– Desired DC Output Current

• Diode Conducts (Vs Vo + V) Capacitor Charges With Time Constant, [Rl||(rD + Rs)]Cl For Small Time Constant, Output Voltage Follows Input Maximum Output Voltage

To Which Capacitor Charges: lomax p

l D s

RV V V

R r R

R l

R s

V s

V o

I DD V

R l

R s

V s

V o

D V

D VI D

V r D

R s

V s R l

V o

S ch em a ticD iagra m

D iode Is C on d u ctive ,C a pa cito r C h arg es

D iode Is N o t C on du c tive ,C a pa cito r D isch arges

C l C l C l

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 14

Filtering–Cont’dFiltering–Cont’dFiltering–Cont’dFiltering–Cont’d

• Diode Non-Conductive Capacitor Voltage Does Not Change Instantaneously When Capacitor Charges To Its Maximum Voltage And The Input

Sinusoid Diminishes from Its Maximum Value, The Diode Open Circuits And The Capacitor Discharges Through The Load Resistance, Rl

Diode Begins ToConduct AgainWhen TheUnfiltered OutputRises To Meet TheDecaying Capacitor VoltageAt Time Tp. At This Point, The Output Voltage Is Vomin

See Plots On Next Slide

l lt R Co omaxV V e p l lT R C

omin omaxV V e

D V

R s

V s R l

V o

C l

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 15

Waveforms: Capacitive FilterWaveforms: Capacitive FilterWaveforms: Capacitive FilterWaveforms: Capacitive Filter

-12

-8

-4

0

4

8

12

0 3 7 10 14 17 21 24 28 31 35 38 42 45 49

Time (mSEC)

Vo

lta

ge

(v

olt

s)

Input: V s

Unfiltered Output

Filtered Output, V o

-12

-8

-4

0

4

8

12

0 3 7 10 14 17 21 24 28 31 35 38 42 45 49

Time (mSEC)

Vo

lta

ge

(v

olt

s)

Input: V s

Unfiltered Output

Filtered Output, V o

t =

0

t =

Tp

Vomax

Vomin

Ripple, Vr

T

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 16

Ripple of Filtered RectifierRipple of Filtered RectifierRipple of Filtered RectifierRipple of Filtered Rectifier

• Characteristic Voltage Equations

• Ripple Equations

• Example

• Non-Ideal Large Capacitance

l lt R Co omaxV V e p l lT R C

omin omaxV V e

l

l

r 5%

f 60 Hz C 667 F

R 500

D V

R s

V s R l

V o

C l

C l

1 0 0

p l l

p l l

T R Cr omax omin omax omax

T R C prl l p

omax l l l l

V V V V V e

TV 1r 1 e , for R C T

V R C f R C

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 17

Diode Conduction TimeDiode Conduction TimeDiode Conduction TimeDiode Conduction Time

Neighborhood Of Time t = 0

Vomax

Vomin

-12

-8

-4

0

4

8

12

0 3 7 10 14 17 21 24 28 31 35 38 42 45 49

Time (mSEC)

Vo

lta

ge

(v

olt

s)

Input: V s

Unfiltered Output

Filtered Output, V o

-12

-8

-4

0

4

8

12

0 3 7 10 14 17 21 24 28 31 35 38 42 45 49

Time (mSEC)

Vo

lta

ge

(v

olt

s)

Input: V s

Unfiltered Output

Filtered Output, V o

0 Tp

T

Re

aso

nab

leR

esu

lt

o omax

o omin omax

r omax omin omax

2r

r omaxomax

v ( t ) V Cos t

v ( T ) V V Cos( T )

V V V V 1 Cos( T )

T 2VV V T 2 r

2 V

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 18

Maximum Diode CurrentMaximum Diode CurrentMaximum Diode CurrentMaximum Diode Current

Diode CurrentOccurs At Diode CutIn Point, t = –T; Load Voltage Nearly Constant At Vomax

Vomax

Vomin

-12

-8

-4

0

4

8

12

0 3 7 10 14 17 21 24 28 31 35 38 42 45 49

Time (mSEC)

Vo

lta

ge

(v

olt

s)

Input: V s

Unfiltered Output

Filtered Output, V o

-12

-8

-4

0

4

8

12

0 3 7 10 14 17 21 24 28 31 35 38 42 45 49

Time (mSEC)

Vo

lta

ge

(v

olt

s)

Input: V s

Unfiltered Output

Filtered Output, V o

0 Tp

T

R l

R s

V s

v (t)o

i ( t)D

C l

o oD l o omax

l

v ( t ) dv ( t )i ( t ) C ; v ( t ) V Cos( t )

R dt

omax omaxDmax omax l l omax

l l

omaxDmax DC

l

V VI V C Sin( T ) C V 2 r

R R

V 2 2I 1 2 I 1 2

R r r

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 19

Transformer InputTransformer InputTransformer InputTransformer Input

• Ideal Transformer N Is Turns Ratio; Generally, N >>1 Voltage On Primary Winding Is Stepped Down By Factor Of N Current In Primary Winding Is Stepped Down By Factor Of N

• Impedance Transformation Set Vs = 0 To Find Effective Source Resistance Seen By Diode Marked Resistance Reduction

s1 s2 D sV NV ; I NI

s2 s1 s1 s s2 2

D s

V V N V I R

I NI N N

R l

R s

V s

V o

ID

C l

N :1

V s1

V s2

I sI s ID

N :1

V s1

V s2

I sP

rim

ary

Win

din

g

Secon

daryW

indin

g

Tra nsform er

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 20

Full Wave RectifierFull Wave RectifierFull Wave RectifierFull Wave Rectifier

• Center–Tapped Transformer

• Operation When Vs1 Is Positive, Vs2 = Vs3 > 0 ID2 = 0 & Il = ID1

When Vs1 Is Negative, Vs2 = Vs3 < 0 ID1 = 0 & Il = ID2

Result Is Full Wave Sinusoid For Unfiltered Case

s1s2 s3

VV V

N

R lR s

V s

V o

ID 1C l

N :1

N :1

V s1

V s2

I s

V s3

ID 2

I l

D 1

D 2

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 21

Full Wave PerformanceFull Wave PerformanceFull Wave PerformanceFull Wave Performance

• Half Wave Analysis Can Be Replicated With Minor Modifications

• Unfiltered Average Is Twice As Large As Half Wave Case Because Current Is Now Continually Supplied To Load

• Ripple Is Factor Of Two Smaller Because Capacitor Now Decays For Only ½ Period

For Same Ripple, Filter Capacitor Can Be ½ As Large In Full Wave Rectifier As In Half Wave Unit

Maximum Diode Current, Expressed In Terms Of Ripple, Is The Same As for Half Wave Case

p l lT R C prl l p

omax l l l l

TV 1r 1 e , for R C T

V R C 2 f R C

EE 348 – Spring 2001

J. Choma,

Jr.

Slide 22

Bridge Full Wave RectifierBridge Full Wave RectifierBridge Full Wave RectifierBridge Full Wave Rectifier

• Operation When Vs > 0, Current Flows From Vs Through D1-Rl-D1A-Back To Vs When Vs < 0, Current Flows From Vs Through D2-Rl-D2A-Back To Vs Full Wave Unfiltered Output Results

• Comments Two Threshold Voltages In Each Current Path Does Not Require Center Tap Transformer

R l

R s

V s

C l

I l

D 1

D 1A

D 2A

D 2