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EE 330 Lecture 16 Devices in Semiconductor Processes Capacitors MOSFETs

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Page 1: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

EE 330Lecture 16

Devices in Semiconductor Processes

• Capacitors

• MOSFETs

Page 2: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Diode Models

ID

VD

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Diode Characteristics

0

0.002

0.004

0.006

0.008

0.01

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Vd (volts)

Id (

am

ps)

Which model should be used?

The simplest model that will give acceptable results in the analysis of a circuit

Review from Last Lecture

Page 3: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Use of Piecewise Models for Nonlinear Devices

when Analyzing Electronic Circuits

Process:

1. Guess state of the device

2. Analyze circuit

3. Verify State

4. Repeat steps 1 to 3 if verification fails5. Verify model (if necessary)

Observations:

o Analysis generally simplified dramatically (particularly if piecewise model is linear)

o Approach applicable to wide variety of nonlinear deviceso Closed-form solutions give insight into performance of circuito Usually much faster than solving the nonlinear circuit directlyo Wrong guesses in the state of the device do not compromise solution

(verification will fail)

o Helps to guess right the first timeo Detailed model is often not necessary with most nonlinear deviceso Particularly useful if piecewise model is PWL (but not necessary)

o For practical circuits, the simplified approach usually applies

Key Concept For Analyzing Circuits with Nonlinear Devices

Rev

iew

fro

m L

ast

Lect

ure

Page 4: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Types of Diodes

Vd

Id Id

Vd

Id

VdVd

Id

Vd

Id

Vd

Id

Vd

Id

Vd

Id

pn junction diodes

Metal-semiconductor junction diodes

Signal or

Rectifier

Pin or

Photo

Light Emitting

LED

Laser Diode

Zener Varactor or

Varicap

Schottky Barrier

Vd

Id

Review from Last Lecture

Page 5: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

Page 6: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Capacitors

• Types

– Parallel Plate

– Fringe

– Junction

Page 7: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Parallel Plate Capacitors

C

d

A1

A2

cond1

cond2

insulator

A = area of intersection of A1 & A2

d

AC

One (top) plate intentionally sized smaller to determine C

Page 8: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Parallel Plate Capacitors

ACC d

d

AεC

areaunit

CapC If d

d

εCd

where

Page 9: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Fringe Capacitors

d

C

d

AεC

A is the area where the two plates are parallel

Only a single layer is needed to make fringe capacitors

Page 10: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Fringe Capacitors

C

Page 11: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Capacitance

2

φV

φ

V1

ACC B

FBn

B

D

jo

for

ddepletion

region

C

Junction Capacitor

d

AC

Note: d is voltage dependent

-capacitance is voltage dependent

-usually parasitic caps

-varicaps or varactor diodes exploit

voltage dep. of C

d

p

n

VD

0.6VφB n ; 0.5

is dielectric constant

Page 12: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Capacitance

2

φV

φ

V1

ACC B

FBn

B

D

jo

for

Junction Capacitor

0.6VφB n ; 0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

-4 -3 -2 -1 0 1

j0

C

C A

VD

Voltage dependence is substantial

VD

Page 13: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Basic Devices and Device Models

• Resistor

• Diode

• Capacitor

• MOSFET

• BJT

Page 14: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

VG S

RSW

CGS

S

DG

Summary of Existing Models (for n-channel)

D

S

G = 1

D

S

G = 0

Switch closed for |VGS|= large

1. Switch-Level model

2. Improved switch-level model

Switch open for |VGS|= small

Drain

Gate

Source

Page 15: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

VG

RSW

CGS

S

DG

Improved Switch-Level ModelDrain

Gate

Source

Switch-level model including gate capacitance and channel resistance

Switch closed for VGS=“1”

• Connect the gate capacitance to the source to create lumped model

• Still neglect bulk connection

Drain

Gate

Source

Bulk

Page 16: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Limitations of Existing MOSFET Models

A

B

Y

RVGS

RSW

CGS

S

DG

For minimum-sized devices in

a 0.5u process with VDD=5V

1.5fFCGS

channelp6KΩ

channeln2KΩRsw

VDD

A B

What is Y when A=B=VDDWhat is RSW if MOSFET is not minimum sized?

What is power dissipation if A is stuck at an intermediate voltage?

Better Model of MOSFET is Needed!

Page 17: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET

Poly

n-active

Gate oxide

p-sub

Page 18: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET

LEFF

L

W

Source

DrainGate

Bulk

Page 19: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET

Poly

n-active

Gate oxide

p-subdepletion region (electrically induced)

Page 20: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Apply small VGS

(VDS and VBS assumed to be small)ID=0

IG=0

IB=0

Depletion region electrically induced in channel

IDIG

IB

Termed “cutoff” region of operation

Page 21: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS

(VDS and VBS assumed to be small)ID=0

IG=0

IB=0Depletion region in channel becomes larger

IDIG

IB

Page 22: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

ID=0

IG=0

IB=0

IDIG

IB

Model in Cutoff Region

Page 23: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS more

IDRCH=VDS

IG=0

IB=0

Inversion layer forms in channel

IDIG

IB

(VDS and VBS small)

Inversion layer will support current flow from D to S

Channel behaves as thin-film resistor

Critical value of

VGS that creates

inversion layer

termed threshold

voltage, VT)

Page 24: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Triode Region of Operation

OXTGS

CHCVV

1

W

LR

0II

VVVL

WμCI

BG

DSTGSOXD

For VDS small

VDS

VBS = 0

VGS

ID

IG

IB

VDSRCH

Behaves as a resistor between

drain and source

Model in Deep Triode Region

Page 25: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Triode Region of Operation

OXTGS

CHCVV

1

W

LR

For VDS small

VBS = 0

VGS

ID

IG

IB

RCH

Resistor is controlled by the voltage VGS

Termed a “Voltage Controlled Resistor” (VCR)

Page 26: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VGS more

IDRCH=VDS

IG=0

IB=0

Inversion layer in channel thickens

IDIG

IB

(VDS and VBS small)

RCH will decrease

Termed “ohmic” or “triode” region of operation

Page 27: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS

ID=?

IG=0

IB=0

Inversion layer thins near drain

IDIG

IB

(VBS small)

ID no longer linearly dependent upon VDS

Still termed “ohmic” or “triode” region of operation

Page 28: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Triode Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

OXTGS

CHCVV

1

W

LR

0II

V2

VVV

L

WμCI

BG

DSDS

TGSOXD

For VDS larger

Model in Triode Region

Page 29: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS even more

ID=?

IG=0

IB=0

Inversion layer disappears near drain

IDIG

IB

(VBS small)

Termed “saturation”region of operation

Saturation first occurs when VDS=VGS-VT

Page 30: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Saturation Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

0II

VV2L

WμCI

VV2

VVVV

L

WμCI

V2

VVV

L

WμCI

BG

2

TGSOX

D

TGSTGS

TGSOXD

DSDS

TGSOXD

lyequivalentor

lyequivalentorFor VDS at onset of

saturation

Page 31: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

n-Channel MOSFET Operation and Model

VBS

VGS

VDS

Increase VDS even more (beyond VGS-VT)

ID=?

IG=0

IB=0

Nothing much changes !!

IDIG

IB

(VBS small)

Termed “saturation”region of operation

Page 32: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Saturation Region of Operation

VDS

VBS = 0

VGS

ID

IG

IB

0II

VV2L

WμCI

BG

2

TGSOX

D

For VDS in Saturation

Model in Saturation Region

Page 33: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Model SummaryVDS

VBS = 0

VGS

ID

IG

IB

GS T

DSD OX GS T DS GS DS GS T

2

OX GS T GS T DS GS T

G B

0 V V

VWI μC V V V V V V V V

L 2

WμC V V V V V V V

2L

I =I =0

T

Note: This is the third model we have introduced for the MOSFET

Cutoff

Triode

Saturation

OXTGS

CHCVV

1

W

LR

(Deep triode special case of triode where VDS is small )

This is a piecewise model (not piecewise linear though)

n-channel MOSFET

Model Parameters: {µ, VT, COX} Design Parameters : {W, L}

Page 34: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Model Summary

VDS

VBS = 0

VGS

ID

IG

IBVBS

TGSDSTGS

2

TGSOX

TGSDSGSDSDS

TGSOX

TGS

D

VVVVVVV2L

WμC

VVVVVV2

VVV

L

WμC

VV0

I T

Observations about this model (developed for VBS=0):

D 1 GS DS

G 2 GS DS

B 3 GS DS

I = f V ,V

I = f V ,V

I = f V ,V

This is a nonlinear model characterized by the functions f1, f2, and f3 where

we have assumed that the port voltages VGS and VDS are the independent

variables and the drain currents are the dependent variables

G BI = I = 0

n-channel MOSFET

Page 35: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

General Nonlinear Models

1 1 1 2

2 2 1 2

I = f V ,V

I = f V ,V

I1 and I2 are 3-dimensional relationships which are often difficult to visualize

v1 v2

I1 I23-terminal

Nonlinear

Device

Two-dimensional representation of 3-dimensional relationships

Page 36: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Graphical Representation of MOS Model

G BI =I =0

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5

VDS

Cutoff

Triode

Saturation

ID

VDS

VGS1

VGS2

VGS3

VGS4

Deep Triode

RegionRegion

2

DSD OX

VWI =μC

L 2

Parabola separated triode and saturation regions and corresponds to VDS=VGS-VT

GS T

DS

D OX GS T DS GS DS GS T

2

OX GS T GS T DS GS T

0 V V

VWI μC V V V V V V V V

L 2

WμC V V V V V V V

2L

T

Page 37: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

PMOS and NMOS Models

S

D

G

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5

VDS

Cutoff

Triode

Saturation

ID

VDS

2

D OX DS

WI = μC V

L

VGS1

VGS2

VGS3

VGS4

Deep Triode

RegionRegion

D

S

G

• Functional form identical, sign changes and parameter values different• Will give details about p-channel model later

Page 38: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Example: Determine the output voltage for the following circuit using

the square-law model of the MOSFET. Assume VT=1V and

μCOX=100μAV-2

Solution:

Since VGS>VT, M1 is operating in either saturation or triode region

10K

W=10u

L=2u

5V

3V

VOUT

M1

ID

Strategy will be to guess region of operation, solve, and then verify region

Page 39: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Example: Determine the output voltage for the following circuit using

the square-law model of the MOSFET. Assume VT=1V and

μCOX=100μAV-2

Solution:

10K

W=10u

L=2u

5V

3V

VOUT

M1

ID

Guess M1 in saturation

D OUT

2OXD T

5V=I 10K+V

μC WI 3-V

2L

Required verification: VDS>VGS-VT

Can eliminate ID between these 2 equations to obtain VOUT

Page 40: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Example: Determine the output voltage for the following circuit using

the square-law model of the MOSFET. Assume VT=1V and

μCOX=100μAV-2

10K

W=10u

L=2u

5V

3V

VOUT

M1

IDGuess M1 in saturation

D OUT

2OXD T

5V=I 10K+V

μC WI 3-V

2L

Required verification: VDS>VGS-VT

2-2

OUT100μAV 10

V = 5V-10K 2V2 2

OUTV = -5V

Verification: VDS=VOUT

-5 >? 2V - - 0 No! So verification fails and Guess of region is invalid

Page 41: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Example: Determine the output voltage for the following circuit using

the square-law model of the MOSFET. Assume VT=1V and

μCOX=100μAV-2

10K

W=10u

L=2u

5V

3V

VOUT

M1

IDGuess M1 in triode

D OUT

OX DSD T DS

5V=I 10K+V

μC W VI 3-V V

L 2

Required verification: VDS<VGS-VT

-2OUT

OUT OUTV100μAV 10

V = 5V-10K 2V- V2 2

OUTV = 0.515V

Verification: VDS=VOUT

0.515 <? 2V Yes! So verification succeeds and triode region is valid

OUTOUT OUT

VV = 5V- 5 2V- V

2

Solving for VOUT, obtain

OUTV = 0.515V

Page 42: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

Stay Safe and Stay Healthy !

Page 43: EE 330 Lecture 16 Devices in Semiconductor Processesclass.ece.iastate.edu/ee330/lectures/EE 330 Lect 16 Fall... · 2020. 9. 21. · Diode Models I D V D s 0 2 4 6 8 1 0 1 2 3 4 5

End of Lecture 16