EE-323 MICROWAVE MEASUREMENTS LABORATORY

Prof. Atif Shamim Electrical Engineering Program

King Abdullah University of Science and Technology

Lecture 3

Low Noise Amplifier

Block Diagram of a Communication System

Information Source

Modulator Transmitter

Information Sink Demodulator Receiver

Antenna

Mixer, PLL, VCO Driver, VCO,

Power Amplifier Music, voice, video, data, bits, +compression+ coding

Low noise amplifier (LNA) Mixer, VGA, VCO + PLL

Video display, speakers, couch potato, web browser

(detect + decode + decompress)

Back-end Front-end

F1 G1

F2 G2

F3 G3

Pin + Ns = 1 + 2 11 + 3 112

LNA in a Receiver

The first stag of a receiver front bend has the dominant effect on the noise performance of the overall system

A Low Noise Amplifier (LNA) is therefore used in a receiver chain

Low Noise Amplifier

Generally, it is not possible to attain both the minimum noise figure and the maximum gain for an amplifier, so some sort of compromise must be made.

Remember: noise figure of a two port device can be expressed as

(11.53)

(11.54a)

Instead of using admittances we can use reflection coefficients

(11.54b)

(11.55)

S is the source reflection coefficient defined in Fig. 11.1 . Fmin, opt and RN are characteristics of the particular transistor being used and are generally given, but can be measured or simulated using models. Using (11.54), we can get

(11.56)

(11.58)

(11.57)

Using Noise and Gain Circles

Example LNA Design

For transistor sizing, we first need to find the current density in the process that will provide the lowest minimum NF (NFmin), and set the current density in the transistor to be this value regardless of the size of the device.

The minimum NF for a process can be found from device measurements, but for the circuit designer it can be determined by the use of simulators such as Cadence or SPICE.

Transistor Sizing (Cases where size control is available like ICs)

Example: CMOS 90 nm Process L = 2 x Lmin = 180nm W = 50 m I = 3.4 mA Current Density = I/W =3.4/50 = 68 A / m

NFmin is @ 3.4mA

Drain current

Once the current density is known, then the size of the transistor can be chosen based on the design constrains.

If current through the device is given, the appropriate device size for NFmin can be obtained. In above example, if Id = 10mA the transistor size for NFmin should be (10 mA) / (68 A / m) = 147 m ).

If channel current is not fixed, the device should chosen so that the real part of the optimum source impedance for lowest noise figure is equal to 50 Ohm. The current must be adjusted in this step to keep the current density at its optimal level determined in step 1. (This will help to simultaneously match for the noise and the impedance)

Transistor Sizing

Example: CMOS 90 nm Process L = 2 x Lmin = 180nm Ropt = 50 ohm @ W = 28 m Hence I = (68 A / m) x (28 m) =1.904 mA

Ropt = 50 ohm @ W = 28 m

Transistor Size

We can design LNA using noise parameters Fmin, RN, and Yopt = Gopt + jBopt

MOSFET LNA

In order to have low noise figure, we would like Ys = Yopt In order to have best impedance match (max power), we would like Ys = Yin* Usually these two are very different, so how can we get good noise and power match? Solution: Inductive source degeneration to make the input at the gate look resistive rather than capacitive This will decrease gain somewhat, but it will resonate out Cgs, if we pick Ls properly

Input Noise and Impedance Match

Simple analysis of the circuit below gives that

Inductive Degeneration

Simultaneous Noise and Impedance Matching

Step 1. Gopt = Y0 (through device sizing) Step 2. Right current density for Nfmin Step 3. Choose current with the same width suitable for Gopt so that the that current density can be maintained

The cascoded LNA is considered as the traditional and the most popular choice of topology

Cascode transistor provides better output to input isolation (S12)

Reduced Miller capacitance for better gain performance

The current is reused and hence there is no extra cost in power consumption

The drawback is that an extra von (VGS-VTh ) is required to bias the cascode transistor in the saturation region.

Provides higher output impedance and higher gain as compared to a CS stage

Cascode

References

The Design of CMOS Radio-Frequency Integrated Circuits, Second Edition by Thomas H. Lee

Radio Frequency Integrated Circuit Design by John Rogers and Calvin Plett

Microwave and RF Circuits and Systems course notes by Dr. Brian Frank, Department of ECE, Queens University

EE-323 Microwave Measurements LaboratoryBlock Diagram of a Communication SystemLNA in a ReceiverLow Noise AmplifierSlide Number 5Slide Number 6Slide Number 7Slide Number 8Using Noise and Gain CirclesExample LNA DesignSlide Number 11Slide Number 12Transistor Sizing (Cases where size control is available like ICs)Transistor SizingMOSFET LNAInput Noise and Impedance MatchSlide Number 17Slide Number 18Slide Number 19Inductive DegenerationSimultaneous Noise and Impedance MatchingSlide Number 22CascodeReferences