Stanford University

EE 316: Advanced VLSI DevicesLecture 0 – Administrative Details

H S Philip WongH.-S. Philip WongProfessor of Electrical Engineering Stanford University, Stanford, California, U.S.A.hspwong@stanford eduhspwong@stanford.edu

http://www.stanford.edu/~hspwong

Department of Electrical EngineeringCenter for Integrated Systems EE 316

Stanford University

Administrative Details

Title: Advanced VLSI Devices Title: Advanced VLSI Devices

Days/Times/Classroom:– July12-15,14:00-16:00. Institute of Microelectronics Building,July12 15,14:00 16:00. Institute of Microelectronics Building,

room 308 at Tsinghua University;

– July18-21, 8:30-10:30AM, classroom: Science Building 1, room 1131 at PKU;1131 at PKU;

– July 25-28, 8:30-10:30AM,classroom: Institute of Microelectronics Building, room 308 at Tsinghua University;

– August 1-4, 8:30-10:30AM, classroom: Science Building 1, room 1131 at PKU;

Course website: TBD

Department of Electrical EngineeringH.-S. Philip Wong0-2 EE 316

Course website: TBD

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Instructor and TA’s

Instr ctor Prof H S Philip WongInstructor: Prof. H.-S. Philip Wong

Office: TBD

Email: hspwong@stanford.edu

Teaching Assistant:

徐晓庆

Department of Electrical EngineeringH.-S. Philip Wong0-3 EE 316

Stanford University

Something About Your Professor

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http://www stanford edu/ hspwong/

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http://www.stanford.edu/~hspwong/

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Poly-silicon

Tox=16A

Tsi=7 nm

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Drain

Tsi=7 nm

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H. Shang et al., IEDM 2002

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M. Yang et al., IEDM2003

60nm

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Department of Electrical EngineeringH.-S. Philip Wong0-4 EE 316

Buried oxide

SiGe

Si

HfO2

SiO2

Stanford University

徐晓庆About Your TA –徐晓庆

Department of Electrical EngineeringH.-S. Philip Wong0-5 EE 316

Stanford University

Course Objectives

At the end of the course you will be able to At the end of the course, you will be able to– Make projections about CMOS device scaling and how they

affect circuit/system performance– Recognize the relevant device physics that underlies CMOS

device design– Go to a conference or read a journal article about CMOS

d i d th k l d bt i d i thi tdevices and use the knowledge obtained in this course to understand the papers

– Design a state-of-the-art MOSFET, project its performance• Use device modeling (TCAD) tools and interpret results from

device modeling

Develop an intuitive feel in addition to solving

Department of Electrical EngineeringH.-S. Philip Wong0-6 EE 316

equations

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Homework and Grading PolicyHomework and Grading Policy

Grading:– Exam: 50%– Exam: 50%

• Date to be determined– Homework: 50%

Homework:– About twice a week

– Some homework are literature reading assignments with specific questions aimed at probing your understanding of the material• Develop skills in reading current literature with focused reading• Cover topics that we do not have time to cover in the lectures• Same skills required for PhD research or R&D job in companies

Department of Electrical EngineeringH.-S. Philip Wong0-7 EE 316

q j p

Stanford University

Late Homework Policy

S bmit b d e date class time f ll credit Submit by due date, class time – full credit

Submit by next day, class time – 25% off

Submit by day after next, class time – 50% off

After that, no credit

Solutions will be posted soon after the homework is collected

Department of Electrical EngineeringH.-S. Philip Wong0-8 EE 316

Stanford University

Q ti ?Questions?

Department of Electrical EngineeringH.-S. Philip Wong0-9 EE 316

Stanford University

TextbookTextbook: Y. Taur & T. H. Ning, “Fundamentals of Modern VLSI Devices,”

Cambridge University Press (1998)– ISBN # 0-521-55056-4 (hardcopy, 1st edition)– ISBN # 0-521-55959-6 (paperback, 1st edition)– ISBN-13: 9780521832946 (Hardcopy, 2nd edition)– Roughly, I will cover Chapters 1 – 5 and 10

Course notes:– Available on-line (course website), posted before the lecture

• Notes are organized in “Lectures” (0 – 10) around major topicsg ( ) j p• Number in the lower bottom are “x-y”, where x=Lecture #, y=slide #• Plenty of references at most slides for further study – please read them

– Course notes sources: courtesy of Prof. S. Simon Wong, Prof. Krishna Saraswat Prof. Yuan Taur (UCSD) Dr Tak H Ning (IBM

Department of Electrical EngineeringH.-S. Philip Wong0-10 EE 316

Krishna Saraswat, Prof. Yuan Taur (UCSD), Dr. Tak H. Ning (IBM Research)

Stanford University

ReferencesDevice physics: R. Muller, T. Kamins, M. Chan, “Device Electronics for Integrated Circuits,” Wiley,

3rd edition R. F. Pierret, “Semiconductor Device Fundamentals,” Addison-Wesley S.M. Sze, “Physics of Semiconductor Devices,” Wiley, 2nd edition S.M. Sze, K.K. Ng, “Physics of Semiconductor Devices,” Wiley, 3rd edition C.Y. Chang & S.M. Sze, “ULSI Technology,” McGraw Hill (1996) C.Y. Chang & S.M. Sze, “ULSI Devices,” Wiley (2000) Dutton & Yu, “Technology CAD – Computer Simulation of IC Processes and

Devices,” Kluwer E. Nicollian & J. Brews, “MOS (Metal Oxide Semiconductor) Physics and

Technology,” Wiley (1982)G “ M. Lundstrom, J. Guo, “Nanoscale Transistors: Device Physics, Modeling and

Simulation,” Springer (2006)Conference proceedings: IEEE International Electron Devices Meeting (IEDM) – access: IEEE Xplore

Department of Electrical EngineeringH.-S. Philip Wong0-11 EE 316

Symposium of VLSI Technology – access: IEEE Xplore IEEE journals: http://ieeexplore.ieee.org/Xplore/dynhome.jsp?tag=1

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Assumptions and Background

EE 216 EE 216

Muller & Kamins book

Chapter 2 (except 2.4, 2.5) of Taur & Ning book (2nd

edition)

U d d t l l k l d f d i Undergraduate level knowledge of device fabrication

Undergraduate level knowledge of CMOS circuits Undergraduate level knowledge of CMOS circuits

Department of Electrical EngineeringH.-S. Philip Wong0-12 EE 316

Stanford University

Topics To Be Covered (1 of 2) Overview of the semiconductor industry MOSFET – MOS capacitor, MOSFET long channel behaviorp , g Si MOSFET device scaling, non-scaling factors, reading the ITRS Short-channel MOSFET Device modelingDevice modeling

– TCAD tools, fundamentals of numerical device simulation, interpretation of device simulation results and tricks of the trade

– TA sessions for Sentaurus modeling tool prior to lecture

MOSFET electrostatics– Channel length, scale length theory, minimum channel length– PDSOI, FDSOI, double-gate, FinFET, multi-gate FET– Threshold voltage, quantum effects– Non-uniform channel doping, halo, super-halo

MOSFET electrodynamics

Department of Electrical EngineeringH.-S. Philip Wong0-13 EE 316

– Carrier mobility, velocity saturation, scattering theory, ballistic transport– Strain effects

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Topics To Be Covered (2 of 2)

High field effectsHigh field effects– Impact ionization and breakdown, band-to-band tunneling, tunneling into gate

dielectrics, hot carriers, dielectric degradation mechanisms

CMOS performance factors– CMOS circuit elements, propagation delay, delay metrics, power dissipation– Interconnect R and C, interconnect scaling– Parasitic elements, device pitch scaling– Device design tradeoff

Department of Electrical EngineeringH.-S. Philip Wong0-14 EE 316

Stanford University

Q ti ?Questions?

Department of Electrical EngineeringH.-S. Philip Wong0-15 EE 316