ecs 7th sem-cse-unit-3

Embedded Computing Systems

Unit – III

Text Book Used:

Wayne Wolf: Computers as Components,

Principles of Embedded Computing Systems

Design, 2nd Edition, Elsevier, 2008.

By

Dr. K. Satyanarayan Reddy

CiTECH, B’lore-36.

Bus-Based Computer SystemsTHE CPU BUS: A computer system

comprises of the CPU; it alsoincludes memory and I/Odevices.

The bus is the mechanism bywhich the CPU communicateswith Memory and Devices.

A Bus is, at a minimum, acollection of wires, but the busalso defines a protocol by whichthe CPU, memory, and devicescommunicate.

One of the major roles of the busis to provide an interface tomemory.

Bus Protocols: The basic buildingblock of most bus protocols isthe Four-cycle Handshake, asshown in adjacent Figure :

October 6, 2014 ECS Lecture Notes VII Sem CSE (VTU), 3rd Unit: By Dr. K Satyanarayan Reddy 2

The Four-cycle Handshake

Bus-Based Computer Systems cont’d….Bus Protocols cont’d.:

1. Device 1 raises its output to signal an enquiry, which tellsdevice 2 that it should get ready to listen for data.

2. When device 2 is ready to receive, it raises its output to signalan acknowledgment.

At this point, devices 1 and 2 can transmit or receive.

3. Once the data transfer is complete, device 2 lowers its output,signaling that it has received the data.

4. After seeing that ack has been released, device 1 lowers itsoutput.

At the end of the handshake, both handshaking signals are low,just as they were at the start of the handshake.

The system has thus returned to its original state in readinessfor another handshake-enabled data transfer.


The term bus is used in 2 ways. A set of related wires, such as data/address wires also the termmay mean a protocol for communicating between components.

To avoid confusion, the term bundle will be used to refer to a set of related signals.

The fundamental bus operations are READING and WRITING.

Figure below shows the structure of a typical bus that supports reads and writes.

The major components follow:

■ Clock provides synchronization to the bus components,

■ R/W is true when the bus is reading and false when the bus is writing,

■ Address is an a-bit bundle of signals that transmits the address for an access,

■ Data is an n-bit bundle of signals that can carry data to or from the CPU, and

■ Data ready signals when the values on the data bundle are valid.


Bus-Based Computer Systems cont’d….

A typical Microprocessor Bus

All transfers on this basic bus are controlled by the CPU, which can read orwrite a device or memory, but devices or memory cannot initiate a transferon their own.

This is reflected by the fact that R/W and Address are unidirectional signals,since only the CPU can determine the address and direction of the transfer.

The behavior of a bus is specified with a Timing Diagram, which shows how thesignals on a bus change over time, but since values like the address and datacan take on many values, some standard notation is used to describe signals,as shown in Figure below:



A’s value is known at all times, so it is shown as a standard waveform that changesbetween 0 and 1. B and C alternate between changing and stable states.

A stable signal has, as the name implies, a stable value that could be measured by anoscilloscope.

e.g.: An address bus may be shown as stable when the address is present, but thebus’s timing requirements are independent of the exact address on the bus.

A signal can go between a known 0/1 state and a stable/changing state.

A changing signal does not have a stable value. Changing signals should not be usedfor computation.

To be sure that signals go to their proper values at the proper times, timing diagrams

sometimes show Timing Constraints.

The Timing Constraints are drawn in two different ways, depending on the amount oftime between events or on the order of events.

e.g.: The timing constraint from A to B, shows that A must go high before B becomesstable.

The constraint from A to B also has a time value of 10 ns, indicating that A goeshigh at least 10 ns before B goes stable.



The adjacent figure shows a timingdiagram for the example bus.

The diagram shows a Read and a Write.

Timing Constraints are shown only for theRead operation, but similarconstraints apply to the writeoperation.

The bus is normally in the read modesince that does not change the stateof any of the devices or memories.

Note: The direction of data transfer onbidirectional lines is not specified inthe timing diagram.

During a read, the external device ormemory is sending a value on thedata lines, while during a write theCPU is controlling the data lines.


Timing Diagram for the Bus


The sequence of operations for a READ on the Timing Diagram asfollows:

■ A read or write is initiated by setting address enable high after theclock starts to rise.

Setting R/W = 1 to indicate a read, and the address lines are set tothe desired address.

■ After 1 clock cycle, the memory or device is expected to assert thedata value at that address on the data lines.

Simultaneously, the external device specifies that the data are validby pulling down the data ready line.

This line is active low, meaning that a logically true value is indicatedby a low voltage, in order to provide increased immunity toelectrical noise.

■ The CPU is free to remove the address at the end of the clock cycleand must do so before the beginning of the next cycle.



The Handshake that tells the CPU andDevices when data are to betransferred is formed by data readyfor the acknowledge side, but isimplicit for the enquiry side.

Since the bus is normally in read mode,“enq” does not need to be asserted,but the “acknowledge” must beprovided by Data Ready.

The Data Ready signal allows the bus tobe connected to devices that areslower than the bus.

As shown in adjacent Figure, the externaldevice need not immediately assertdata ready.

The cycles between the minimum time atwhich data can be asserted and whenit is actually asserted are known asWait States. Wait states arecommonly used to connect slow,inexpensive memories to buses.


A wait state on a read operation


The bus handshaking signals can also beused to perform Burst Transfers, asillustrated in Figure on right.

In this Burst Read Transaction, the CPUsends one address but receives asequence of data values.

Here an extra line is added to the bus,called Burst9, which signals when atransaction is actually a burst.

Releasing the burst9 signal tells thedevice that enough data has beentransmitted.

To stop receiving data after the end ofdata 4, the CPU releases the burst9signal at the end of data 3 since thedevice requires some time torecognize the end of the burst.

Those values come from successivememory locations starting at thegiven address.


A burst read transaction


Some buses provide Disconnected Transfers.In these buses, the request and response are

separate.A first operation requests the transfer.The bus can then be used for other

operations.The transfer is completed later, when the data

are ready.The state machine view of the bus transaction

is also helpful and a useful complement tothe timing diagram.

Figure on right shows the CPU and devicestate machines for the read operation.

As with a timing diagram, not all the possiblevalues of address and data lines areshown, instead transitions of controlsignals are dealt with.

When the CPU decides to perform a readtransaction, it moves to a new state,sending bus signals that cause the deviceto behave appropriately.

The device’s state transition graph captures itsside of the protocol.


State diagrams for the bus read transaction


Some buses have Data Bundles that are smallerthan the word size of the CPU, thus usingfewer data lines reduces the cost of thechip.

Byte addresses are sequentially sent over thebus, receiving one byte at a time; the bytesare assembled inside the CPU’s bus logicbefore being presented to the CPU proper.

Some buses use multiplexed address and data.

As shown in Figure on right, additional controllines are provided to tell whether the valueon the address/data lines is an address ordata.

Typically, the address comes first on thecombined address/data lines, followed bythe data.

The address can be held in a register until thedata arrive so that both can be presentedto the device (such as a RAM) at the sametime.


Bus signals for multiplexing address and data


Direct Memory Access (DMA)Standard bus transactions require the CPU to be in the middle of

every read and write transaction.

However, there are certain types of data transfers in which the CPUdoes not need to be involved.

e.g.: A high-speed I/O device may wish to transfer a block of datainto memory.

This capability requires that some unit other than the CPU, to beable to control operations on the bus.

Direct memory access (DMA) is a bus operation that allows readsand writes not controlled by the CPU.

A DMA transfer is controlled by a DMA controller, which requestscontrol of the bus from the CPU.

After gaining control, the DMA controller performs read and writeoperations directly between devices and memory.


Figure below shows the configuration of a bus with a DMA controller.

The DMA requires the CPU to provide two additional bus signals:

■ The bus request is an input to the CPU through which DMAcontrollers ask for ownership of the bus.

■ The bus grant signals that the bus has been granted to theDMA controller.


Direct Memory Access cont’d….

A device that can initiate its own bus transfer is known as a Bus Master.

The DMA controller uses bus request & bus grant signals to gain control ofthe bus using a classic four-cycle handshake.

The bus request is asserted by the DMA controller when it wants to controlthe bus, and the bus grant is asserted by the CPU when the bus is ready.

The CPU will finish all pending bus transactions before granting control of thebus to the DMA controller.

When it does grant control, it stops driving the other bus signals: R/W,address, and so on.

Upon becoming Bus Master, the DMA controller has control of all bus signalsand it can perform reads and writes using the same bus protocol as withany CPU-driven bus transaction.

Memory and devices do not know whether a read or write is performed bythe CPU or by a DMA controller.

After the transaction is finished, the DMA controller returns the bus to theCPU by de-asserting the bus request, causing the CPU to de-assert the busgrant.



The CPU controls the DMA operation through registersin the DMA controller.

A typical DMA controller includes the following threeregisters:■ A starting address register specifies where thetransfer is to begin.■ A length register specifies the number of wordsto be transferred.■ A status register allows the DMA controller to beoperated by the CPU.

The CPU initiates a DMA transfer by setting the startingaddress and length registers appropriately andthen writing the status register to set its starttransfer bit.

After the DMA operation is complete, the DMAcontroller interrupts the CPU to tell it that thetransfer is done.

The CPU’s role during a DMA transfer: As the CPUcannot use the bus.

As shown in adjacent Figure 4.10, if the CPU hasenough instructions and data in the cache andregisters, it may be able to continue doing usefulwork for quite some time oblivious of the DMAtransfer.

But once the CPU needs the bus, it stalls until the DMAcontroller returns bus mastership to the CPU.



UML sequence diagram of systemactivity around a DMA transfer

System Bus ConfigurationsA microprocessor system generally has more than one bus.

As shown in Figure below, high-speed devices may be connected to a high-performance bus, while lower-speed devices are connected to a different bus.

A small block of logic known as a Bridge allows the buses to connect to each other.

The advantage of using multiple buses and bridges are:

■ Higher-speed buses may provide wider data connections.

■ A high-speed bus usually requires more expensive circuits and connectors. The cost of low-speeddevices can be held down by using a lower-speed, lower-cost bus.

■ The bridge may allow the buses to operate independently, thereby providing some parallelism in

I/O operations.


A multiple bus system

Operation of a bus Bridge: The bridge is a slave on the fast bus and the master of the slow bus.

The bridge takes commands from the fast bus (on which it is a slave) and issues those commands on theslow bus( of which it is a master).

It also returns the results from the slow bus to the fast bus; e.g.: It returns the results of a read on theslow bus to the fast bus.

The upper sequence of states handles a write from the fast bus to the slow bus.

These states must read the data from the fast bus and set up the handshake for the slow bus.

Operations on the fast and slow sides of the bus bridge should be overlapped as much as possible toreduce the latency of bus-to-bus transfers.

Similarly, the bottom sequence of states reads from the slow bus and writes the data to the fast bus.


UML state diagram of bus bridge operation

System Bus Configurations cont’d….

AMBA BusThe AMBA bus supports CPUs, memories, and peripherals integrated in a system-on-silicon.

As shown in Figure below, the AMBA specification includes two buses. The AMBA High-performance Bus (AHB) is optimized for high-speed transfers and is directly connected tothe CPU which supports several high-performance features: pipelining, burst transfers, splittransactions, and multiple bus masters.

A bridge can be used to connect the AHB to an AMBA Peripherals Bus (APB).

This bus is designed to be simple and easy to implement; it also consumes relatively littlepower.

The AHB assumes that all peripherals act as slaves, simplifying the logic required in both theperipherals and the bus controller. It also does not perform pipelined operations, whichsimplifies the bus logic.


Elements of the ARM AMBA bus system

Memory Device Organization: A memory ischaracterized by its capacity, such as 256MB.

e.g: A 256-MB memory may be available intwo versions:

■ As a 64M 4-bit array, a single memoryaccess obtains an 8-bit data item, witha maximum of 226 different addresses.

■ As a 32M 8-bit array, a single memoryaccess obtains a 1-bit data item, witha maximum of 223 different addresses.

The height/width ratio of a memory is knownas its Aspect Ratio.

The best aspect ratio depends on the amountof memory required.

Internally, the data are stored in a two-dimensional array of memory cells asshown in adjacent Figure.

Because the array is stored in two dimensions,the n-bit address received by the chip issplit into a row and a column address(with n = r + c).


Internal organization of a memory device

MEMORY DEVICES

MEMORY DEVICES cont’d….The row and column select a particular memory cell.

If the memory’s external width is 1 bit, the columnaddress selects a single bit; for wider data widths, thecolumn address can be used to select a subset of thecolumns.

Most memories include an enable signal that controlsthe tri-stating of data onto the memory’s pins.

A read/write signal (R/W in the figure) on read/writememories controls the direction of data transfer;memory chips do not typically have separate read andwrite data pins.


Random-Access MemoriesRandom Access memories can be both read and written. They are

called random access because addresses can be read in any order.

Most bulk memory in modern systems is dynamic RAM (DRAM).

DRAM is very dense; it does, however, require that its values berefreshed periodically since the values inside the memory cellsdecay over time.

The dominant form of dynamic RAM today is the synchronous DRAMs(SDRAMs), which uses clocks to improve DRAM performance.

SDRAMs use Row Address Select (RAS) and Column Address Select(CAS) signals to break the address into two parts, which select theproper row and column in the RAM array.

Signal transitions are relative to the SDRAM clock, which allows theinternal SDRAM operations to be pipelined.



As shown in adjacent Figure, transitions onthe control signals are related to a clock.

RAS and CAS can therefore become valid atthe same time.

The address lines are not shown in fulldetail here; some address lines may notbe active depending on the mode inuse.

SDRAMs use a separate refresh signal tocontrol refreshing.

DRAM has to be refreshed roughly once permillisecond and DRAMs refresh part ofthe memory at a time instead ofrefreshing the entire memory at once.

When a section of memory is beingrefreshed, it cannot be accessed untilthe refresh is complete.

The memory refresh occurs over fairly fewseconds so that each section isrefreshed every few microseconds.

Random-Access Memories cont’d….

Timing diagram for a read on a synchronous DRAM

Read-only memories (ROMs) are preprogrammed with fixed data.

They are very useful in embedded systems since a great deal of the code, and perhaps somedata, does not change over time.

There are several types of ROM available. The factory-programmed ROM (sometimes calledmask-programmed ROM) and field-programmable ROM.

Factory-programmed ROMs are ordered from the factory with particular programming.

ROMs can typically be ordered in lots of a few thousand, but clearly factory programming isuseful only when the ROMs are to be installed in some quantity.

Field-programmable ROMs, on the other hand, can be programmed in the lab.

Flash memory is the dominant form of field-programmable ROM and is electrically erasable.

Flash memory uses standard system voltage for erasing and programming, allowing it to bereprogrammed inside a typical system.

Early flash memories had to be erased in their entirety; modern devices allow memory to beerased in blocks.

Most flash memories today allow certain blocks to be protected, where the boot-up code iskept and other memory blocks on the device can be updated. Such form of flash iscommonly known as Boot-block flash.


Read Only Memories (ROM)

I/O DEVICES


Timers and Counters: Timers and counters aredistinguished largely on the basis of their usage, nottheir logic.

Both are built from adder logic with registers to hold thecurrent value, with an increment input that adds one tothe current register value.

However, a Timer has its count connected to a periodicclock signal to measure time intervals, while a Counterhas its count input connected to an aperiodic signal inorder to count the number of occurrences of someexternal event.

Because the same logic can be used for either purpose, thedevice is often called a Counter/Timer.

The adjacent Figure shows enough of the internalsof a Counter/Timer to illustrate its operation.

An n-bit counter/timer uses an n-bit register tostore the current state of the count and anarray of half subtractors to decrement thecount when the count signal is asserted.

Combinational logic checks when the count equalszero; the done output signals the zero count.

It is often useful to be able to control the time-out,rather than require exactly 2n events to occur.

For this purpose, a reset register provides the valuewith which the count register is to be loaded.

The Counter/Timer provides logic to load the resetregister.

Most counters provide both cyclic and acyclicmodes of operation.

In the cyclic mode, once the counter reaches thedone state, it is automatically reloaded and thecounting process continues.

In acyclic mode, the counter/timer waits for anexplicit signal from the microprocessor toresume counting.


Internals of a Counter/Timer

I/O DEVICES cont’d….

A Watchdog Timer is an I/O device that isused for internal operation of a system.

As shown in Figure, the Watchdog Timer isconnected into the CPU bus and also tothe CPU’s reset line.

The CPU’s software is designed toperiodically reset the watchdog timer,before the timer ever reaches its time-out limit.

If the watchdog timer ever does reach thatlimit, its time-out action is to reset theprocessor.

In that case, the presumption is that eithera Software Flaw or Hardware Problemhas caused the CPU to misbehave.

Rather than diagnosing the problem, thesystem is reset to get it operational asquickly as possible.


I/O DEVICES cont’d….

A Watchdog Timer

A/D and D/A ConvertersANALOG/DIGITAL (A/D) and Digital/Analog (D/A) converters (typically

known as ADCs and DACs, respectively) are often used to interfacenon digital devices to embedded systems.

Because A/D conversion requires more complex circuitry, it requires asomewhat more complex interface.

Analog/digital conversion requires sampling the analog input beforeconverting it to digital form.

A control signal causes the A/D converter to take a sample and digitizeit.

A typical A/D interface has, in addition to its analog inputs, two majordigital inputs.

A Data Port allows A/D registers to be read and written, and a ClockInput tells when to start the next conversion.

D/A conversion is relatively simple, so the D/A converter interfacegenerally includes only the data value.

The input value is continuously converted to analog form.


KeyboardsA keyboard is basically an array of switches, but it may include some internal logic to help

simplify the interface to the microprocessor.

A switch uses a mechanical contact to make or break an electrical circuit.

The major problem with mechanical switches is that they bounce as shown in Figure below.

When the switch is depressed by pressing on the button attached to the switch’s arm, theforce of the depression causes the contacts to bounce several times until they settle down.

If this is not corrected, it will appear that the switch has been pressed several times, givingfalse inputs.

A hardware debouncing circuit can be built using a one-shot timer. Software can also be usedto debounce switch inputs. A raw keyboard can be assembled from several switches.

Each switch in a raw keyboard has its own pair of terminals, making raw keyboards impracticalwhen a large number of keys is required.


Switch Bouncing

More expensive keyboards, such as those used in PCs,actually contain a microprocessor to preprocessbutton inputs.

PC keyboards typically use a 4-bit microprocessor toprovide the interface between the keys and thecomputer. The microprocessor can providedebouncing, but it also provides other functions aswell.

An encoded keyboard uses some code to representwhich switch is currently being depressed. At theheart of the encoded keyboard is the scannedarray of switches shown in adjacent Figure.

Unlike a raw keyboard, the scanned keyboard arrayreads only one row of switches at a time.

The demultiplexer at the left side of the array selectsthe row to be read. When the scan input is 1, thatvalue is transmitted to one terminal of each key inthe row.

If the switch is depressed, the 1 is sensed at thatswitch’s column. Since only one switch in thecolumn is activated, that value uniquely identifies akey.

The row address and column output can be used forencoding, or circuitry can be used to give adifferent encoding.


A Scanned Key Array

Keyboards cont’d….

There are 2 problems associated with encoding the keyboard listed asfollows:

1. Combinations of keys may not be represented.

e.g.: On a PC keyboard, the encoding must be chosen so thatcombinations such as control-Q can be recognized and sent to the PC.

2. Rollover may not be allowed.

e.g.: if “a” is pressed and then “b” is pressed before releasing “a,” inmost applications there is need to send an “a” followed by a “b” throughthe keyboard.

Rollover is very common in typing at even modest rates.

A naive implementation of the encoder circuitry will simply throw awayany character depressed after the first one until all the keys are released.

The keyboard microcontroller can be programmed to provide n-key rollover,so that rollover keys are sensed, put on a stack, and transmitted insequence as keys are released.


Keyboards cont’d….

Light Emitting Diodes (LEDs)LED’s are often used as simple displays by themselves, and arrays of

LEDs may form the basis of more complex displays.

Figure below shows how to connect an LED to a digital output.

A resistor is connected between the output pin and the LED to absorbthe voltage difference between the digital output voltage and the0.7 V drop across the LED.

When the digital output goes to 0, the LED voltage is in the device’s offregion and the LED is not on.


An LED connected to a digital output

DisplaysA display device may be either directly driven

or driven from a frame buffer.The displays with a small number of elements

are driven directly by logic, while largedisplays use a RAM frame buffer.

The n-digit array, shown in adjacent Figure, isa simple example of a display that isusually directly driven.

A single-digit display typically consists ofseven segments; each segment may beeither an LED or a Liquid Crystal Display(LCD) element.

This display relies on the digits being visiblefor some time after the drive to the digit isremoved, which is true for both LEDs andLCDs.

The digit input is used to choose which digit iscurrently being updated, and the selecteddigit activates its display elements basedon the current data value.

The display’s driver is responsible forrepeatedly scanning through the digitsand presenting the current value of eachto the display.


An n-digit Display

A Frame Buffer is a RAM that is attached to the system bus.

The microprocessor writes values into the frame buffer in whateverorder is desired.

The pixels in the frame buffer are generally written to the display inraster order by reading pixels sequentially.

Many large displays are built using LCD. Each pixel in the display isformed by a single liquid crystal.

LCD displays present a very different interface to the systembecause the array of pixel LCDs can be randomly accessed.

Modern LCD panels use an active matrix system that puts atransistor at each pixel to control access to the LCD.

Early LCD panels were called passive matrix because they relied on atwo-dimensional grid of wires to address the pixels.

Active matrix displays provide higher contrast and a higher-qualitydisplay.


Displays cont’d….

TouchscreensA Touchscreen is an input device overlaid on an output device. The Touchscreen registers the position of a

touch to its surface. By overlaying this on a display, the user can react to information shown on thedisplay.

The 2 most common types of touchscreens are Resistive and Capacitive.

Resistive Touchscreen: It uses a 2D voltmeter to sense position. As shown in Figure below, the touchscreenconsists of two conductive sheets separated by spacer balls.

The top conductive sheet is flexible so that it can be pressed to touch the bottom sheet. A voltage isapplied across the sheet; its resistance causes a voltage gradient to appear across the sheet.

The top sheet samples the conductive sheet’s applied voltage at the contact point.

An Analog/Digital Converter is used to measure the voltage and resulting position.

The touchscreen alternates between x and y position sensing by alternately applying horizontal andvertical voltage gradients.


Cross section of a Resistive Touchscreen

COMPONENT INTERFACINGMemory Interfacing: The memory structure will be simple, if a memory

is bought which is of the exact size that is needed.

If more memory is needed than that can be bought in a single chip,then several such memory chips are needed to construct thememory of required size.

e.g. if 4GB Memory is needed and the single memory chip is availablein 2GB then 2 Memory chips are needed.

To build a memory that is wider than the one that can bought on asingle chip.

e.g. A 32-bit-wide memory chip cannot be bought generally, a memoryof a given width can easily be constructed (32 bits, 64 bits, etc.) byplacing RAMs in parallel.

Also LOGIC may be needed to turn the Bus Signals into the appropriatememory signals. So appropriate refresh signals need to begenerated.

e.g. Most busses won’t send address signals in row and column form.


Device Interfacing: Some I/O devices are designedto interface directly to a particular bus, formingglue-less interfaces.

But glue logic is required when a device isconnected to a bus for which it is not designed.

An I/O device typically requires a much smallerrange of addresses than a memory, soaddresses must be decoded much moreaccurately.

Some additional logic is required to cause the busto read and write the device’s registers.


COMPONENT INTERFACING cont’d….

The device has four registers that can be read andwritten by presenting the register number onthe regid pins, asserting R/W as required, andreading or writing the value on the regval pins.

To interface to the bus, the bottom two bits of theaddress are used to refer to registers within thedevice, and the remaining bits are used toidentify the device itself.

The top bits of the address are sent to a comparatorfor testing against the device address.

The device’s address can be set with switches toallow the address to be easily changed.

When the bus address matches the device’s, theresult is used to enable a transceiver for thedata pins.

When the transceiver is disabled, the regval pinsare disconnected from the data bus.

The comparator’s output is also used to modify theR/W signal: The device’s R/W pin is given thevalue (bus R/W + not-equal address), so thatwhen the comparator’s result is not 1, thedevice’s R/W pin always receives a 1 to avoidinadvertently writing the device registers.

A glue logic interface: Belowis an interfacing schemefor a simple I/O device


COMPONENT INTERFACING cont’d….

System Architecture: An Architecture is a set of elements and therelationships between them that together form a single unit.

The architecture of an embedded computing system is the blueprint forimplementing that system it gives an information about the componentsneeded and how they are put together. It includes both hardware andsoftware elements.

It includes several elements, some of which may be less obvious than others.■ CPU An embedded computing system clearly contains a

microprocessor.There are many different architectures, and even within anarchitecture there are models that vary in clock speed, bus datawidth, integrated peripherals, and so on.The choice of the CPU is one of the most important, also thesoftware that will execute on the machine.

■ Bus The choice of a bus is closely tied to that of a CPU, since the bus isan integral part of the microprocessor.But in applications that make intensive use of the bus due to I/O orother data traffic, the bus may be more of a limiting factor than theCPU.


DESIGNING WITH MICROPROCESSORS

System Architecture cont’d….■ Memory The most obvious characteristic of the memory is its total size,

which depends on both the required data volume and the size of theprogram instructions.

The ratio of ROM to RAM and selection of DRAM versus SRAM can have asignificant influence on the cost of the system.

The speed of the memory plays a great role in determining systemperformance.

■ Input and Output devices: For a given function, there may be severaldifferent devices of varying sophistication and cost that can do the job forthe CPU.

These devices are called the I/O devices based on fact whether suchdevice is being used for input or output operation.

e.g. A set of switches and knobs on a front panel may all be controlled by asingle microcontroller, which is in turn connected to the main CPU.

The difficulty of using a particular device, such as the amount of glue logicrequired to interface it, may also play a role in final device selection.


Hardware DesignStep – 1: Consider evaluation boards supplied by the microprocessor manufacturer or another company working in

collaboration with the manufacturer.

Evaluation boards are sold for many microprocessor systems; they typically include the CPU, some memory, a serial linkfor downloading programs, and some minimal number of I/O devices.

Figure below shows an ARM evaluation board manufactured by Sharp. The evaluation board may be a Complete Solutionor provide what is needed with only slight modifications. If the evaluation board is supplied by the microprocessorvendor, its design may be available from the vendor;

If the evaluation board comes from a third party, it may be possible to contract them to design a new board with therequired modifications, or start from scratch on a new board design.


Step-II: The other major task is the choice of memory andperipheral components.

In the case of I/O devices, there are two alternatives for eachdevice: selecting a component from a catalog or designingfrom scratch.

When shopping for devices from a catalog, it is important toread data sheets carefully; it may not be trivial to figure outwhether the device does what it is intended for.

Also due consideration must be given to the amount of gluelogic required to connect the device to the bus.

Simple peripheral logic can be implemented inProgrammable Logic Devices (PLDs), while more complexunits can be built from Field-programmable Gate Arrays(FPGAs).


Hardware Design cont’d….

The PC as a PlatformPersonal computers are often used as platforms

for embedded computing.

Advantages of a PC: it is a predesigned hardwareplatform with a great many features, a widevariety of I/O devices can be attached to it,and it provides a rich programmingenvironment.

Disadvantage: PC is larger, more power hungry,and more expensive than a custom hardwareplatform would be.

However, for low-volume applications andenvironments such as factories and officeswhere size and power are not critical, using aPC to build an embedded system oftenmakes a lot of sense.

As shown in adjacent Figure, a typical PC includesseveral major hardware components:

■ The CPU provides basic computationalfacilities.

■ RAM is used for program storage.

■ ROM holds the boot program.

■ A DMA controller provides DMAcapabilities.

■ Timers are used by the operating system fora variety of purposes.

■ A High-speed Bus, connected to the CPUbus through a bridge, allows fast devicesto communicate efficiently with the restof the system.

■ A Low-speed Bus provides an inexpensiveway to connect simpler devices and maybe necessary for backward compatibilityas well.


Hardware architecture of a typical PC

PCI (Peripheral Component Interconnect)PCI is the High-performance system bus which uses High-speed data

transmission techniques and efficient protocols to achieve high throughput.

The original PCI standard allowed operation up to 33 MHz; at that rate, amaximum transfer rate of 264 MB/s can be achieved using 64-bit transfers.

The revised PCI standard allows the bus to run up to 66 MHz, giving a maximumtransfer rate of 524 MB/s with 64-bit wide transfers.

PCI uses wide buses with many data and address bits along with multiplecontrol bits. The width of the PCI bus increases both the cost of an interfaceto the bus and makes the physical connection to the bus more complicated.

PCI also allows devices to be chained together so that users need not worryabout the order of devices on the bus or other details of connection.

USB (Universal Serial Bus) and IEEE 1394 are the two major high-speed serialbuses. Both of these buses offer high transfer rates using simple connectors.


Basic Input / Output System (BIOS)A PC provides a standard software platform that interfaces to the

underlying hardware as well as more advanced services.

At the bottom of the software platform structure in most PCs is aminimal set of software in ROM.

This software is designed to load the complete operating systemfrom some other device (disk, network, etc.), and it may alsoprovide low-level hardware interfaces.

In the IBM-compatible PC, the low-level software is known as theBasic Input / Output System (BIOS).

The BIOS provides low-level hardware drivers as well as bootingfacilities.

The operating system provides high-level drivers, control ofexecuting processes, user interfaces, and so on.


System organization of the Intel StrongARM SA-1100 and SA-1111

The StrongARM SA-1100 provides a number of functions besides the ARM CPU.

The chip contains two on-chip buses: a high-speed system bus and a lower-speed peripheral bus.

The chip also uses two different clocks. A 3.686 MHz clock is used to drive the CPU and high-speedperipherals, and a 32.768 kHz clock is an input to the system control module.

The system control module contains the following peripheral devices:

■ A real-time clock

■ An operating system timer

■ 28 general-purpose I/Os (GPIOs)

■ An interrupt controller

■ A power manager controller

■ A reset controller that handles resetting the processor.

The 32.768 kHz clock’s frequency is chosen to

be useful in timing real-time events.

The slower clock is also used by the power

manager to provide continued operation of

the manager at a lower clock rate and

therefore lower power consumption.


DEVELOPMENT AND DEBUGGINGDevelopment Environments: A typical embedded computing system has a relatively small amount of

everything, including CPU horsepower, memory, I/O devices, and so forth.

As a result, it is common to do at least part of the software development on a PC or workstation known asa host as illustrated in Figure below.

The hardware on which the code will finally run is known as the Target.

The host and target are frequently connected by a USB link, but a higher-speed link such as Ethernet canalso be used.

The target must include a small amount of software to talk to the host system.

That software will take up some memory, interrupt vectors, and so on, but it should generally leave thesmallest possible footprint in the target to avoid interfering with the application software.

The host should be able to do the following:

■ load programs into the target,

■ start and stop program execution on the target, and

■ examine memory and CPU registers.


Connecting a host and a target system

A Cross-compiler is a compiler that runs on one type of machine butgenerates code for another.After compilation, the executable code is downloaded to the embeddedsystem by a serial link or perhaps burned in a PROM and plugged in.

Host-target debuggers are often used, in which the basic hooks for debuggingare provided by the target and a more sophisticated user interface iscreated by the host.

A PC or workstation offers a programming environment which is muchfriendlier than the typical embedded computing platform.

Problem with this approach emerges when debugging code talks to I/Odevices, as the host will not have the same devices configured in the sameway, the embedded code cannot be run as is done on the host.

A Test-bench program can be built to help debug the embedded code.The Test-bench generates inputs to simulate the actions of the input devices;

it may also take the output values and compare them against expectedvalues, providing valuable early debugging help.

The embedded code may need to be slightly modified to work with theTestbench, but careful coding (such as using the #ifdef directive in C) canensure that the changes can be undone easily and without introducingbugs.


DEVELOPMENT AND DEBUGGING cont’d….

Debugging Techniques (S/W based)A Software Debugging can be done by Compiling and Executing

the code on a PC or workstation.

But at some point it inevitably becomes necessary to run code onthe embedded hardware platform.

Embedded systems are usually less friendly programmingenvironments than PCs but, the resourceful designer hasseveral options available for debugging the system.

The serial port found on most evaluation boards is one of themost important debugging tools.

It is a good idea to design a serial port into an embedded systemeven if it is not likely to be used in the final product; the serialport can be used not only for development debugging but alsofor diagnosing problems in the field.


Another very important debugging tool is theBreakpoint.

The simplest form of a Breakpoint is for the user tospecify an address at which the program’s executionis to break.

When the PC reaches that address, control is returnedto the monitor program.

From the monitor program, the user can examineand/or modify CPU registers, after which executioncan be continued.

Implementing breakpoints does not require usingexceptions or external devices.


Debugging Techniques (S/W based) cont’d….

Following Programming Example shows how to use instructions to createbreakpoints.

Breakpoints: A breakpoint is a location in memory at which a program stopsexecuting and returns to the debugging tool or monitor program.

Implementing breakpoints is very simple, it only requires replacement of theinstruction at the breakpoint location with a subroutine call to the monitor.

In the following code, to establish a breakpoint at location 0x40c in some ARM code,the branch (B) instruction is replaced and is normally held at that location with asubroutine call (BL) to the breakpoint handling routine:

When the breakpoint handler is called, it saves all the registers and can then displaythe CPU state to the user and take commands.

To continue execution, the original instruction must be replaced in the program.

If the breakpoint can be erased, the original instruction can simply be replaced andcontrol returned to that instruction.

This will normally require fixing the subroutine return address, which will point to theinstruction after the breakpoint.


Debugging Techniques (S/W based) cont’d….

When Software Tools are insufficient to debug the system, Hardwareaids can be deployed to give a clearer view of what is happeningwhen the system is running.

The microprocessor In Circuit Emulator (ICE) is a specialized hardwaretool that can help debug software in a working embedded system.

An ICE is a special version of the microprocessor that allows its internalregisters to be read out when it is stopped.

The In-circuit Emulator surrounds this specialized microprocessor withadditional logic that allows the user to specify breakpoints andexamine and modify the CPU state.

The CPU provides as much debugging functionality as a debuggerwithin a monitor program, but does not take up any memory.

Drawback of In-circuit Emulation: The machine is specific to aparticular microprocessor, even down to the pinout.

If several microprocessors are used, maintaining a fleet of In-circuitEmulators to match can be very expensive.


Debugging Techniques (H/W based) cont’d….

The Logic Analyzer is the other major piece of instrumentation in theembedded system designer’s arsenal.

Think of a logic analyzer as an array of inexpensive oscilloscopes; theanalyzer can sample many different signals simultaneously (tens tohundreds) but can display only 0, 1, or changing values for each.

All these logic analysis channels can be connected to the system torecord the activity on many signals simultaneously.

The logic analyzer records the values on the signals into an internalmemory and then displays the results on a display once the memoryis full or the run is aborted.

The logic analyzer can capture thousands or even millions of samplesof data on all of these channels, providing a much larger timewindow into the operation of the machine than is possible with aconventional oscilloscope.



A typical Logic Analyzer can acquire data in either of two modes that aretypically called State and Timing modes.

The measurement resolution on each signal is reduced in both voltage andtime dimensions.

The reduced voltage resolution is accomplished by measuring logic values (0,1, x) rather than analog voltages.

The reduction in Timing resolution is accomplished by sampling the signal,rather than capturing a continuous waveform as in an analog oscilloscope.

State and timing mode represent different ways of sampling the values.Timing mode uses an Internal Clock that is fast enough to take several

samples per clock period in a typical system.State mode, uses the System’s own Clock to control sampling, so it samples

each signal only once per clock cycle.As a result, timing mode requires more memory to store a given number of

system clock cycles.On the other hand, it provides greater resolution in the signal for detecting

glitches.Timing mode is typically used for glitch-oriented debugging, while state mode

is used for sequentially oriented problems.



The Internal Architecture of a logic analyzer is shown in Figure below.

The system’s data signals are sampled at a latch within the logic analyzer; the latch is controlled by either thesystem clock or the internal logic analyzer sampling clock, depending on whether the analyzer is being usedin state or timing mode.

Each sample is copied into a vector memory under the control of a state machine.

The latch, timing circuitry, sample memory, and controller must be designed to run at high speed since severalsamples per system clock cycle may be required in timing mode.

After the sampling is complete, an embedded microprocessor takes over to control the display of the datacaptured in the sample memory.

Logic analyzers typically provide a number of formats for viewing data. One format is a timing diagram format.

Many logic analyzers allow not only customized displays, such as giving names to signals, but also more advanceddisplay options.

For example, an inverse assembler can be used to turn vector values into microprocessor instructions.

The logic analyzer does not provide access to

the internal state of the components, but it

does give a very good view of the externally

visible signals.

That information can be used for both

Functional and timing debugging.


Architecture of a Logic Analyzer


Debugging ChallengesLogical errors in software can be hard to track down, but errors in real-time code can

create problems that are even harder to diagnose.

Real-time programs are required to finish their work within a certain amount of time;if they run too long, they can create very unexpected behavior.

Example below demonstrates one of the problems that can arise.

A timing error in real-time code: To make it easier to compare input to output andsee the results of the bug, assuming that the computation produces an outputequal to the input, but that a bug causes the computation to run 50% longer thanits given time interval.

A sample input to the program over several sample periods follows:


If the program ran fast enough to meet its deadline, the output would simply be a timeshifted copy of the input.

But when the program runs over its allotted time, the output will become very different.

The behavior of the A/D and D/A converters is unpredictable make some assumptions like.

First, the A/D converter holds its current sample in a register until the next sample period,and the D/A converter changes its output whenever it receives a new sample.

Next, a reasonable assumption about interrupt systems is that, when an interrupt is notsatisfied and the device interrupts again, the device’s old value will disappear and bereplaced by the new value.

The basic situation that develops when the interrupt routine runs too long is somethinglike this:

1. The A/D converter is prompted by the timer to generate a new value, saves it inthe register, and requests an interrupt.

2. The interrupt handler runs too long from the last sample.

3. The A/D converter gets another sample at the next period.

4. The interrupt handler finishes its first request and then immediately responds tothe second interrupt. It never sees the first sample and only gets the second one.


Debugging Challenges cont’d….

Thus, assuming that the Interrupt Handler takes 1.5 times longer than it should, here ishow it would process the sample input:

• Input sample

Output sample

The output waveform is seriously distorted because the interrupt routine grabs the wrongsamples and puts the results out at the wrong times.

The exact results of missing real-time deadlines depend on the detailed characteristics ofthe I/O devices and the nature of the timing violation.

This makes debugging real-time problems especially difficult and if a system exhibits trulyunusual behavior, missed deadlines should be suspected.

In-circuit emulators, logic analyzers, and even LEDs can be useful tools in checking theexecution time of real-time code to determine whether it in fact meets its deadline.


Debugging Challenges cont’d….

SYSTEM-LEVEL PERFORMANCE ANALYSISSYSTEM-LEVEL PERFORMANCE involves much more than the CPU.

Though focus is on often the CPU because it processes instructions, but any part of the systemcan affect total system performance.

More precisely, the CPU provides an upper bound on performance, but any other part of thesystem can slow down the CPU. Merely counting instruction execution times is notenough.

Consider the simple system of Figure below. Data needs to be moved from memory to the CPUto process it.

To get the data from memory to the CPU following must be done:

■ read from the memory;

■ transfer over the bus to the cache; and

■ transfer from the cache to the CPU.


System level Data Flows and Performance

The time required to transfer from the cache to the CPU is included in theinstruction execution time, but the other two times are not.

The most basic measure of performance is Bandwidth— the rate at which thedata can be moved.

The point of interest is real-time performance measured in seconds.

But often the simplest way to measure performance is in units of clock cycles.

However, different parts of the system will run at different clock rates.

So, it has to be ensured that the right clock rate is applied to each part of theperformance estimate while converting clock cycles to seconds.

For simplicity, consider the bandwidth provided by only one systemcomponent, the bus.

Consider an image of 320240 pixels, with each pixel composed of 3 bytes ofdata. This gives a grand total of 230, 400 bytes of data.

If these images are video frames, then it is to be checked if one frame can bepushed through the system within the 1/30s that a frame has to beprocessed before the next one arrives.


SYSTEM-LEVEL PERFORMANCE ANALYSIS cont’d….

Let the bus clock period be P and the bus width be W.

Putting W in units of bytes (other measures of width could be used as well).

Then to write formulas for the time required to transfer N bytes of data.

We will write our basic formulas in units of bus cycles T , then convert those bus cyclecounts to real time t using the bus clock period P:

t = TP. (4.1)

As shown in Figure below, a basic bus transfer transfers a W-wide set of bytes.

The data transfer itself takes D clock cycles. (Ideally, D = 1, but a memory thatintroduces wait states is one example of a transfer that could require D > 1cycles.)



Times and data volumes in a basic bus transfer

Addresses, handshaking, and other activities constitute overhead that may occur

before (O1) or after (O2) the data.

For simplicity, let the overhead be summed into O = O1 + O2.

This gives a total transfer time in clock cycles of:

Tbasic(N) = (D + O) . N/W ………………………………. (4.2)

As shown in Figure below, a burst transaction performs B transfers of W bytes each.

Each of those transfers will require D clock cycles. The bus also introduces O cycles ofoverhead per burst. This gives

Tburst(N) = (B.D + O). N / (BW) ……………………………... (4.3)

Transferring data into and out of components also raises questions of bandwidth. Thesimplest illustration of this problem is memory.



Times and data volumes in a burst bus transfer

A single memory chip is not solely specified by the number of bits it can hold.

As shown in Figure below, memories of the same size can have different Aspect Ratios.

e.g: A 64-MB memory that is 1-bit-wide will present 64 million addresses of 1-bit data. The same sizememory in a 4-bit-wide format will have 16 distinct addresses and an 8-bit-wide memory will have 8million distinct addresses.

Memory chips do not come in extremely wide aspect ratios but wider memories can be built by usingseveral chips.

The memory system width may also be determined by the memory modules used. Rather than buy memorychips individually, memory as SIMMs or DIMMs may be bought.

Which aspect ratio is preferable for the overall memory system depends also on the format of the dataneeds to be stored in the memory and the speed with which it must be accessed, giving rise tobandwidth analysis.



if the data types do not fit naturally into the width of the memory.

Let color video pixels need to be stored in the memory.

A standard pixel is 38-bit color values (say red, green, blue).

A 24-bit-wide memory would allow to read or write an entire pixel value inone access.

An 8-bit-wide memory, in contrast, would require three accesses for the pixel.

If a 32-bit-wide memory is there then there are 2 main choices:

1. One byte of each transfer could be wasted or

2. Use that byte to store unrelated data, or the pixels can be packed.

In the 2nd case, the first read would get all of the first pixel and one byte ofthe second pixel; the second transfer would get the last two bytes of thesecond pixel and the first two bytes of the third pixel; and so forth.

The total number of accesses A required to read E data elements of w bitseach out of a memory of width W is:

A = [(E/w) mod W] + 1 …………………………………. (4.4)



Performance bottlenecks in a bus-based systemConsider a simple bus-based system: data has to be transferred

between the CPU and the memory over the bus.

We need to be able to read a 320 X 240 video frame into the CPU atthe rate of 30 frames/s, for a total of 612,000 bytes/s.

Which will be the bottleneck and limit system performance: the bus orthe memory?

Let’s assume that the bus has a 1-MHz clock rate (period of 10-6 sec)and is 2 bytes wide, with D = 1 and O = 3.

This gives a total transfer time of

Tbasic = (1 + 3).612,000/2 = 1,224,000 cycles ……………….(4.5)


t = Tbasic · P = 1,224,000 · 1 x 10-6 = 1.224 sec ………………………………(4.6)

Since the total time to transfer one second’s worth of frames is morethan 1s, the bus is not fast enough for our application.

The memory provides a burst mode with B = 4 but is only 4 bits wide,giving W = 0.5.

For this memory, D = 1 and O = 4. The clock period for this memory is107 s. Then

Tmem = (4 · 1 + 4).612,000/(4 x 0.5) = 2,448,000 cycles ……… (4.7)

t = Tmem · P = 2,448,000 · 1 x 10-7 = 0.2448 sec ………………..(4.8)

The memory requires < 1s to transfer the 30 frames that must betransmitted in 1s, so it is fast enough.


Performance bottlenecks in a bus-based system

ParallelismWhen different components of the

system operate in parallel, morework can be done in a givenamount of time.

Direct Memory Access is a primeexample of parallelism, DMA wasdesigned to off-load memorytransfers from the CPU.

The CPU can do other useful workwhile the DMA transfer is running.Figure below shows the paths ofdata transfers without and withDMA when transferring frommemory to a device.

Without DMA, the data must gothrough the CPU; the CPU cannotdo useful work at that time.


DMA transfers and parallelism

The CPU is tied up for the amount of time required for thebus transfer.

Since buses often operate at slower clock rates than theCPU, that time can be considerable.

The system performance can be increased significantly byoverlapping operations on the different units of thesystem.

The timing diagrams of adjacent Figure shows timingdiagram for two versions of a computation.

The top timing diagram shows activity in the system whenthe CPU first performs some setup operations, thenwaits for the bus transfer to complete, then resumesits work.

In the bottom timing diagram, the program on the CPU hasbeen rewritten so that its main work is broken intotwo sections.

In this case, once the first transfer is done, the CPU canstart working on that data.

Meanwhile, due to DMA, the second transfer happens onthe bus at the same time.

Once that data arrives and the first calculation is finished,the CPU can go on to the second part of thecomputation.

The result is that the entire computation finishesconsiderably earlier than in the sequential case.


Sequential and parallel schedules in a bus-based system

Parallelism cont’d….

Design Example : ALARM CLOCKRequirements: the adjacent Figure

illustrates the front panel design forthe alarm clock.

The time is shown as four digits in 12-hformat; a light has been used todistinguish between AM and PM.

Several buttons are used to set the clocktime and alarm time.

When the hour and minute buttons arepressed, the hour and minute isadvanced, respectively, by one.

When setting the time, the set timebutton must be held down while thehour and minute buttons are hit; theset alarm button works in a similarfashion.

With the alarm on and alarm off buttons,the alarm is turned on and off.

When the alarm is activated, the alarmready light is on. A separate speakerprovides the audible alarm.


Front panel of the alarm clock

The Requirements Table:


Design Example : ALARM CLOCK cont’d….

The adjacent Figure 1 shows the basic classes for thealarm clock.

Calling the class that handles the basic clock operationthe Mechanism class (based on a term frommechanical watches).

Three classes are there representing physical elements:Lights* for all the digits and lights,

Buttons* for all the buttons, and

Speaker* for the sound output.

The Buttons* class can easily be used directly byMechanism.

The physical display must be scanned to generate thedigits output, so the Display class is introduced toabstract the physical lights.

The details of the low-level user interface classes areshown in Figure 2.

The Buzzer* class allows the buzzer to be turned off;analog electronics will be used to generate the buzztone for the speaker.

The Buttons* class provides read-only access to thecurrent state of the buttons.

The Lights* class allows to drive the lights.

For saving the pins on the display, Lights* provides signalsfor only one Digit, along with a set of signals toindicate which digit is currently being addressed.

Class diagram for the alarm clock


Details of low-level class for the alarm clock

Design Example : ALARM CLOCK cont’d….

Figure 2

Figure 1

SpecificationThe display is generated by scanning the digits periodically, this function is performed by the Display

class, which makes the display appear as an un-scanned, continuous display to the rest of thesystem.

The Mechanism class is described in Figure below.

This class keeps track of the current time, the current alarm time, whether the alarm has beenturned on, and whether it is currently buzzing.

The clock shows the time only to the minute, but it keeps internal time to the second.

The time is kept as discrete digits rather than a single integer to simplify transferring the time to thedisplay.

The class provides two behaviors, both of which run continuously.

I. Scan-keyboard is responsible for looking at the inputs and updating the alarm and otherfunctions as requested by the user.

II. Update-time keeps the current time

accurate.


The Mechanism Class

Adjacent Figure shows the statediagram for update-time.

This behavior is straightforward,but it must do several things.

It is activated once per second andmust update the seconds clock.

If it has counted 60 s, it must thenupdate the displayed time;when it does so, it must rollover between digits and keeptrack of AM-to-PM and PM-to-AM transitions.

It sends the updated time to thedisplay object.

It also compares the time with thealarm setting and sets thealarm buzzing under properconditions.


Specification cont’d….

State diagram for update-time

The state diagram for scan-keyboard is shown inadjacent Figure .

This function is called periodically, frequently enoughso that all the user’s button presses are caught bythe system.

Because the keyboard will be scanned several timesper second and the same button press need notbe registered several times.

e.g.: the minutes count is advanced on everykeyboard scan when the set-time and minutesbuttons were pressed, the time would beadvanced much too fast.

To make the buttons respond more reasonably, thefunction computes button activations; itcompares the current state of the button to thebutton’s value on the last scan, and it considersthe button activated only when it is on for thisscan but was off for the last scan.

Once computing the activation values for all thebuttons, it looks at the activation combinationsand takes the appropriate actions.

Before exiting, it saves the current button values forcomputing activations the next time this behavioris executed.


State diagram for scan-keyboard

Specification cont’d….

The system has both Periodic and Aperiodic components; the current time mustobviously be updated periodically, and the button commands occuroccasionally.

The following 2 major software components can be present in the Architecture:

■ An Interrupt-driven Routine can update the current time.

The current time will be kept in a variable in memory.

A timer can be used to interrupt periodically and update the time.

The display must be sent the new value when the minute value changes.

This routine can also maintain the PM indicator.

■ A Foreground Program can poll the buttons and execute their commands.

Since buttons are changed at a relatively slow rate, it makes no sense toadd the hardware required to connect the buttons to interrupts.

Instead, the foreground program reads the button values and then usesimple conditional tests to implement the commands, including settingthe current time, setting the alarm, and turning off the alarm.

Another routine called by the foreground program will turn the buzzer onand off based on the alarm time.


System Architecture

The Foreground Code will be implemented as a while loop:

while (TRUE) {

read_buttons(button_values);/* read inputs */

process_command(button_values);/* do commands */

check_alarm();/* decide whether to turn on the alarm */

}

The loop first reads the buttons using read_buttons().

In addition to reading the current button values from the input device, this routine must preprocess thebutton values so that the user interface code will respond properly.

As shown in Figure below, this can be done by performing a simple edge detection on the button input, thebutton event value is 1 for one sample period when the button is depressed and then goes back to 0and does not return to 1 until the button is depressed and then released.

This can be accomplished by a simple

two-state machine.


System Architecture cont’d….

Preprocessing button inputs

The process_command() function is responsible for responding tobutton events.

The function checks the current time against the alarm time anddecides when to turn on the buzzer.

This check_alarm() routine is kept separate from the CommandProcessing Code since the alarm must go on when the proper timeis reached, independent of the button inputs.

From the software architecture it can be seen that a timer needs to beconnected to the CPU. Also a logic to connect the buttons to theCPU bus will be needed.

Finally, before starting to write code and build hardware, draw theState Transition Graph for the clock’s commands.

That diagram will be used to guide the implementation of the softwarecomponents.


System Architecture cont’d….

Component Design and TestingThe 2 major software components, the Interrupt Handler and the Foreground

Code, can be implemented relatively straightforwardly.

As the functionality of the Interrupt Handler is in the interruption processitself, that code is best tested on the Microprocessor Platform.

The Foreground Code can be more easily tested on the PC or workstationused for code development.

A testbench can be created for this code which generates button depressionsto exercise the state machine.

the advancement of the system clock also needs to be simulated.

A better testing strategy for Interrupt Handler is to add testing code thatupdates the clock, perhaps once per four iterations of the foregroundwhile loop.

The Timer taken care this way, the focus can thus be on implementing logic tointerface to the buttons, display, and buzzer.

The buttons will require debouncing logic.

The display will require a register to hold the current display value in order todrive the display elements.


System Integration and TestingBecause this system has a small number of

components, system integration is relatively easy.

The software must be checked to ensure thatdebugging code has been turned off.

Three types of Tests can be performed.

1. The clock’s accuracy can be checked against areference clock.

2. The commands can be exercised from thebuttons.

3. The buzzer’s functionality should be verified.


THANK YOU


ecs 7th sem-cse-unit-3

Devices & Hardware