ecfa ilc workshop, november 2005, viennaladislav andricek, mpi für physik, hll depfet project...
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ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
DEPFET Project Status - in SummaryDEPFET Project Status - in Summary
Technology development
thinning technology steering chips Switcher II
r/o chips Curo II tolerance against ion. radition
beam test
55Fe
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
DEPFET PrincipleDEPFET Principle
DrainSource
Gate
fully depleted sensitive volume
internal amplification
no interconnection strays
charge collection in "Off" state, readout on
demand
J. Kemmer & G. Lutz, 1987
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
DEPFET PrincipleDEPFET Principle
fully depleted sensitive volume
internal amplification
no interconnection strays
charge collection in "Off" state, readout on
demand
J. Kemmer & G. Lutz, 1987
gq
(pA
/e- )
measuredvalue
Simulation
)(2 thGSpD
q VVLdQ
dIg
internal amplification
effective channel length L (m)
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Matrix operationMatrix operation
n x mpixel
IDRAIN
DEPFET- matrix
VGATE, OFF
off
off
on
off
VGATE, ON
gate
drain VCLEAR, OFF
off
off
reset
off
VCLEAR, ON
reset
output
0 suppression
VCLEAR-Control
Only selected rows dissipate powerbut
Sensor still sensitive even with the DEPFET in OFF state
Reset row i
Gate row i
sample Iped+Isig sample Iped
TROW ≈ 50ns
Row wise read outand
row wise CDS!
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Compact linear DEPFETs Compact linear DEPFETs
Double pixel cells: reduces the required read out speed by 2 doubles the number of read out channels
smallest pixel cell 22.5 x 36 μm2
limited by technology: smallest feature size ≈2μm
Gates
Common Sources
Clears
D1
D2
double poly-silicon/double metal Technology
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Module Concept: "all-silicon module"Module Concept: "all-silicon module"
Thinned sensor (50 µm) in active area
Chips are thinned to 50 μm, connection via bump bonding
Cavities in frame can save material
Thick support frame (~300 µm)
Material budget (1st layer, incl. steering chips and frame) ≈ 0.11 %X0
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Top Wafer
Handle <100> Wafer
a) oxidation and back side implant of top wafer
b) wafer bonding and grinding/polishing of top wafer
c) process passivation
open backside passivation
d) anisotropic deep etching opens "windows" in handle wafer
Processing thin detectorsProcessing thin detectors
50 μm, 4 diodes, 10 mm2
revers
e c
urr
en
t (p
A)
700..850 pA/cm2
Al
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Irradiation IssuesIrradiation Issues
D1
D2
SG1
G2Cl Cl
Double pixel DEPFETs like in the main matrix from the latest production
(Gate dielectrics: more than 200 nm)
Radiation Effects (ionizing radiation)
1. postive oxide charge and postively charged oxide traps have to be compensated by a more negative gate voltage: negative shift of the theshold voltage (~tox
2)
2. increased density of interface traps: higher 1/f noise and reduced mobility (gm)
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Threshold voltage shiftThreshold voltage shift
GSF – National Research Center for Environment and Health, Munich60Co (1.17 MeV and 1.33 MeV)
No annealing during irradiation ~ 3 days irradiation
Dose rate: ≈ 20 krad(SiO2)/h
-∆V
th (V
)
∆N
ot
(10
11cm
-2)
"OFF"
"ON"
Dose (krad)
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Transconductance and subtreshold slopeTransconductance and subtreshold slope
s=85mV/dec
s=155mV/dec
Vth=-0.2V
Vth=-4.5V
12)10ln( DDox
it sskTCN
Literature: After 1Mrad 200 nm (SiO2):
Nit ≈ 1013 cm-2
300 krad Nit≈2·1011 cm-2
912 krad Nit≈7·1011 cm-2
No change in the transconductance gm
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Performance Performance beforebefore irradiation irradiation
55Fe
Energy (eV)
Counts
/ch
annel
o non-irrad. double pixel DEPFETo L=7μm, W=25 μm
o Vthresh≈-0.2V, Vgate=-1V
o Idrain=41 μA
o Drain current read out
o time cont. shaping =6 μs
Noise ENC=2.3 e- (rms)
at T>23 degC
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Performance Performance afterafter irradiation irradiation
55Fe
Energy (eV)
Counts
/ch
annel
o Irradiated double pixel DEPFETo L=7μm, W=25 μmo after 913 krad, 60Co
o Vthresh≈-4V, Vgate=-5.3V
o Idrain=21 μA
o Drain current read out
o time cont. shaping =6 μs
Noise ENC=7.9 e- (rms)
at T>23 degC
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Clear Gate after irradiation (Clear Gate after irradiation (6060Co)Co)
G1
G2
S
D1
D2
Clear Gate
ClCl
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
What's next in 2006??What's next in 2006??
1. New production PXD5-: bigger matrices
-: better gq
-: further improvement of clearing
2. Transfer thinning technology to production line-: qualify industrial partner for wafer bonding
and top wafer thinning (engineered SOI Wafer)-: 150mm wafer-: produce diodes and mechanical samples as far
as possible on main processing line
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
New ILC DEPFET productionNew ILC DEPFET production
Main Device-: 512 x 512 pixels-: read out in both sides-: 24μm x 33μm pixel size-: array area: 17mm x 12.3mm
-: chip area: ~ 21mm x 18mm
max. ILC width (outer layers)-: Array 2,2cm x 0,62cm
max. ILC length (layer 1)-: Array 0,5cm x 5cm
+ 128x128 "working horse" arrays + 128x64 design studies + single pixel, mini matrices,
teststructures
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
Thin test diodes, 150mm WaferThin test diodes, 150mm Wafer
Top Wafer
Handle <100> Wafer
a) oxidation and back side implant of top wafer
b) wafer bonding and grinding/polishing of top wafer
c) process passivation
open backside passivation
d) anisotropic deep etching opens "windows" in handle wafer
SOI Wafers ready!
Material (Top and Handle): 150mm, FZ, 100 Ohm.cm
Oxidation 230 nmFull sheet P-implant back side top wafer
At TraciT, Grenoble:
Wafer Bonding Annealing 1050 degC, 4h
Grinding, CMP: 50 μm top wafer Edge treatment, polishing Top and Handle wafer
Yield:No voids: 9 Wafer
1 void (<5mm): 7 WaferMore than one void: 4 Wafer
Continue processing at HLL (finished by end of 2005)
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
In Summary.... In Summary....
So far:
Double Metal/Double Poly Technology established Present Pixel size: 22x36 μm2 – can go to ~ 20x20 µm2, limited only by manufacturing
equipment Compact Linear DEPFETs show the expected excellent noise performance Technology for thin (≤ 50μm) detectors established (total budget 0.11% X0 per layer) Radiation tolerance against ionizing radiation demonstrated up to 1Mrad
Advantages DEPFET:
Charge generation and first amplification in a fully depleted pixel cell good Signal/Noise
No charge transfer needed: better rad. tolerance against hadronic irradiation
Wafer scale arrays (6") possible: easier module construction, less material
Charge collection in "OFF"-state, only one row active during readout: low power consumption, less material for cooling
Production technology completely under control of detector designers and physicists
We are ready to go for the next round!
ECFA ILC Workshop, November 2005, Vienna Ladislav Andricek, MPI für Physik, HLL
WorkshopWorkshop
A Vertex Detector for the ILC- Physics and Technologies -
May 28, 2006 - May 31, 2006http://www.hll.mpg.de/~lca/ringberg