ece554 computer architecture - softnology.bizsoftnology.biz/pdf/lecture05-dram.pdf · page 1 ece...
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ECE 554 Computer Architecture
Lecture 5
Main Memory
Spring 2013
Sudeep Pasricha Department of Electrical and Computer Engineering
Colorado State University
© Pasricha; portions: Kubiatowicz, Patterson, Mutlu, Binkert, Elsevier
1
Main Memory Background
• Performance of Main Memory: – Latency: Cache Miss Penalty
» Access Time: time between request and word arrives
» Cycle Time: time between requests
– Bandwidth: I/O & Large Block Miss Penalty (L2)
• Main Memory is DRAM: Dynamic Random Access Memory – Dynamic since needs to be refreshed periodically (8 ms, 1% time)
– Addresses divided into 2 halves (Memory as a 2D matrix):
» RAS or Row Address Strobe
» CAS or Column Address Strobe
• Cache uses SRAM: Static Random Access Memory – No refresh (6 transistors per bit vs. 1 transistor + 1 capacitor per bit)
Size: SRAM/DRAM 4-8, Cycle time: DRAM/SRAM 8-16
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Memory subsystem organization
• Memory subsystem organization
– Channel
– DIMM
– Rank
– Chip
– Bank
– Row/Column
Memory subsystem
Memory channel
Memory channel
DIMM (Dual in-line memory module)
Processor
“Channel”
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Breaking down a DIMM
DIMM (Dual in-line memory module)
Side view
Front of DIMM Back of DIMM
Serial presence detect (SPD) - Stored in EEPROM on module
- has info to configure mem controllers
Breaking down a DIMM
DIMM (Dual in-line memory module)
Side view
Front of DIMM Back of DIMM
Rank 0: collection of 8 chips Rank 1
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Rank
Rank 0 (Front) Rank 1 (Back)
Data <0:63> CS <0:1> Addr/Cmd
<0:63> <0:63>
Memory channel
DIMM & Rank (from JEDEC)
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Breaking down a Rank
Rank 0
<0:63>
Ch
ip 0
Ch
ip 1
Ch
ip 7
. . .
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
Breaking down a Chip
Ch
ip 0
<0
:7>
Bank 0
<0:7>
<0:7>
<0:7>
...
<0:7
>
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Breaking down a Bank
Bank 0
<0:7
>
row 0
row 16k-1 ...
2kB
1B
1B (column)
1B
Row-buffer
1B ...
<0:7
>
Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Channel 0
DIMM 0
Rank 0
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Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Rank 0 Chip 0 Chip 1 Chip 7
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
. . .
Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Rank 0 Chip 0 Chip 1 Chip 7
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
Row 0
Col 0
. . .
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Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Rank 0 Chip 0 Chip 1 Chip 7
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
8B
Row 0
Col 0
. . .
8B
Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Rank 0 Chip 0 Chip 1 Chip 7
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
8B
Row 0
Col 1
. . .
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Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Rank 0 Chip 0 Chip 1 Chip 7
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
8B
8B
Row 0
Col 1
. . .
8B
Example: Transferring a cache block
0xFFFF…F
0x00
0x40
...
64B
cache block
Physical memory space
Rank 0 Chip 0 Chip 1 Chip 7
<0:7
>
<8:1
5>
<56
:63
>
Data <0:63>
8B
8B
Row 0
Col 1
A 64B cache block takes 8 I/O cycles to transfer.
During the process, 8 columns are read sequentially.
. . .
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DRAM Overview
19
DRAM Architecture
Row
Addre
ss
Decoder
Col. 1
Col. 2M
Row 1
Row 2N
Column Decoder & Sense Amplifiers
M
N
N+M
bit lines word lines
Memory cell (one bit)
D Data
• Bits stored in 2-dimensional arrays on chip
• Modern chips have around 4 logical banks on each chip
– each logical bank physically implemented as many smaller arrays
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1-T Memory Cell (DRAM)
• Write: – 1. Drive bit line
– 2.. Select row
• Read: – 1. Precharge bit line to Vdd/2
– 2. Select row
– 3. Storage cell shares charge with bitlines
» Very small voltage changes on the bit line
– 4. Sense (fancy sense amp)
» Can detect changes of ~1 million electrons
– 5. Write: restore the value
• Refresh – 1. Just do a dummy read to every cell.
row select
bit
21
SRAM vs. DRAM
22
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DRAM Operation: Three Steps • Precharge
– charges bit lines to known value, required before next row access
• Row access (RAS) – decode row address, enable addressed row (often multiple Kb in row)
– Contents of storage cell share charge with bitlines
– small change in voltage detected by sense amplifiers which latch whole row of bits
– sense amplifiers drive bitlines full rail to recharge storage cells
• Column access (CAS) – decode column address to select small number of sense amplifier
latches (4, 8, 16, or 32 bits depending on DRAM package)
– on read, send latched bits out to chip pins
– on write, change sense amplifier latches. which then charge storage cells to required value
– can perform multiple column accesses on same row without another row access (burst mode)
23
DRAM: Memory-Access Protocol
24
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DRAM Bank Operation
Row Buffer
(Row 0, Column 0)
Ro
w d
ec
od
er
Column mux
Row address 0
Column address 0
Data
Row 0 Empty
(Row 0, Column 1)
Column address 1
(Row 0, Column 85)
Column address 85
(Row 1, Column 0)
HIT HIT
Row address 1
Row 1
Column address 0
CONFLICT !
Columns
Ro
ws
Access Address: Commands
ACTIVATE 0
READ 0
READ 1
READ 85
PRECHARGE
ACTIVATE 1
READ 0
DRAM: Basic Operation
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A D
OE_L
256K x 8
DRAM 9 8
WE_L CAS_L RAS_L
OE_L
A Row Address
WE_L
Junk
Read Access
Time
Output Enable
Delay
CAS_L
RAS_L
Col Address Row Address Junk Col Address
D High Z Data Out
DRAM Read Cycle Time
Early Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L
• Every DRAM access begins at:
– The assertion of the RAS_L
– 2 ways to read: early or late v. CAS
Junk Data Out High Z
DRAM Read Timing (Example)
27
DRAM: Burst
28
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DRAM: Banks
29
DRAM: Banks
30
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2Gb x8 DDR3 Chip [Micron]
31
Observe: bank organization
Quest for DRAM Performance
1. Fast Page mode – Add timing signals that allow repeated accesses to row buffer
without another row access time
– Such a buffer comes naturally, as each array will buffer 1024 to 2048 bits for each access
2. Synchronous DRAM (SDRAM) – Add a clock signal to DRAM interface, so that the repeated
transfers would not bear overhead to synchronize with DRAM controller
3. Double Data Rate (DDR SDRAM) – Transfer data on both the rising edge and falling edge of the
DRAM clock signal doubling the peak data rate
– DDR2 lowers power by dropping the voltage from 2.5 to 1.8 volts + offers higher clock rates: up to 400 MHz
– DDR3 drops to 1.5 volts + higher clock rates: up to 800 MHz
– DDR4 drops to 1-1.2 volts + higher clock rates: up to 1600 MHz
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1. Fast Page Mode Operation • Regular DRAM Organization:
– N rows x N column x M-bit
– Read & Write M-bit at a time
– Each M-bit access requires a RAS / CAS cycle
• Fast Page Mode DRAM – N x M “SRAM” to save a row
• After a row is read into the register
– Only CAS is needed to access other M-bit blocks on that row
– RAS_L remains asserted while CAS_L is toggled
N r
ow
s
N cols
DRAM
Column
Address
M-bit Output
M bits
N x M “SRAM”
Row
Address
A Row Address
CAS_L
RAS_L
Col Address Col Address
1st M-bit Access
Col Address Col Address
2nd M-bit 3rd M-bit 4th M-bit
34
2. SDRAM timing (Single Data Rate)
• Micron 128M-bit dram (using 2Meg16bit4bank ver) – Row (12 bits), bank (2 bits), column (9 bits)
RAS (New Bank)
CAS Precharge x
Burst
READ CAS Latency
35
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3. Double-Data Rate (DDR2) DRAM
[ Micron, 256Mb DDR2 SDRAM datasheet ]
Row Column Precharge Row’
Data
200MHz
Clock
400Mb/s
Data Rate 36
Memory Organizations
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Memory Organizations
Graphics Memory
• Achieve 2-5 X bandwidth per DRAM vs. DDR3 – Wider interfaces (32 vs. 16 bit)
– Higher clock rate
» Possible because they are attached via soldering instead of socketted DIMM modules
– E.g. Samsung GDDR5
» 2.5GHz, 20 GBps bandwidth
40
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DRAM Power: Not always up, but…
41
DRAM Modules
42
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DRAM Modules
43
A 64-bit Wide DIMM (physical view)
44
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A 64-bit Wide DIMM (logical view)
45
DRAM Ranks
46
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Multiple DIMMs on a Channel
47
Fully Buffered DIMM (FB-DIMM)
• DDR Problem – Higher capacity → more DIMMs → lower data rate (multidrop bus)
• FB-DIMM approach: use point to point links – introduces an advanced memory buffer (AMB) between memory
controller and memory module
– Serial interface between mem controller and AMB
– enables an increase to the width of the memory without increasing the pin count of the memory controller
48
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FB-DIMM challenges
• As of Sep 2006, AMD has taken FB-DIMM off their roadmap
• In 2007 it was revealed that major memory manufacturers have no plans to extend FB-DIMM to support DDR3 SDRAM
– Instead, only registered DIMM for DDR3 SDRAM had been demonstrated
– In normal registered/buffered memory, only the control lines are buffered whereas in fully buffered memory, the data lines are buffered as well
– Both FB and “registered” options increase latency and are costly 49
Intel Scalable Memory Buffer
50
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DRAM Channels
52
DRAM Channels
53
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DRAM Channel Options
54
Multi-CPU (old school)
55
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NUMA Topology (modern)
56
Memory Controller
57
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DRAM: Timing Constraints
58
DRAM: Timing Constraints
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Latency Components: Basic DRAM Operation
60
500 MHz DDR = 1000 MT/s
DRAM Addressing
61
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DRAM Controller Functionality
62
A Modern DRAM Controller
63
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Row Buffer Management Policies
68
DRAM Controller Scheduling Policies (I)
70
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DRAM Controller Scheduling Policies (II)
71
DRAM Refresh (I)
72
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DRAM Refresh (II)
73
DRAM Controllers are Difficult to Design
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DRAM Power Management
75
DRAM Reliability
• DRAMs are susceptible to soft and hard errors
• Dynamic errors can be – detected by parity bits
» usually 1 parity bit per 8 bits of data
– detected and fixed by the use of Error Correcting Codes (ECCs)
» E.g. SECDED Hamming code can detect two errors and correct a single error with a cost of 8 bits of overhead per 64 data bits
• In very large systems, the possibility of multiple errors as well as complete failure of a single memory chip becomes significant
– Chipkill was introduced by IBM to solve this problem
– Similar in nature to the RAID approach used for disks
– Chipkill distributes data and ECC information, so that the complete failure of a single memory chip can be handled by supporting the reconstruction of the missing data from the remaining memory chips
– IBM and SUN servers and Google Clusters use it
– Intel calls their version SDDC 76
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Looking Forward
• Continued slowdown in both density and access time of DRAMs → new DRAM that does not require a capacitor?
– Z-RAM prototype from Hynix
• MRAMs → use magnetic storage of data; nonvolatile
• PRAMs → phase change RAMs (aka PCRAM, PCME) – use a glass that can be changed between amorphous and crystalline
states; nonvolatile
77