ECE543Intro to Digital

Systems

Lecture 36Propagation Delay in Counter Designs II

04/26/2013

Announcement Postpone homework 9 to 4/29 (Monday) Homework #10

7-45, 9-1, 9-3, 9-5, 9-8, 9-16 Due May 3rd (Friday)

Final Exam May 13 (Monday), 6-8pm Kingsbury N343

Overview classes May 3rd and May 6th

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Outline Overview

Propagation delay Timing diagram for counter design

Synchronous counter

Asynchronous counter Clock period and frequency Computational block design

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Flip-Flop Timing Considerations - Parameters

Important timing parameters: Setup and hold times Propagation delay Maximum clocking frequency

MOD-16

CLK

A

B

C

FF tpd

FF tpd

AB AND tpd

FF tpd

1

0

1

0

1

0

1

0

TCLK, min

TCLK

TCLK >= AND tpd + FF tpd

MOD-6 Counter State transition diagram for the MOD-6 counter

Circle state; arrow state change Clear a MOD-8 counter when a count of six (110)

occurs

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MOD-6 Counter B output contains a spike or glitch

Caused by the momentary occurrence of the 110 state

MOD-6 counter produced by clearing a MOD-8counter when a count of six (110) occurs.

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CLK

A

B

FF tpd

FF tpd

C

BCNAND tpd

FF tpd

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1

0

1

0

1

0

1

0

1 2 3 4 5 6 7

CLK

A

B

FF tpd

FF tpd

C

FF tpd

BCNAND tpd

CLR tpd

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1

0

1

0

1

0

1

0

1 2 3 4 5 6 7

CLK

A

B

FF tpd

FF tpd

C

FF tpd

BCNAND tpd

CLR tpd

NAND tpd ECE543-Intro to Digital Systems 10

1

0

1

0

1

0

1

0

1 2 3 4 5 6 7

MOD-6 Counter B output contains a spike or glitch

Caused by the momentary occurrence of the 110 state

MOD-6 counter produced by clearing a MOD-8counter when a count of six (110) occurs.

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CLK

A

B

FF tpd

FF tpd

C

BC

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1

0

1

0

1

0

1

0

TCLK’

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Asynchronous (Ripple) Counter

Diagram

Waveform An asynchronous counter—state is notchanged in exact synchronism with the clock.

MSB LSB

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Propagation Delay in Ripple Counters

50ns

50ns

Homework 7-5 Four-bit ripple counter with frequency

f=20MHz (i.e. T=50ns), tpd=20ns=

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A

CLK

B

C

D

1

1

1

1

Homework 7-5 Four-bit ripple counter with frequency

f=20MHz (i.e. T=50ns), tpd=20ns.

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A

CLK

B

C

D

1

0

0

0

1

1

0

0

0

1

1

0

0

1

1

1

1

1

1

1

1

0

1

1

0

0

1

1

1

0

1

1

1

1

1

1

1

1

0

1

Propagation Delay

Synchronous counter Critical Path = FF tpd + sum of Logic gate tpds The fastest frequency = 1/ Critical Path

Asynchronous (Ripple) counter Critical Path = X * FF tpd (X, # of FFs used) The fastest frequency = 1/ Critical Path

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