ece496 design project t be marked, etc. etc. opening lecture this … · 2011. 9. 9. · 1 1 ece496...
TRANSCRIPT
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ECE496 Design Project Opening Lecture
Thursday, Sept. 8, 2011
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Section Assignment soon …
Registered students will be assigned a section & administrator next week
You need to register properly with Kelly Chan or you won’t be marked, etc. etc.
This is NOT our responsibility,
it is YOURS.
If you know you are not registered and are not ready to register, come and see me at the end of the evening
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Outline
February Info Session n Course overview and sign-up Tonight n An introduction to "Real-World Engineering" (Gillett) n Course Deliverables and Resources (Phang) Next Thursday, Sept. 15th, 7-8PM, MC102 n Preparing Your Project Proposal n Question/answer session
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Introductions - ECE496 Administrators
*Industrial Administrator with ECE backup
1. Khoman Phang 2. Phil Anderson 3. Bruno Korst 4. Hans Kunov
5.Hamid Timorabadi 6. John Taglione* 7. Ross Gillett* 8. Cristiana Amza
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Introductions - ECE496 Team Members Kelly Chan (Registration)
Mike Mehramiz (Design Centre)
Ken Tallman & ECP
G Also tonight … some past ECE496 Students: Richard Abrich
Real-time Simulation of Ultra-sound Fields (Cobbold) Aditya Thakkar
Theft Prevention Android Application (Lie)
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Design Fair (3 nights + showcase)
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ECE496 Goals
A capstone design project for ECE students to 1. Integrate their technical knowledge acquired through
their undergraduate education 2. Effectively communicate their ideas and work 3. Develop team work and project management skills
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
ECE496: An Introduction to
"Real World Engineering"
Ross Gillett, M. Eng, P. Eng September 2011
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R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Agenda
• What is Engineering? • ECE 496 is important !!! • Example of a Project • Summary
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
What is Engineering?
• Science/Math ("creating knowledge"): – Matrix mathematics – Electromagnetic Forces – Material properties – Circuit theory, etc
• Engineering ("creation using knowledge"): – The Canadarm2
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
ECE 496 is important !!!
ECE496 = "Real World" engineering: – ECE 496 teaches how to direct your skills toward
achieving an engineering goal • Teamwork • Project planning, tracking • Technical and business communication • Risk management • System design process (to a limited extent)
ECE496 knowledge Technical (undergrad) knowledge
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Teamwork
Orbital Express Satellite Servicing Demonstration Mission,
Launched February 2007
Why was teamwork essential? - There are not enough hours in one lifetime - Teamwork = parallel design activities
Canada's MOST Microsatellite Canada's Canadarm2
The Apollo Missions
Most (all) great "engineering feats" were accomplished by large teams of people
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R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
My Current Project
NEOSSat: 75 kg Microsatellite to launch in 2010 80 kg Microsatellite to launch in 2011
Team: More than 20 people over 3.5 years 5+ years (i.e. approximately 60 person-years)
2012 R. Gillett, P.Eng. (2011)
ECE496 The Design Process September 2003
Teamwork in Your Project
+
-U1
5
6
7
C2100
n
TL082
4
R910k
R851k
R10
330k
+12V
+12V
RCS10CTransmitter
+12V
GND
5
1
6
Circular PlasticConnector
+12V
R12
10k
R11
510
+
-U1
3
2
1TL082
+15V
8
4
R522k
R451k
R3330
k
+15V
+12V
R710k
R6510
R24k7
IRFZ30
IRFZ30
+12V
7812 C110u25V
+
R1100
k
R13
82k
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GRN
BLU
BLK
RED
+15V
AUX Input(Grip Enable)
ESTOP
AntennaOutput
Q1
Q2
D1
D2 DIP Switch Settings:3,7 Closed
Others open
D3
RP1
330k
+12V
D4
RP2
1M0
+12V
1N4007
1N4007 C3100
n
- Voltage regulator toaccept 15 Vdc system
voltage
- Comparators withhysteresis needed
- Correct input levelsto RF unit
- Correct connectorpinouts to Unit that I also
built
"Simple_design_by_one_individual"
B0
Transmitter Chip Set
TransmitDelay
Counter(Tx_Delay_Ctr)
TransmitBlock IDCounter
(Tx_Block_ID_Ctr)4-Bit Magnitude
Comparator
TransmitController
Transmit Block Selector
Transmitter Multiplexer
32 + Strobe
32 + Strobe
3
32
32
4
Next_Block
Clear/Disable
5_Blocks
All_Sent
A0
A2
A1
STRBI
RDYI
Clear_Disable
A3
Echo Data (From ReceiverSection)
OTX
'1' '0'
B1 B3
B2
8D0 . .D7D8 . .D39
To/From
Receiver
SectionControl Word Output Enable
ControlWord
3 Rx_Ok , Tx_Enable ,Node_Addressed
Tx_Completed
(2 Additional Strobes for Growth)
ESTOP Out
('A=B')
Phase Lock Loop
Pentium III with Parallel IO card
- Interface Voltage levels- Software Design- CommunicationHandshaking
- Centre Frequency- Tracking Range- Locking Range- Jitter
- Digital Logic / VHDL- Hardware Interface Voltage levels- Firmware/Software Interface Design- Communication Handshaking
Complex Design by Multiple Individuals (like your project!) - Requires a team to complete the job within the “skule” year
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Project Planning/Tracking
Perform Weekly Lawn MaintenanceCut Grass
Cut front lawnCut back lawnCut sides
Trim EdgesTrim property boundariesTrim around gardenTrim around trees
Trim BushesPrune side hedgesPrune back hedge
Case 1: One person does Lawn MaintenancePerform Weekly Lawn Maintenance
Cut GrassCut front lawnCut back lawnCut sides
Trim EdgesTrim property boundariesTrim around gardenTrim around trees
Trim BushesPrune side hedgesPrune back hedge
Case 2: Two people do the same, each with their own equipment
A team of two:
[By adding team members, the project progresses faster ...
No Teamwork
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Perform Weekly Lawn MaintenanceCut Grass
Cut front lawnCut back lawnCut sides
Trim EdgesTrim property boundariesTrim around gardenTrim around trees
Trim BushesPrune side hedgesPrune back hedge
Case 3: Three people do the same but can’t ‘Trim’ until the grass is cut (alogical dependency)
The "critical path" limits how fast the team can complete the job
... but not always]
Project Planning/Tracking
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R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Teamwork Requires Communication and Organization
• All team members work toward the same goal
• Each member working on separate portions – No duplication of effort
• Integrated portions will work together correctly – Correct functions, interfaces, and performance
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Technical/Business Communication
• Engineers and engineering companies:
– Create proposals and project summaries – Conduct design reviews – Report progress to customers (Progress reports) – Present project overviews to clients, conferences
and management • Seminars and/or posters
– Give project demonstrations
i.e. All of the activities in ECE496
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Risk Management
• How many of you:
– Bring more than one pen/pencil to an exam? – Back up important files from your computer to a CD/DVD? – Leave earlier for a 9AM exam than for a 9AM lecture? – Drive a car with a spare tire? Replaced a spare tire? – Will not base your project's success solely on obtaining
obscure components with uncertain delivery timelines?
• Then you have considered risk
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
System Design Process
• A process for efficient team-based design Goal → ”Use Cases” → System Requirements → Component Requirements → Detailed Design → Verification
• The "Goal" is the top level (single sentence) • The most famous "Goal" statement in history:
U.S. President J.F. Kennedy, 25 May 1961
"... I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the Moon and returning him safely to the earth".
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R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Functional FlowBlock Diagram(UseCaseA)
Functional FlowBlock Diagram(UseCaseN)
SystemReq'ts
ComponentReq'ts
System ArchitectureDefinition Document
Traceability
SubsystemReq'ts
Requirements
SubsystemArchitecture
Definition Document
Ops Concept * Verification
* *
DetailedDesign,
Manufacturing,and Test
Documentation
Detailed Design(H/W, S/W,
Mech ...)
Layouts,Part Lists,Assembly
Test Reqtsand
Procedures
System Design Process (Aerospace nomenclature shown)
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
ECE 496 is Narrower
Functional FlowBlock Diagram(UseCaseA)
Functional FlowBlock Diagram(UseCaseN)
SystemReq'ts
ComponentReq'ts
System ArchitectureDefinition Document
Traceability
SubsystemReq'ts
Requirements
SubsystemArchitecture
Definition Document
Ops Concept* Verification
* *
DetailedDesign,
Manufacturing,and Test
Documentation
Detailed Design(H/W, S/W,
Mech ...)
Layouts,Part Lists,Assembly
Test Reqtsand
Procedures
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Suppose a team of sculptors work together on a sculpture, each doing a separate part ....
Why must teams follow a Design Process?
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Why must teams follow a Design Process?
With no design process With a design process (each sculptor knew how his work needs to fit into the full 'system')
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R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Project Example using Requirement-Driven Design
Goal: Amplify the specified input signal, with large amounts of harmonic distortion, to drive 50Watts rms into a 8-ohm speaker
Input Signal Specification: Approx 80-150 Vrms signal, 40-10,000 Hz, 10kOhm output impedance
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Requirements permit a team to design "in parallel“ (Note that decomposition of requirements is a design decision)
Pre-Amplifier Stage Requirements: - Input Z: >10kohm - Output Z: < 100 ohm - Gain: 0 to +20 V/V log control - Output DC Voltage: < 1 mV - Frequency Response: -3db at 18kHz, single pole - User Tone Controls: Treble: ±10db notch at 8kHz Mid: ±10db notch at 1kHz Bass: ±10db notch at 150Hz - Power: ± 12 Vdc, < 200 mA
Gain Stage: Requirements: - Input Z: >1kohm - Output Z: < 20 ohm - Output DC voltage: < 1 mV - Gain: 15 V/V - Clipping at ± 8 Volts - Frequency Response: -3db at 20kHz - Power: ± 12 Vdc, < 500 mA
Output Driver Stage: Requirements: - Input impedance: >1kohm - Gain: 2 V/V - Output type: Class A-B with bias trim ** - Output power: 50 Watts into 8 ohm load - Power Supply: 110 Vac, 60 Hz input, ± 12 Vdc, 700 mA to other circuitry
Project Example
** Not really a pure requirement, because it dictates implementation
Input signal from Electric Guitar: 80 mV rms James Susan David
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
Example: Final Design James' circuit
Susan's circuit
David's circuit
R. Gillett, P.Eng. (2011) ECE496 The Design Process
September 2003
• You undergraduate theory forms the foundation of analysis / technical implementation – this is vital
• ECE496 focuses on organizing this knowledge for successful Engineering projects – Teamwork – Project planning and tracking – Design with Requirements – Technical and Business Communication
• These skills are highly valued in industry
Summary
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ECE496 Goals
A capstone design project for ECE students to 1. Integrate their technical knowledge acquired through
their undergraduate education 2. Effectively communicate their ideas and work 3. Develop team work and project management skills
ECE496 Roadmap, Milestones & Deliverables
Sept Nov Jan Dec Mar Feb Apr Oct 2011 2012
1st draft
Design Review meeting
Individual Progress Report
Final Report
Oral Presentations (in tutorials)
2nd draft Final version
Design Fair
Feb
Registration & background research
Project Proposal
Design Goal
System Requirements & Design
Design & Test Modules
System Integration & Testing
End of term status meeting
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ECE496 Deliverable Weighting
Start Decide What you must Do Do It End
Proj
ect P
ropo
sal
(fina
l dra
ft)
Des
ign
Rev
iew
Indi
vidu
al
Prog
ress
R
epor
t/eva
l O
ral R
epor
t
Des
ign
Fair
fall spring
15% 8% 17%
35% 22 %
5%
Fina
l Rep
ort
15%
Dec
embe
r rev
iew
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Your Final Report: A Living Document
n Evolving your final report from the start
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Support Resources
n The Supervisor’s Almanac n Friends of Design
– Discussion forum: http://friendsofdesign.utoronto.ca/forum – Website: https://sites.google.com/site/utfriendsofdesign/ – Training workshops (microcontrollers, PCB layout, etc.)
n The Design Centre (SFB520) n Funding: OCE Connections and Design Project Fund n Books
– P. Anderson, ECE298 System Design Course Notes – Available on ECE496 website
– J. Eric Salt and Robert Rothery, Design for Electrical and Computer Engineers, Wiley, ISBN 0-471-39146-8
– In Eng. Library (5 copies on 1day short term loan)
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Supervisor’s Almanac
n Help your supervisor by keeping on track
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Working Together
Supervisor Administrator
Students
• Marking consistency • Engineering design & project planning • Effective technical communication
• The ‘expert client’ • Defining the problem • Getting the technical details ‘right’
Friends of Design
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Design Centre
n Sandford Fleming, room B520 n Borrow equipment, computers, lockers, PCB CAD tools,
soldering station and microscope, wireless transceivers,etc.
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Funding Support
n Students contribute up to $100 each n Other sources of funding and resources include:
– The ECE Department Design Project Fund. Students apply for this funding around the time of the Design Review.
– Supervisors who contribute out of their own funds, particularly where the student projects will aid their research.
– Industrial sponsors – Matching funding from the University and/or Ontario Centres of
Excellence (OCE) through the OCE Connections Initiative
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Mark Normalization
n Mark normalization ensures mark consistency across sections n Your marks can go up or down (slightly) n Marks heavily weighted towards final deliverables n Put marks in perspective - focus on making a strong impression with
your supervisor and administrator
Section Averages(unadjusted)
60
65
70
75
80
85
90
95
1 2 3 4 5 6 7 8 9 10 11 12
Series1Series2Series3Series4Series5Series6Series7
Concept / Proposal / Progress #1 / Progres#2 / Oral / Fair / Final Report / Total
Section Averages (adjusted)
60.0
65.0
70.0
75.0
80.0
85.0
90.0
95.0
1 2 3 4 5 6 7 8 9 10 11 12
Series1
Series2
Series3
Series4
Series5
Series6
Series7
Concept / Proposal / Progress #1 / Progres#2 / Oral / Fair / Final Report / Total
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Awards
n ALOHA Award ($10,000) n Orbis Prize in Software Design ($4k & $1k) n CNIB Hochhausen Prize n Gordon E. Slemon Design Award ($1k) n Centennial Thesis Awards (2) n Certificates of Recognition/Invitation to Final Showcase Many students get jobs
based on their project!
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Reminder to students (1 of 3)
n First draft of Project Proposal due Tue. Sept. 20th at 3pm sharp in drop off boxes across from Design Centre (SFB520). Softcopies submitted through your ECF account (make sure you can log in!)
n Must petition if you hand in a deliverable late or if you fail to appear for an oral presentation (need medical certificate in the event of sickness)
n Projects involving testing on animals or humans require an ethics review
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Reminder to students (2 of 3)
n Self-manage. It is easy to “put off” work that has no deadline, but this catches up with you.
n Don’t use the time you should be allocating to the course to do other courses
n Don’t ignore other courses to do more work in this one n Watch for long delivery times, long processes... n Look ahead to the design fair & final report.
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Reminder to students (3 of 3)
n Marks are NOT for deliverables alone. Supervisor will assign 50% based on his/her evaluation of your work, including biggest chunk of the “final report” mark.
n Keep notes. Keep a notebook. n Do the work, then report on it. Think about what you are
reporting and make the report appropriate. n Writing well helps, but you are COMMUNICATING
about your project. Review the feedback. n Have regular, focused meetings with your supervisor. n You, not your supervisor and not your administrator, are
responsible for your project!
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Upcoming Events
n Thurs. Sept. 15th Lecture on Project Proposal n Tue. Sept. 20th Draft A due n Tue. Sept. 27th Draft B due n Thurs. Sept. 29th Draft A returned during Meet your
Administrator Night
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Questions……