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ECE 428 Programmable ASIC Design

Haibo WangECE Department

Southern Illinois UniversityCarbondale, IL 62901

FPGA Implementation of Combinational Logic

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Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables

Any single function of five variables Any function of four variables together with some functions of six variables Some functions of up to nine variables.

Combinational Logic Implemented by Xilinx XC4000 CLB

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Combinational Logic Implemented by Xilinx XC4000 CLB

F(a, b, c, d, e) = aF(a=1) + aF(a=0) Both F(a=1) and F(a=0) are four-input functions

Why can any five-input function be implemented by a XC4000 CLB?

LUT 1

LUT 2

LUT 3

a

bcde

cde

b

F(a=1)

F(a=0)

F(a,b,c,d,e)

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Combinational Logic Implemented by Xilinx XC4000 CLB

Any function of four variables together with some functions of six variables can be implemented by a single CLB

F(a,b,c,d,e,f) = abF1 + abF2 + abF3 + abF4F1 = F(a=1, b=1); F2 = F(a=1, b=0); F3 = F(a=0, b=1); F4 = F(a=0, b=0)

What kind of six variable functions can be implemented with another four variable function within a single CLB?

Condition: Among F1-F4, three of them are constant (e.g. F1=1, F2=F3=0)

LUT 1

LUT 2

LUT 3Six-variable function

Four-variable function

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Example: A Six-Input Majority Function Six-input majority function: the function output is 1 if three or more than

three inputs are 1. =i

imfedcbaF ),,,,,( (mi Minterm of function F)Number of inputs

with logic 1Minterms

6 abcdef

5 abcdef abcdef abcdef abcdefabcdef abcdef4 abcdef abcdef abcdef abcdef

abcdef abcdef abcdef abcdefabcdef abcdef abcdef abcdefabcdef abcdef abcdef

3 abcdef abcdef abcdef abcdefabcdef abcdef abcdef abcdefabcdef abcdef abcdef abcdefabcdef abcdef abcdef abcdefabcdef abcdef abcdef abcdef

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Example: A Six-Input Majority FunctionF(a=1,b=1) =e+c+fc+edF(a=1,b=0) =F(a=0,b=1) = cd+ef+df+ed+fc+ec (F2, F3)

F(a=0,b=0) =cdf + cde + efc + efd (F4)

F = abF(a=1,b=1) + abF(a=1,b=0) + abF(a=0,b=1) + abF(a=0,b=0)

= a{bF(a=1,b=1) + bF(a=1,b=0)} + a{bF(a=0,b=1) + bF(a=0,b=0)}

Fa Fa

(F1)

F1

F2Fa

bcdef

cdef

F3

F4Fa

bcdef

cdef

Fa1

CLB CLB CLB

F

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Decoding Circuits

2-to-4 Decoding circuit

x1x2

x1x2

x1x2

x1x2

CLB

CLB

x1x2

o1

o2

o3

o4

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Decoding Circuits 10-to-1024 Decoding circuit

F1

F2F3

x0

F4

F5CLB CLB1

1

x1x2x3

x4x5x6x7x8

1

1 O1023

O1022

It needs 1024 CLBs; expensive to implement. It is a two level implementation, resulting large delay.

Disadvantages

F1= x4x5x6x7F2= x0x1x2x3F3= x8F1F2

x9

F4= x9F3F5= x9F3

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Dedicated Decoding Circuits in Xilinx FPGAs

Four dedicated programmable decoding circuits are included in Xilinx FPAGs.

The number of decoder inputs ranges from 42 to 132 for different devices.

The decoding circuits use wired-AND gate structures (like the AND plane in PAL).

AB

C

I/O I/OFrom CLB

ABCBAC

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Combinational Logic implemented by Actel ACT1

Actel ACT1 Cell

ABC

Y Y

01

01

01

01

01

01

0

C

BA

Y=ABC = C(AB) + C0= C(B A+B0) + C0

3-input AND gate implementation

Example

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Combinational Logic implemented by Actel ACT1 For a general three-input function

F(a, b, c) = aF(a=1) + aF(a=0)= a(bF(a=1,b=1) + bF(a=1,b=0)) + a(bF(a=0 b=1) + bF(a=0,b=0))

Note: F(a=1,b=1), F(a=1,b=0), F(a=0,b=1) and F(a=0,b=0) must be one of the the following values: c, c, 0, 1

F

01

01

01

F(a=0,b=1)

F(a=1,b=1)F(a=1,b=0)

F(a=0,b=0)

b

baa

If for every variable its complement is also available, any three-input combinationalfunction can be implemented by a single ACT cell.

Some functions with inputs up to eight can be implemented by a single ACT1 cell.

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Example: A Six-Input Majority Function Six-input majority function: the function output is 1 if three or more than

three inputs are 1. F(a=1,b=1,c=1) = 1 (F1)F(a=1,b=1,c=0) = F(a=1,b=0,c=1) =F(a=0,b=1,c=1) = e+f+d (F2,F3,F4)F(a=1,b=0,c=0) =F(a=0,b=1,c=0) = F(a=0,b=0,c=1) = ef+df+ed (F5,F6,F7)F(a=0,b=0,c=0) = efd (F8)

F = abcF1 + abcF2 + abcF3 + abcF4 + abcF5 + abcF6 + abcF7 + abcF8

= ab(cF1+cF2) + ab(cF3+cF5) + ab(cF4+cF6) + ab(cF7+cF8)

F1 F2 F3 F4

= a(bF1 + bF2) + a (bF3 + bF4)

H1 H2

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Example: A Six-Input Majority Function

01

010

1

01

010

1

01

010

1

01

010

1

01

010

1

01

010

1

e1

f1d

d+f+e

F2, F3, F4

e

1f

dfd0

ef+df+ed

F5, F6, F7

efd

0edf

F8

bc

F1F2

cF3F5

F1

F2

bc

F4F6

cF7F8

F3

F4

H1

H2

aH1H2

0

F

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Decoding Circuits 4-to-16 Decoding circuit

01

01

01

O0 abcd

c

d

b

a

a a b b c c d d

0

00

0

It needs 16 ACT1 cells

Decoder circuits with more than four inputs need multi-level implementation.

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Decoding CircuitsA 10-to-1024 decoder needs

x0 x9

cell cell

x0 x9

level1level2

level3

4-to16

4-to16

2-to-4

x0~x3

x4~x7

x8~x9

It needs 1070 ACT1 cells

Actel FPGAs also use dedicated decoding circuits.

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Speed Considerations For a combinational circuit implemented by a single memory block, its delay

depends on neither the function type nor the input transition patterns.

Memory

For a combinational circuit implemented by mux-based FPGAs, its delay normally depends on the function type and the input transition patterns.

01

01

01

01

01

01

a

1

0

F1=a

ab

0

1F2=ab

The delay of F1 is smallerthan that of F2

For F2, d1 is the output delay when inputs switch froma=1 and b=1 to a=0 and b=1;d2 is the delay when inputsswitch from a=1 and b=1 toa=1 and b=0.

d2 > d1 Assume the delay of OR gate is smaller than that of MUX

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Speed Considerations

To reduce propagation delay, always place signals which arrive late close to the output.

LUT1LUT2

abcde

LUT1LUT2

abc

de

Signal e always arrives late

GoodBad

CLB CLB

01

01

01

ab

0

1F2=ab

01

01

01

ba

0

1F2=ab

Good Bad

Signal a always arrives late

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Other Considerations

Always try to balance signal paths to avoid glitches

CLB CLB CLB

CLB

CLB

CLB

a

b

y

If possible, change circuitimplementation into the following style

y

a

b