ece200 – computer organization chapter 8 – interfacing processors and peripherals
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ECE200 – Computer Organization
Chapter 8 – Interfacing Processors and
Peripherals
Chapter 7 versus Chapter 8 views
Chapter 7 covered the high-level interface between memory and I/O
Chapter 8 covers the nitty-gritty details of getting data in and out of I/O devices
You are only responsible for the subset of Chapter 8 that we cover in class
The big picture
Memory-I/O bus handles data and communication between the CPU, memory, and I/O
Bus basics
A bus consists of A set of wires over which data and bus commands are
transferredCommunication protocols for determining bus
ownership, (which device can currently use the bus), bus commands, and responses to commands
To use the bus, a device (cache, memory, or I/O) must first arbitrate for the usage of the bus in order to get exclusive usage for the required time period
A bus operation may consist of sending Bus commands (e.g., read, write)Addresses (e.g., of the memory location to read or
write)Data (e.g., to be returned in response to a read
command)
Split transaction bus
The bus is free for other uses after a command that requires a response is sent over the bus
Example L2 cache miss occursL2 cache gains control of the bus, and then sends a
request to MM for the block MM receives the request and starts the access, during
which the bus is free for other usesWhen the MM has completed the access, it arbitrates for
the bus, and then sends the requested data to the L2 cache
Implementation of a split transaction bus is very complicated!
Most memory-I/O buses in laptop/desktop/server systems are split transaction and 64-256 bits wide (for data)
The OS and I/O
User programs request I/O services through system call exceptions to the OS
The OS provides the low-level software routines (drivers) that send commands to the I/O device and read status back
Multiple programs need to share I/O services and need them to be protected from each other
Communicating with an I/O device
The CPU sends commands to the I/O device over the memory-I/O bus and reads status back
Approach 1: memory-mapped I/OA portion of the memory address space is reserved for
sending commands (as store instructions) and reading status (as load instructions)
The reserved pages are designated as non-cacheable so that they bypass the caches
The memory addresses are ignored by the main memoryParticular addresses are reserved for particular devicesUser programs cannot use these instructions, only the OSUsed by MIPS and many others
Approach 2: special privileged I/O instructions are defined in the ISAUsed by X86
Checking device status
The OS needs to know when an I/O action (e.g., mouse movement, printer done) has occurred
With polling, the OS periodically reads the device status registers to check if particular status bits have been set by the device
In interrupt-driven I/O, the device raises an interrupt (exception) when it has taken some action The OS determines the device through the exception
information and takes actionUseful for devices with high data rates (e.g., disks) for
which the overhead of polling would be prohibitive
Data transfer between I/O and memory
Simplest approach is for the CPU to perform the data transfer through load and store operations (assuming memory-mapped I/O)CPU determines either through polling or interrupts
that the transfer is done and another can occur
load
store
Data transfer between I/O and memory
A common higher performance alternative is direct memory access (DMA) in which the device directly transfers data to/from memory without CPU intervention
DMA operation
Processor provides to the DMA device the number of bytes to transfer, the memory address, and the operation to be performed
DMA operation
The device performs the transfer over the memory-I/O bus to or from memory
DMA operation
The device interrupts the processor
DMA operation
The processor reads the status registers to determine if the operation completed without errors
M68HC11 embedded microprocessor
8-bit microprocessor
Read-Only Memory (ROM) Holds code (program)Program once, not easily writable thereafterContents are maintained when system is powered off
Electrically Erasable Programmable ROM (EEPROM)Can be written, but slowlyHolds configuration information, etc.Contents are maintained when system is powered off
SRAMUsed to hold variables, etc.
M68HC11 embedded microprocessor
Serial and parallel I/O interfaces
Analog to digital (A/D) converterConverts analog input signals (voltage level) to a
binary representation that can be processed within the CPU
Timer Can be used to periodically interrupt the CPU to
perform some function, e.g., read incoming data on a parallel port
M68HC11 block diagram
M68HC11 parallel I/O interfaces
Five ports (PORT A-PORT E)
8 bits wide except for D (6 bits)
PORT B is output only
PORT E is input onlyCan be used as input for an A/D converter
PORT C and PORT D are bidirectionalIndividual pins can be configured as inputs or outputs
Configuring parallel I/O ports
Parallel I/O ports C and D can be configured
Whether each pin is used as an input or output Type of handshaking used to interface with
peripheralsWhether interrupts are generated on external events
Parallel I/O registers lie between the CPU and the I/O portsTo read or write port data and for configuration
Parallel I/O registers
register nameaddress bit 7 6 5 4 3 2 1 0
$1000
$1002
$1003
$1004
$1005
$1007
$1008
$1009
$100A
$1026
$1028
PORTA
PIOC
PORTC
PORTB
PORTCL
DDRC
PORTD
DDRD
PORTE
PACTL
SPCR
bit 7 6 5 4 3 2 1 0
STAF STAI CWOM HNDS OIN PLS EGA INVB
bit 7 6 5 4 3 2 1 0
bit 7 6 5 4 3 2 1 0
bit 7 6 5 4 3 2 1 0
bit 7 6 5 4 3 2 1 0
0 0 5 4 3 2 1 0
0 0 5 4 3 2 1 0
bit 7 6 5 4 3 2 1 0
DDRA7 PAEN PAMOD PEDGE 0 0 RTR1 RTR0
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
Addresses for PORT A through PORT E can be referenced for reading or writing port data
Data direction registers
Ports C and D each have an 8-bit data direction register (DDRC and DDRD)
The direction (input or output) of each pin is configured by writing a value to the DDR bit0 configures as input, 1 as output
Handshaking modes
Handshaking refers to the manner in which two interfacing units coordinate data transfer
Three handshake modes available for Port C Simple strobe modeFull-input handshakeFull-output handshake
Two signals (STRA and STRB) used for status or latching of data
PIOC register is used to configure handshakingWritten by software to set up the desired mode,
polarity of signals, etc.
Simple strobe handshaking – output
Enabled when HNDS=0 in the PIOC register
STRB is pulsed in conjunction with a write to the PORT B register
INVB control bit in PIOC specifies the STRB polarity
Timing signals transition in relation to the HC11 clock
PORT B
STRB
new PORT B data
Simple strobe handshaking – input
Transition on STRA is used to latch incoming data into the PORT C register
Polarity determined by EGA bit in PIOC
STAF bit in PIOC gets set after STRA latches data, and reset when data is read out by the CPUSTAF 01 creates an interrupt if STAI=1 in PIOC
STRA is asynchronous in relation to HC11 clock
STAF transition occurs in relation to HC11 clock
PORT C
STRA
new PORT C data
STAF
Full-input handshaking
Enabled when HNDS=1 and OIN=0 in PIOC
PORT C used as an input
Transition on STRA used to latch incoming data
STRB used as a “ready” signal that indicates that the HC11 can accept new data on PORT CLatching data into PORT C negates STRBReading data out of PORT C asserts STRBPORT C
STRA
new PORT C data
STAF
STRB
Read of PORT C
Full-output handshaking
Enabled when HNDS=1 and OIN=1 in PIOC
PORT C used as an output
STRB is asserted when data is written to PORT C
STRA is driven by the external peripheral to indicate that it has received the dataSTRB gets deassertedSTAF is set indicating that new data can be written to
PORT C
PORT C
STRB
new PORT C data
STRA
Write of PORT C
STAF
MC68HC11 Timer
The timer can be used to measure the time of events and to generate periodic interrupts
The timer consists ofA 16-bit free-running counter
Sets an overflow bit when it wraps around to 0A prescalar that sets the number of clock cycles between
which the counter is incremented1, 4, 8, or 16
Comparators for measuring elapsed timeA real-time interrupt function
The timer can generate periodic interruptsUseful for forcing the CPU to perform some function on a
regular basis to meet some deadline, e.g., monitoring temperature and controlling coolant flow
Interrupt handler calls the functions to be periodically performed
A/D converter
Each PORT E input serves as an input channel for the A/D converter
All 8 inputs can be connected and sampled at different times
A/D converter
Converter creates a binary representation in one of the four A/D result registers (ADR1-ADR4) that is proportional to the voltage on the input channelADR1, ADR2, ADR3, ADR4 are at addresses $1031,
$1032, $1033, and $1034, respectively
Other registers allow you to configure the converter
Questions?