ECE 429 – Introduction to VLSI DesignLecture 01 Introduction

Professor Jia WangDepartment of Electrical and Computer Engineering

Illinois Institute of Technology

January 9, 2018

ECE 429 – Introduction to VLSI Design Spring 2018 1/22

Outline

Administrative Issues

Introduction

ECE 429 – Introduction to VLSI Design Spring 2018 2/22

Outline

Administrative Issues

Introduction

ECE 429 – Introduction to VLSI Design Spring 2018 3/22

Instructor

I Professor Jia Wang

I Office: 317 Siegel Hall

I Phone: 312 567-3696I E-Mail: jwang@ece.iit.edu

I Please start your email subject line with [ECE429].

I Office hours:I Tue./Thur. 3:30 PM – 4:30 PM,I Or by appointment

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Lecture Information

I Time: Tue./Thur. 1:50 PM – 3:05 PM

I Location: Stuart Building 111I Home Page:

http://www.ece.iit.edu/~jwang/ece429-2018s/I Important messages will also be delivered through your IIT

email.I Blackboard (http://blackboard.iit.edu/) is used for

lecture videos, homework/report submissions, and gradings.

I Required Textbook: “CMOS VLSI DESIGN: A Circuits andSystems Perspective” (4th ed.)Neil H.E. Weste, and David Harris, Addison-Wesley, ISBN:0321547748

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Prerequisite

ECE 218 and ECE 311

I Familiarity with circuits, logic and digital system design.

I Experience with CAD tools and UNIX is a plus.

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Course Outline

Main topic: VLSI digital design, from RTL to layoutI VLSI digital design at various abstraction levels

I MOS transistors: I-V curvesI Gates and interconnects: delay and powerI Circuit netlists: circuit families and static timingI RTL subsystems: adders, memories, etc.

I Design flows (EDA tools), issues, and trends

ECE 429 – Introduction to VLSI Design Spring 2018 7/22

Course Objectives (ABET)

After completing this course, you should be able to:

1. Design VLSI circuits from register-transfer level to layouts.2. Discuss the basic attributes of VLSI systems, their impact

upon society, and the tradeoffs between design metrics,especially speed, power, and cost.

3. Design experiments to measure design metrics and explain thedifferences between theoretical models and experiments.

4. Identify the basic parts of VLSI design flows.Compare/contrast both custom and standard-cell baseddesign methodologies.

5. Explain and analyze dynamic techniques such as chargesharing and current leakage and how it impacts specificcircuits from a dynamic circuits perspective.

6. Complete an engineering design incorporating engineeringstandards and realistic constraints.

7. Prepare an informative and organized design project reportwith solid supporting data and deliver an oral presentation.

ECE 429 – Introduction to VLSI Design Spring 2018 8/22

Homeworks/Labs/Project

I 5 Homeworks: every other week, usually due in 2 weeksI 9 Labs: every week, usually due in 1 to 2 weeks

I No lab in the first week.

I Final project: two parts, plus oral demonstrationI Late homeworks and lab/project reports will not be graded.

I Submit online in Blackboard only.

I For possible late submissions due to extraordinary reasons, youshould contact me before the deadline.

ECE 429 – Introduction to VLSI Design Spring 2018 9/22

ECE UNIX Network for Labs/Project

I In SH 310A: Available depending on your registration

I Remotely: 24 × 7, mandatory for online students,recommended for main campus students

I Remote lab access guide will be posted soon.

I Please wait for my email for login information.

ECE 429 – Introduction to VLSI Design Spring 2018 10/22

Ethics (Very Seriously)

I Read “IIT Code of Academic Honesty” and “IEEE Code ofConduct” (posted on the course website).

I Projects/labs/homeworks should be done individually.I Discussions on homeworks/labs/projects are encouraged.I Code from the lectures and instructions in this course can be

used directly.

I All other writings and code should be BY YOURSELF.I NEVER SHARE YOUR WRITINGS/CODE WITH OTHERS!I NEVER USE WRITINGS/CODE FROM OTHERS!

I Minimum punishmentI First time: 0 points for the project/labI Second time: E grade for the courseI All violations will be reported to the department and are

subjected to additional punishment, including expulsion fromthe university.

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Exams

I Midterm: Tue. 3/6 or Thur. 3/8, 1:50 PM – 3:05 PM

I Final exam: TBD

I Closed book/notes, cheat sheet allowed

I Main campus students and Internet students staying at maincampus should take exams in this room.

I Check http://www.iit.edu/registrar/important_

dates/final_exam_schedule.shtml for other issues.

I Makeup exams will NOT be given.

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Grading

I PercentageI Homeworks: 2%*5=10%I Labs 2-9: 3%*8=24%I Project: 4%+8%+4%=16%I Exams: 15%+35%=50%I Class Participation: extra 5%

I Complete all homeworks/labs/projectI Make progress during the semester

I Additional bonus points in labs and project

I Letter gradeI A: 90I B: 80I C: 60I D (undergraduate only): 55

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Reading Assignment

I This lecture: 1.1, 1.2

I Next lecture: 1.3, 2.1, 2.2

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Outline

Administrative Issues

Introduction

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History

I Vacuum Tube: first 1/2 of 20th centuryI Large, expensive, consume a lot of power, unreliable

I Bipolar Transistor: first transistor – 1947I First integrated circuit – 1957I More reliable and power-efficient (than vacuum tubes)I As current is required for operation, limited device density on a

single chip.

I MOSFET: Metal–Oxide–Semiconductor Field–Effect TransistorI Consume much less power/current than bipolarI nMOS or pMOS: still consume power when idleI Intel 4004 – 1971: nMOS process

I CMOS: Complementary Metal–Oxide–SemiconductorI Gates use both nMOS and pMOSI Widely adopted since 80s for almost all digital ICsI Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Spring 2018 16/22

History

I Vacuum Tube: first 1/2 of 20th centuryI Large, expensive, consume a lot of power, unreliable

I Bipolar Transistor: first transistor – 1947I First integrated circuit – 1957I More reliable and power-efficient (than vacuum tubes)I As current is required for operation, limited device density on a

single chip.

I MOSFET: Metal–Oxide–Semiconductor Field–Effect TransistorI Consume much less power/current than bipolarI nMOS or pMOS: still consume power when idleI Intel 4004 – 1971: nMOS process

I CMOS: Complementary Metal–Oxide–SemiconductorI Gates use both nMOS and pMOSI Widely adopted since 80s for almost all digital ICsI Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Spring 2018 16/22

History

I Vacuum Tube: first 1/2 of 20th centuryI Large, expensive, consume a lot of power, unreliable

I Bipolar Transistor: first transistor – 1947I First integrated circuit – 1957I More reliable and power-efficient (than vacuum tubes)I As current is required for operation, limited device density on a

single chip.

I MOSFET: Metal–Oxide–Semiconductor Field–Effect TransistorI Consume much less power/current than bipolarI nMOS or pMOS: still consume power when idleI Intel 4004 – 1971: nMOS process

I CMOS: Complementary Metal–Oxide–SemiconductorI Gates use both nMOS and pMOSI Widely adopted since 80s for almost all digital ICsI Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Spring 2018 16/22

History

I Vacuum Tube: first 1/2 of 20th centuryI Large, expensive, consume a lot of power, unreliable

I Bipolar Transistor: first transistor – 1947I First integrated circuit – 1957I More reliable and power-efficient (than vacuum tubes)I As current is required for operation, limited device density on a

single chip.

I MOSFET: Metal–Oxide–Semiconductor Field–Effect TransistorI Consume much less power/current than bipolarI nMOS or pMOS: still consume power when idleI Intel 4004 – 1971: nMOS process

I CMOS: Complementary Metal–Oxide–SemiconductorI Gates use both nMOS and pMOSI Widely adopted since 80s for almost all digital ICsI Consume negligible power when idle

ECE 429 – Introduction to VLSI Design Spring 2018 16/22

Moore’s Law

Process scaling enables the production of integrated circuits (ICs) with millions of

transistors – the number grows exponentially.

Power consumption becomes a bottleneck again since 2000s. Currently, high-end

CPUs and GPUs have a transistor count of several billions.

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Applications

I VLSI chips are essential for digital and mixed-signal systems

I Most systems operating on electrical power or battery

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Applications

I VLSI chips are essential for digital and mixed-signal systems

I Most systems operating on electrical power or battery

ECE 429 – Introduction to VLSI Design Spring 2018 18/22

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.I Same applies even if VLSI is replaced by some technique in

future.

I Manual design is simply beyond what human beings canhandle for complex systems.

I Trial-and-error approaches won’t work as transistors becomeextremely small.

I Very costly (money and time) to manufacture one chipI When you find a real chip fails, very difficult to tell why.

I Design automation comes to the rescueI Computer-aided design (CAD) tools not only assist designers

for simulation and debugging but actually define the designflow.

ECE 429 – Introduction to VLSI Design Spring 2018 19/22

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.I Same applies even if VLSI is replaced by some technique in

future.

I Manual design is simply beyond what human beings canhandle for complex systems.

I Trial-and-error approaches won’t work as transistors becomeextremely small.

I Very costly (money and time) to manufacture one chipI When you find a real chip fails, very difficult to tell why.

I Design automation comes to the rescueI Computer-aided design (CAD) tools not only assist designers

for simulation and debugging but actually define the designflow.

ECE 429 – Introduction to VLSI Design Spring 2018 19/22

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.I Same applies even if VLSI is replaced by some technique in

future.

I Manual design is simply beyond what human beings canhandle for complex systems.

I Trial-and-error approaches won’t work as transistors becomeextremely small.

I Very costly (money and time) to manufacture one chipI When you find a real chip fails, very difficult to tell why.

I Design automation comes to the rescueI Computer-aided design (CAD) tools not only assist designers

for simulation and debugging but actually define the designflow.

ECE 429 – Introduction to VLSI Design Spring 2018 19/22

Electronic Design Automation (EDA)

I Design is a must to turn transistors into functional systems.I Same applies even if VLSI is replaced by some technique in

future.

I Manual design is simply beyond what human beings canhandle for complex systems.

I Trial-and-error approaches won’t work as transistors becomeextremely small.

I Very costly (money and time) to manufacture one chipI When you find a real chip fails, very difficult to tell why.

I Design automation comes to the rescueI Computer-aided design (CAD) tools not only assist designers

for simulation and debugging but actually define the designflow.

ECE 429 – Introduction to VLSI Design Spring 2018 19/22

Why take this course?

I VLSI design 6= Verilog (or VHDL, etc) programmingI Garbage In, Garbage Out

I You need to specify more than the functionality for superiorperformance within a budget.

I A chip design shown to be working by a tool is not necessaryworking in reality.

I Making further improvements requires to understand thedetailed analysis provided by tools.

I CAD tools define the design flow, i.e. the abstraction levels.I Learn all design aspects in addition to system functionality at

various abstraction levels of digital design in this course.

ECE 429 – Introduction to VLSI Design Spring 2018 20/22

Why take this course?

I VLSI design 6= Verilog (or VHDL, etc) programmingI Garbage In, Garbage Out

I You need to specify more than the functionality for superiorperformance within a budget.

I A chip design shown to be working by a tool is not necessaryworking in reality.

I Making further improvements requires to understand thedetailed analysis provided by tools.

I CAD tools define the design flow, i.e. the abstraction levels.I Learn all design aspects in addition to system functionality at

various abstraction levels of digital design in this course.

ECE 429 – Introduction to VLSI Design Spring 2018 20/22

Why take this course?

I VLSI design 6= Verilog (or VHDL, etc) programmingI Garbage In, Garbage Out

I You need to specify more than the functionality for superiorperformance within a budget.

I A chip design shown to be working by a tool is not necessaryworking in reality.

I Making further improvements requires to understand thedetailed analysis provided by tools.

I CAD tools define the design flow, i.e. the abstraction levels.I Learn all design aspects in addition to system functionality at

various abstraction levels of digital design in this course.

ECE 429 – Introduction to VLSI Design Spring 2018 20/22

Challenges in VLSI Design

I System complexity: more functionality within shorttime-to-market.

I Silicon complexity: physical effects can no longer be ignored,e.g., interconnects, power, thermal, process variations,manufacturability.

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Summary

I Know what to learn in this course

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