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ECE 368: CAD-Based Logic Design

Lecture Notes # 5

Sequential Circuit (Finite-State Machine) Design

SHANTANU DUTT

Department of ECEUniversity of Illinois, Chicago

Phone: (312) 355-1314: e-mail: dutt@ece.uic.eduURL: http://www.ece.uic.edu/~dutt

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Finite State Machine (FSM) Design• FSMs are different from counters in the sense that they have external I/Ps, and state transitions are dependent on these I/Ps and the current state.• Example : Problem Statement

There is a bit-serial I/P line. Design an FSM that outputs a ‘0’if an even # of 1’s have been received on the I/P line and the outputs a ‘1’ otherwise.

Note : If a synchronous sequential circuit is being designed, the counting of the # of 1s occur every clock cycle.

FSMx O/p y

CLK

CLK

x# of1s

even(0)

odd(1)

even(2)

odd(3)

odd(3)

Tlogic + Tsetup

Samplinginstances

Approach to determining states of an FSM:• First determine the min # of useful information classes about past i/ps required to

solve the problem (requires analytical thinking about the problem)• Each info class a potential state• From this 1st cut at possible states, determine if there are well-defined transitions

from each state for all possible i/p values.• If so then these states can be the final states; otherwise some states may need to be

refined into multiple states to achieve well-defined transitions (see FSM word prob. 1).

• In this problem, only 2 classes of information are reqd: whether an even # of 1s have been received so far, or an odd # of 1s have been received so far & there are well-defined transitions between them. Thus these 2 classes become 2 states.Solution 1: (Mealy)

0/0

Even

Odd

1/11/0

0/1

Reset

Output

Input

Transition Arc

O/P is dependenton current state andinput in Mealy

Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse).

0Even

11

0

Reset[0]

Odd [1]

Output

Input

Output is dependent only on current state

Solution 2: (Moore)

Moore Machine: Output is associatedwith the state and hence appearsafter the state transition take place.

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Determining a Reset State:• A reset state is a state the the FSM (seq ckt) should be in when it is just powered on.• In other words, a reset state is a state the FSM should be in, when it has recvd no

i/ps• Based on the above definition, decide if any of the states determined so far can be a

reset state. E.g., in the parity detector problem, the even state qualifies to be the reset state, as in the reset state no i/ps recvd zero 1’s recvd even # of 1’s recvd it can be the even state

• If not, then need to have a separate reset state, and have the correct transitions from this state to the other states (depending on the problem solved by the FSM).

Solution 1: (Mealy)0/0

Even

Odd

1/11/0

0/1

Reset

Output

Input

Transition Arc

O/P is dependenton current state andinput in Mealy

Mealy Machine: Output is associatedwith the state transition, and appearsbefore the state transition is completed(by the next clock pulse).

0Even

11

0

Reset[0]

Odd [1]

Output

Input

Output is dependent only on current state

Solution 2: (Moore)

Moore Machine: Output is associatedwith the state and hence appearsafter the state transition take place.

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FFs

External I/Ps External O/Ps

m1 m2

nn

Comb.Logic

CLK

FFsn

CLK

n

OutputLogic

m2

Next StateComb.Logic

m1

ExternalI/Ps

External Outputs

Mealy Machine Model Moore Machine Model

even odd

Time t : Even I/P = propagation delay of logic of Mealy M/C

t t+ t+TCLKt+TCLK+2

Evenx=1O/P=0

O/P=1(Mealy)

Odd O/P=1(Moore)

2 = propagation delay of O/Plogic unit of Moore M/C

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State Transition Table(Even-Parity Checker)

Even State: 0 ; Odd State: 1; State Variable A

A x A+ y1 y2 DA TA

0 0 0 0 0 0 0

0 1 1 0 1 1 1

1 0 1 1 1 1 0

1 1 0 1 0 0 1

PresentState

InputNextState

MooreO/P

MealyO/P

D-FFExcit.

T-FFExcit.

Input variablesto comb. logic

QFF

N.S. & O/PLogic

CLK

x y2

A DA

Or

FFs

y1

N.S.Logic

O/PLogic

DAAQ

xDA= Ax (same for Mooreand Mealy); TA= x (same for Mooreand Mealy);y1 = A for Moorey2 = Ax for Mealy

Output functions

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State=0Even

State=1Odd

1/11/0

0/1

Reset 0State=0Even

11

0

Reset[0]

State=1Odd [1]

x

FF

N.S.Logic

CLK

Q

Q DD-

Mealy MooreAssume single bit state information stored in a D-FF

CLK

x

D

Q(state)y2

(Mealy O/P)y1 Moore O/P)

State Transition is occurring

State Transition is occurring

S.T. is complete.

S.T. is complete.

oddoddevenevenoddeven

0/0

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Moore M/C Implementation

D Q

QRCLK

y2x=1

A0

a) D-FF

T Q

QR

A y2x

CLK

b) T-FF

Moore O/P is synchronized with clock.

Mealy M/C Implementation

D Q

QRCLK

y1

x=1A

0 1 T Q

QR

x

CLK

y1

a) D-FFb) T-FF

Mealy O/P is not synchronized with clock.

Reset

Reset

Reset

Reset

DA= Ax ; TA= x; y1 = A for Moore; y2 = Ax for Mealy

Note: Here Moore and Mealy state transitionfunction is the same. Will not always be the case.

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Difference Between Mealy and Moore Machine

Mealy Moore (1) O/Ps depend on the present O/Ps depend only on the state and present I/Ps present state(2) The O/P changes asyn Since the O/Ps change -chronously with the when the state changes, enabling clock edge and the state change is synchronous with the enabling clock edge, O/Ps change synchronously with this clock edge(3) A counter is not a Mealy A counter is a Moore machine machine(4) A Mealy machine will have the same # or fewer states than a Moore machine

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Behavioral FSM Descriptions in VHDL – 1st Cutentity fsm1_1 is port (x, reset:in bit; y: out bit:=`0’)end entity fsm1_1architecture behav of fsm1_1 istype states is (even, odd);beginstate_mc: process (x, reset) isvariable curr_state, next_state: states := even;-- initial state is reset statebeginif reset = ‘1’ then curr_state := even; y <= ‘0’;elsecase curr_state iswhen even => y <=`0’; -- assert output-- next determine transition based on input if x=`1’ then next_state := odd; else next_state := even; end if;when odd => y <= `1’; -- assert output if x=`1’ then next_state := even; else next_state := odd; end if;end case;curr_state := next_state;end if;end process state_mc;end architecture behav;

0Even

11

0

Reset[0]

Odd [1]

Moore machine

• Simple very high-level behavioral description w/o timing (no clock, no delays)

• Checks only the high-level FSM logic

• No parallelism• If timing and/or parallelism of

the underlying hardware is desired we need to introduce clocks, delays and multiple processes

FFs

y

N.S.Logic

O/PLogic

Q

x

N.S

.

C.S.

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Behavioral FSM Descriptions in VHDL – 2nd Cutarchitecture behav of fsm1_2 istype states is (even, odd);beginstate_mc: process isvariable curr_state, next_state: states := even; -- reset statebeginwait until (clk’event and clk=`1’) or (reset=`1’);if reset = ‘1’ then curr_state := even; y <= `0’ after 2 ns;else-- note need of curr_state to be variable for immediate effectcase curr_state iswhen even => y <=`0’ after 2 ns; -- assert outputs-- next determine transition based on input if x=`1’ then wait for 2 ns; next_state := odd; else wait for 2 ns; next_state := even; end if;when odd => y <= `1’ after 2 ns; -- assert outputs if x=`1’ then wait for 2 ns; next_state := even; else wait for 2 ns; next_state := odd; end if;end case;curr_state := next_state; end if;end process state_mc;end architecture behav;

entity fsm1_2 is port (x, clk, reset:in bit; y: out bit:=`0’)end entity fsm1_2

0Even

11

0

Reset[0]

Odd [1]

Moore machine

Problem w/ the description: The N.S. logic is simulated only on the clock edge. Actually, it shouldbe simulated anytime x or C.S. changes (note that the latter changes w/ some delay after the clockedge, not @ the clock edge), and this does not happen in the code.

FFs

y

N.S.Logic

O/PLogic

Q

x

N.S

.

C.S.

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Behavioral FSM Descriptions in VHDL – Final CutGeneral solution to behavioral description of a system (described in an arch) – when to have multiple processes: -- If a design has different components, each operating or triggered w/ different timing events, then separate them into individual processes.-- In other words a single process should not describe multiple components triggered by different timing events-- Furthermore if signal assignments to, say, signal X, in a process should affect the rest of the logic in it in the current iteration and X cannot be made a variable (if it is also an o/p of the process, e.g., when it is an i/p signal of another process), separate out the X-dependent logic as a separate process-- In a Moore machine, we have 3 modules, FFs, N.S. logic and O/P logic. FF is triggered by the clock +ve edge. Its o/p C.S. triggers the O/P logic; so it is also ultimately triggered by the clock. The N.S. logic is triggered by C.S. and x, where x has no relation to the clock.-- So a possible breakup is Process 1: FFs + O/P Logic and Process 2: N.S. Logic. But not a good idea as:-- C.S. needs to be a signal i/p to the N.S. Logic and FF processes to communicate -- Since the O/P Logic depends on C.S., if it is in the same process as the FF, there will not be any effect from the FF to the O/P Logic modules in the current iteration (in other words, combined FF+O/P process will need to be simulated more times (i.e., it has to be activated by more events) to propagate final values to o/p of O/P module). So separate out the O/P Logic as a 3rd process-- Large processes resulting from the above partitioning methodology may be further broken up functionally (i.e., by functional modules, e.g., ALU and Register File in a Datapath process of a CPU) and/or if some parallelism of the underlying hardware is desired to be simulated and/or communication between these modules need to be simulated

FFs

y

N.S.Logic

O/PLogic

Q

x

N.S

.

C.S.

Process 2

Process3 Process 1clock

X <= …..

Y <= X nand Z;

Process A

Process B

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Behavioral FSM Descriptions in VHDL – Final Cutarchitecture behav of fsm1_3 istype states is (even, odd);signal next_state, curr_state: states := even;beginns_proc: process (curr_state, x) isbegincase curr_state iswhen even => if x=`1’ then next_state <= odd after 2 ns; else next_state <= even after 2 ns; end if;when odd => if x=`1’ then next_state <= even after 2 ns; else next_state <= odd after 2 ns; end if;end case;end process ns_proc;ff_proc: process isbeginwait until (clk’event and clk=`1’) or (reset=`1’);if reset = ‘1’ then curr_state <= even;else curr_state <= next_state; end if;end process ff_proc;op_proc: process (curr_state) isbegincase curr_state iswhen even => y <=`0’ after 2 ns; -- assert outputswhen odd => y <= `1’ after 2 ns;end case;end process op_proc;end architecture behav;

entity fsm1_3 is port (x, clk, reset:in bit; y: out bit:=`0’)end entity fsm1_3

Process3

FFs

y

N.S.Logic

O/PLogic

Q

x

N.S

.

C.S.

Process 2

Process 1clock

0Even

11

0

Reset[0]

Odd [1]

Moore machine

Note: When all processes block, sim. timeis advanced by at least the fictitious delta time or min. delay across signals when at least one unblocks, resulting in some assigned signal values (w/ the corresponding delay) appearing and causing corresponding processes to unblock (those w/ wait statements dependent on these signals).

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Behavioral FSM Descriptions in VHDL– First Cutarchitecture behav of fsm2_1 istype states is (even, odd);beginstate_mc: process isvariable next_state, curr_state: states := even; -- reset statebeginwait until (clk’event and clk=`1’) or (reset=`1’);if reset = ‘1’ then curr_state := even;else curr_state := next_state; end if;case curr_state iswhen even => if x=`1’ then y <= `1’ after 2 ns; wait for 2 ns; next_state := odd; else y <= `0’ after 2 ns; wait for 2 ns; next_state := even after 2 ns; end if;-- note: above times are arbitrary; just for e.g.when odd => if x=`1’ then y <=`0’ after 2 ns; wait for 2 ns; next_state := even after 2 ns; else y <= `1’ after 2 ns; wait for 2 ns; next_state := odd after 2 ns; end if; end case;end process state_mc;end architecture behav;

entity fsm2_1 is port (x, clk, reset:in bit; y: out bit:=‘0’)end entity fsm2_1

Mealy Machine0/0

Even

Odd

1/11/0

0/1

Reset

Transition Arc

Problem w/ the description: The N.S. & O/P logic is simulated only on the clock edge. Actually, it should be simulated anytime x or C.S. changes. The latter happens but not the former.

QFF

N.S. & O/PLogic

CLK

x y2

C.S. N.S.

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Behavioral FSM Descriptions in VHDL– Final Cutarchitecture behav of fsm2_2 istype states is (even, odd);signal next_state, curr_state: states := even;begin

ns_op_proc: process (x, curr_state) isbegincase curr_state iswhen even => if x=`1’ then y <= `1’ after 2 ns; next_state <= odd after 2 ns; else y <= `0’ after 2 ns; next_state <= even after 2 ns; end if;-- note: above times are arbitrary; just for e.g.when odd => if x=`1’ then y <=`0’ after 2 ns; next_state <= even after 2 ns; else y <= `1’ after 2 ns; next_state <= odd after 2 ns; end if; end case;end process ns_op_proc;

ff_proc: process isbeginwait until (clk’event and clk=`1’) or (reset=`1’);if reset = ‘1’ then curr_state <= even;else curr_state <= next_state; end if;end process ff_proc;end architecture behav;

entity fsm2_2 is port (x, clk, reset:in bit; y: out bit:=‘0’)end entity fsm2_2

Mealy Machine0/0

Even

Odd

1/11/0

0/1

Reset

Transition Arc

QFF

N.S. & O/PLogic

CLK

x y2

C.S. N.S.

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Another example: A simple vending machineHere is how the control is supposed to work. The vending machine delivers

a package of gum after it has received 15 cents in coins. The machine has a single coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor indicates to the control whether a dime or a nickel has been inserted into the coin slot. The controller’s output causes a single package of gum to be released down a chute to the customer.

One further specification: We will design our machine so it does not give change. A customer who pays with two dimes is out 5 cents!

VendingMachine

FSMCLK

Reset (ext.)

CoinSensor

GumReleaseMechanism

Open

Vending Machine block diagram

States: 0C 15C10C5C

Timertime_outOR

Reset

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— The figure below show the Moore and Mealy machine state transition diagrams.

15 cent

10 cent

5 cent

0 cent

Mealy machine

Moore and Mealy machine state diagrams for the vending machine FSM

Reset / 0 N(

Reset / 0

N / 0

D / 0

N / 0

N+D/1

D/1

N 0/D

N 0/D

D Reset)/0

0 cent[0]

5 cent[0]

10 cent[0]

15 cent[1]

Moore machine

N( DReset

Reset

N+D

N

D

N

D

N D

N D

Reset)/0

Reset Reset / 1

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Behavioral VHDl description of Moore vending machine controller

Reset

Mooremachine

0 cent[0]

5 cent[0]

10 cent[0]

15 cent[1]

Reset

N+D

N D

N

D

N D

N D

N( DReset)/0

Reset

ff_proc: process isbeginwait until (clk’event and clk=‘1’) or ( reset=`1’);if reset = ‘1’ then curr_state <= S0 after 1 ns;else curr_state <= next_state after 1 ns; end if;end process ff_proc;op_proc: process (curr_state) isbegincase curr_state iswhen S0 => open1 <=` 0’ after 2 ns; when S5 => open1 <= `0’ after 2 ns; when S10 => open1 <=` 0’ after 2 ns; when S15 => open1 <= `1’ after 2 ns;end case;end process op_proc;

entity vend_moore is port(N, D, ext_reset, clk: in bit; open1:inout bit);end entity vend_moore;architecture behav of vend_moore istype states is (S0, S5, S10, S15);signal next_state, curr_state: states := even;signal reset, time_out : bit := `0’;beginreset <= ext_ reset or time_out after 2 ns; -- concurrent signal assignment statementtimer: process is wait until open1 = `1’;time_out = `1’ after 20 sec;wait for 20 sec;time_out = `0’ after 10 ns; -- timeout signal is high for 10 ns;if open1 = `1’ then wait until open1 = `0’; end process timer;

Timerproc

o/p logicproc

FFproc

NS logicprocessreset <= ext_ reset or

time_out after 2 ns;

next_state

curr

_sta

te

open1

time_out

ND

reset clk

ext_reset

open1

entity vend_moore

Arch. behav

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Behavioral VHDl description of Moore vending machine controller

Reset

Mooremachine

0 cent[0]

5 cent[0]

10 cent[0]

15 cent[1]

Reset

N+D

N D

N

D

N D

N D

N( D Reset)/0

Reset

ns_proc: process (N, D, curr_state) iscase curr_state iswhen S0 =>if N=1 then next_state <= S5 after 2 ns; elsif D=1 next_state <= 10 after 2 ns; else next_state <= S0 after 2 ns; end if;when S5 =>if N=1 then next_state <= S10 after 2 ns; elsif D=1 next_state <= S15 after 2 ns; else next_state <= S5 after 2 ns;end if;when S10 => if N=1 or D=1 then next_state <= S15 after 2 ns; else next_state <= S10 after 2 ns;end if;when S15 =>next_state <= S15 after 2 ns;end case;end process ns_proc;end architecture behav;

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Q1 Q2 D N Q1+ Q2

+ Open Open 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 x x x x 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 1 0 1 1 1 x x x x 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 x x x x 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 x x x x

Present State Inputs Next State Moore Output Mealy Output

Encoded vending machine state transition table. Note: Do not have to designfor the reset input if FFs have a direct reset inputs. Make sure though that reset state isencoded as all 0’s if possible; otherwise need FFS w/ asynch. reset as well as set inputs

Q+ = D

Q Q+ D0 0 00 1 11 0 01 1 1

—State transition table for Moore and Mealy M/C.(Next state also gives D-FF excitation).

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Implementation using D-FFs

00 01 11 10

00

01

11

10

Q1Q0

DN 00 01 11 10

00

01

11

10

Q1Q0

DN 00 01 11 10

00

01

11

10

Q1Q0

DN0 0 1 1

0 1 1 1

x x x x

1 1 1 1

0 1 1 0

1 0 1 1

x x x x

0 1 1 1

0 0 1 0

0 0 1 0

x x x x

0 0 1 0

K-map for D1 K-map for D0K-map for Open (Moore)

D1 = Q1 + D + Q0·NDQNQNQQND 11000

OPEN = Q1·Q0

OPEN = Q1·Q0 + D·Q0 + D·Q1 + N·Q1Moore

Mealy

00 01 11 10

00

01

11

10

Q1Q0

DN0 0 1 0

0 0 1 1

x x x x

0 1 1 1

K-map for Open (Mealy)

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D Q

QR

D Q

QR

Q0

N

N

Q0

Q1

N

Q1

D

D0

D1 Q1

OPEN

D

0Q

NCLK

CLK

Vending machine FSM implementation based on D flip-flops(Moore).

0Q

1Q

Q1

Q0

Similarly,a Mealyimplementation;only the OPENfunction changes.

Reset

Reset

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Implementation using J-K FFS

Q1 Q2 D N Q1+ Q2

+ J1 K1 J0 K0 0 0 0 0 0 0 0 x 0 x 0 1 0 1 0 x 1 x 1 0 1 0 1 x 0 x 1 1 x x x x x x 0 1 0 0 0 1 0 x x 0 0 1 1 0 1 x x 1 1 0 1 1 1 x x 0 1 1 x x x x x x 1 0 0 0 1 0 x 0 0 x 0 1 1 1 x 0 1 x 1 0 1 1 x 0 1 x 1 1 x x x x x x 1 1 0 0 1 1 x 0 x 0 0 1 1 1 x 0 x 0 1 0 1 1 x 0 x 0 1 1 x x x x x x

Remapped next-state functions for the vending machine example.

Q Q+ J K0 0 0 x0 1 1 x1 0 x 11 1 x 0

J-K Excitation

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00 01 11 10

00

01

11

10

Q1Q0

DN

00 01 11 10

00

01

11

10

Q1Q0

DN 00 01 11 10

00

01

11

10

Q1Q0

DN

00 01 11 10

00

01

11

10

Q1Q0

DN0 0 x x

0 1 x x

x x x x

1 1 x x

x x 0 0

x x 0 0

x x x x

x x 0 0

0 x x 0

1 x x 1

x x x x

0 x x 1

x 0 0 x

x 1 0 x

x x x x

x 0 0 x

K-map for J1 K-map for K1

K-map for J0 K-map for K0

K-maps for J-K flip-flop implementation of vending machine.

J1 = D + Q0·N K1 = 0DQNQJ 100

NQK 10

25

J Q

QR

Q1CLK

K

J Q

QR

Q0

CLK

K

OPENN

Q0

D

N

DQ1

N

0Q1Q

0Q1Q

J-K flip-flop implementation for the vending machine example (Moore).

Similarly, a Mealy implementation; only the OPEN function changes.

Reset

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Basic Steps in the FSM Design Procedure

1. Understand the problem and the different information classes (minimal number) required to solve it. Also make sure there are well-defined transitions possible between these classes; otherwise break down some or all classes into smaller classes to get well-defined transitions.

2a. Convert these information classes into distinct states, and determine the state transition diagram of the FSM. Determine reset state.2b Optional: Perform state minimization

3a. Encode states in binary, and obtain state transition table and FF excitation (for desired FF type).3b Optional: Perform state assignment for minimizing logic.

4. Minimize the FF excitation functions and output functions (using K-Maps, for example) and implement the FSM using these FFs and logic gates (or MUXes, PLAs, etc.) that implement the output and FF excitation functions.

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FSM Word Problem 1:

• Design a system that outputs a ‘1’ whenever it receives a multiple of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x.

— Relevant information classes needed to solve the problem: (A) A multiple of 3 # is received. (B) A non-multiple of 3 # is received.

Questions to consider:(1) How do we go from (A)(B)

Ans.: If a ‘1’ is received

(2) How do we go from (B)(A)Ans.: Not clear. Need to split up (B) further into(B1): 3y+1 # of 1’s received.(B2): 3y+2 # of 1’s received. Where y is an integer 0.

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Note: (A): is 3y+0 = 3y # of 1’s received.

• Now the transitions between the3 classes of information is clear:(A) (B1) (B2) (A)

1 received 1 received 1 received

• Hence these classes of information can be considered states of the required as states of the required FSM:

These 3 states can be represented by 3y+I, i = 0,1,2

i=2[0]

i=1[0]

i=0[1]

Reset

1

1

1

0

0

0

Moore Machine

i=0

i=1

i=2

Reset0/1

0/0

0/0

1/0

1/1

00

10

01

Mealy Machine

Input

Output

1/0

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FSM Word Problem 2:

• Design a system that outputs a ‘1’ whenever it receives:(a) A multiple of 3 # of 1’s AND (b) A non-zero even # of 0’s

E.g., ((0,2) , (3,2) , (3,4) , (6,2) ,···)

— Relevant classes of information:- For # of 1’s: 3y+i, i = 0,1,2

[3 classes]- For # of 0’s: 2z+j, j = 0,1

For j = 0, we need to distinguish between zero (z = 0) and non-zero (z > 0) # of 0’s

- Thus we have 3 classes:2z+0, z = 0 ( 0 )2z+0, z > 0 ( non-zero even )2z+1 ( odd )

# of 0’s

# of 1’s

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The relevant # of 1’s can be represented by i = { 0, 1, 2 }( # of 1’s = 3y+i )— The relevant # of 0’s can be represented by j= { 00 , 0>0 , 1 }( # of 0’s = 2z+j ) where the subscript of the 0 indicates whether z=0 or z>0.

— Since at any point time, a certain # of 1’s and # of 0’s will havebeen received, the state of the system will be given by a combination of relevant # of 1’s and # of 0’s.

— There are 9 combinations:

{ 0, 1, 2, } X { 00, 0>0, 1 } = (0,00), (0,0>0), (0,1), (1,00), (1,0>0), (1,1), (2,00), (2,0>0), (2,1)

# of 1’s # of 0’s

CartesianProduct

31

(0,00)

(1,00)(0,0>0)

(2,00)

(2,1)

(1,1)(0,1)

(2,0>0)

(1,0>0)

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(0,00)

(1,00) (0,0>0)

(2,00)

(2,1)

(1,1)(0,1)

(2,0>0)

(1,0>0)

ResetNote: 0>0 2z+j, j = 0

z > 0

1/0

1/0

0/0 1/0

0/0

0/0

0/0

0/0

0/0

0/1

1/0

1/0

0/0

0/0

1/0

1/0

1/1

1/0