ece 3450 m. a. jupina, vu, 2014 metal-oxide-semiconductor field-effect transistor digital logic...

ECE 3450 M. A. Jupina, VU, 2014

Metal-Oxide-Semiconductor Field-Effect Transistor

Digital Logic Technology

CMOS Fabrication MOS Device Structure and Operation NMOS Circuits CMOS Circuits The Future of CMOS Technology BiCMOS Circuits

Some Key Lecture Objectives A basic understanding of the layout and structure of MOS

devices and circuits A basic understanding of the electrical operation of MOSFETs How logic functions can be synthesized in CMOS and why

CMOS is the dominate digital technology today A more fundamental understanding of power dissipation and

propagation delay in CMOS technologies The future of CMOS technology (FinFETs and TFETs) When should BiCMOS technology be used and why

Reference:Fundamentals of Digital Logic, Chapter 3 and references at course website.


CMOS Fabrication Processes

IC built on silicon substrate:– some structures diffused into substrate;

– other structures built on top of substrate.

Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped)

Wires made of polycrystalline silicon (poly), multiple layers of aluminum/copper (metal).

Silicon dioxide (SiO2) is an insulator.


Simple Cross Section of a MOS Integrated Circuit

substraten+ n+p

substrate

metal1

poly

SiO2

metal2

metal3

transistorvia


Example: Cross Section of Intel 0.25 Micron Process


CMOS Fabrication Processing Steps

First place tubs or wells to provide properly-doped substrate for nmos and pmos transistors:

p-tub n-tub

substrate


Processing Steps, Cont’d.

Pattern polysilicon before diffusion regions:

p-tub n-tub

poly polygate oxide


Processing Steps, Cont’d

Add diffusions (self-aligned source and drain)

p-tub n-tub

poly poly

n+n+ p+ p+



Start adding metal layers:

p-tub n-tub

poly poly

n+n+ p+ p+

metal 1 metal 1

vias



Add other metal interconnect layers:

p-tub n-tub

poly poly

n+n+ p+ p+

metal 1 metal 1

vias

metal 2


MOS Transistor Layout

NMOS FET: PMOS FET:

w

L

w

L


NMOS Transistor Structure

nmos transistor:


+

(a) Small transistor

L

W 1

L

W 2

(b) Larger transistor

Transistor Sizes


++++++++++ ++++++ +++ ++++++++++++ ++++++ ++++++

+++++++++ +++++++++ +++++++++++ +++++++++++

Drain (type n)Source (type n)

Substrate (type p)

SiO 2

When V GS < VT, the transistor is off

V S

0 V =

V G

0 V =

V D

++++++

++++++++++++++++++

0DI

NMOS Transistor When Turned Off


++++++++++ +++ ++++++++++++ ++++++

+++++++++ +++++++++++++++++++++ +++++++++++++++++

Channel (type n)

SiO 2

V DD

When V GS > VT, the transistor is on

+++++++++

V D

V G 5 V =

V S 0 V =

0DI

NMOS Transistor When Turned On


Drain Source

in = "low" in = "high"

(a) A simple switch controlled by the input

V D V S

(b) NMOS transistor

Gate

(c) Simplified symbol for an NMOS transistor

V G

Substrate (Body)

NMOS Transistor as a Switch


Gate

in = "high" in = "low"

(a) A switch with the opposite behavior

V G

V D V S

(b) PMOS transistor

(c) Simplified symbol for an PMOS transistor

V DD

Drain Source

Substrate (Body)

PMOS Transistor as a Switch


(a) NMOS transistor

V G

V D

V S = 0 V

V S = V DD

V D

V G

Closed switch whenV G =V DD

V D = 0 V

Open switch whenV G = 0 V

V D

Open switch whenV G =V DD

V D

V DD

Closed switch whenV G = 0 V

V D =V DD

V DD

(b) PMOS transistor

NMOS and PMOS Transistors in Logic Circuits


0

Linear or

Triode

V DS

Saturation

I D

V GS V T > ID,SAT

The Current-Voltage Relationship of a NMOS Transistor

VDS,SAT = VGS - VT


NMOS Drain Current Characteristics

Sub-Threshold (ID=0)


Drain Current Equations

For VGS > VT,

Linear region (VDS < VGS - VT)

Saturation region (VDS >= VGS - VT)

For VGS < VT, ID = 0 (Sub-Threshold region)

21D GS T DS DS2I = k (W/L)[(V - V )V - V ]

21D GS T2I = k (W/L) (V - V )


NMOS and PMOS I-V Characteristics


(b) Simplified circuit diagram

V x

V f

V DD

x f

(c) Graphical symbols

x f

R

V x

V f

R +

-

(a) Circuit diagram

5 V

An Inverter (NOT gate) Circuit for NMOS Technology


V DD

(b) V x = VDD=5V

I stat

R

R DS

V f V OL=

(a) NMOS NOT gate

V f

V DD

V x

Voltage Levels in an NMOS Inverter

212

stat

For 5V

1' range

I

GS X DD

DS DSDS

D n GS T DS DS n GS T

fDS DDf OL DD

DS DS DS

V V V

V VR K s

W WI k V V V V k V VL LVR V

V V VR R R R R

-1/RVOL VOH=VDD

Load Line Analysis

V DD

(c) V x = 0

R

R DS

V f V OH=

Istat


~

V f

V DD

(a) Circuit


(b) Truth table

f f

0 0 1 1

0 1 0 1

1 1 1 0

x 1 x 2 f

V x 2

V x 1

x 1

x 2

x 1

x 2

NMOS Realization of a NAND Gate


V x 1 V x 2

V f

V DD

(a) Circuit


(b) Truth table

f

0

0

1

1

0

1

0

1

1

0

0

0

x 1 x 2 f

f x 1

x 2

x 1

x 2

NMOS Realization of a NOR Gate


V f

V DD

Pull-down network

V x 1

V x n

(PDN)

Structure of an NMOS Circuit


Open Collector Examples

High Current External Loads

Wire-Anding

Open Drain logic devices are also available in MOS technologies.


Static Complementary CMOS Circuits

high noise margins - full rail to rail swing (VOH and VOL are at VDD and GND, respectively)

low output impedance, high input impedance no steady state path between VDD and GND (no static

power consumption) delay is a function of load capacitance and transistor

resistance comparable propagation delay times (under the

appropriate transistor sizing conditions) logic levels not dependent upon the relative device

sizes; ratioless


Static Complementary Gate Structure

pullupnetwork

pulldownnetwork

VDD

VSS

outinin out

+

Drain


Switch Models of CMOS Inverter

VDD

Rn

Vout = 0

Vin = V DD

VDD

Rp

Vout = VDD

Vin = 0


VDD

Vf

Vx

IDVx

Vf

ID

(a) Current flow when input Vx

changes from 0 V to 5 V

(b) Current flow when input Vx

changes from 5 V to 0 V

Dynamic Current Flow in CMOS Circuits



CMOS Power Dissipation

2

1( )

AVER LEAKAGE

TOTAL STATIC DYNAMIC

LEAKAGE DD LOAD DD

I I i t dtT

P P P

I V fC V

IAVER

OFF

ON

Ways to Reduce CMOS Power Dissipation Lower VDD – Hardware steps down supply voltage when system’s activity decreases (DVS)

Reduce Capacitance in logic circuits (minimize the size of transistors)

Lower fCLK – Hardware steps down clock frequency when system’s activity decreases (DFS)

Use Gated-Clock Circuits to power-off logic circuits when not being used

Clock

Clock

DisableSignal

Gatedclock

Can insert clock gating at multiple levels in clock treeCan shut off entire subtree if all gating conditions are satisfied


CMOS Propagation Delay

, ,

GS in DD DS out DD

GS

212

in DD DS out DD

1, 2

212

saturatio

2

at t = 0 V =V =V , V =V =V ( )

at t = V =V =V linear

2

, V =V =V / 2 (

n

)

2

DDpHL

D AVG D AVG

pHL

D A DDDD T DD DV n D TG V V V V

C

V V

V CVt

I I

t

WI k L

2.43 1.7 2.43

Also, 0.69 thus Similarly, and pHL n n pLH p

n DD p DD p DD

Ct R C R t R

W W Wk V k V k VL L L

OFF

ON

tpHL tpHL

tpLH

21

T DD , DD5

1.7Assuming V = V , 0.298 V thus D AVG n pHL

n DD

CWI k tL Wk VL


Examples of MOSFET Electrical Parameters

L 1 m 0.25 m

VDD (V) 5 2.5

kn’(A/V2) 120 115

VTn (V) 0.8 0.43

kp’(A/V2) 40 30

VTp (V) -0.9 -0.4


CMOS NAND

A

B

A • B

A BA B M1 M2 M3 M4

F

0 0 on on off off 1

0 1 on off off on 1

1 0 off on on off 1

1 1 off off on on 0

A

B

M1

M2

M3

M4

F


CMOS NOR

A + B

A

B

A B

AB

A B M1 M2 M3 M4F

0 0

0 1

1 0

1 1

M1

M2

M3

M4

F

on on off off 1

on off off on 0

off on on off 0

off off on on 0


CMOS Realization of an AND Gate

A

B

F = A • B


Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PUN and PDN are dual logic networks

……

Pull-up network (PUN) and pull-down network (PDN)

PMOS transistors only

pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1

NMOS transistors only

pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0


Construction of PDN NMOS devices in series implement a NAND function

NMOS devices in parallel implement a NOR function

A

B

A • B

A B

A + B


Dual PUN and PDN PUN and PDN are dual networks

DeMorgan’s theorems

a parallel connection of transistors in the PUN corresponds to a series connection of the PDN

Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)

Number of transistors for an N-input logic gate is 2N

A + B = A • B

A • B = A + B


Complex CMOS Gate

D

A

B C

D

A

B

C

OUT = (D+A•(B+C))


V f

V DD

V x 1

V x 2

V x 3

Examples 3.1 and 3.2 in Textbook

V f

V DD

V x 1

V x 2

V x 3

V x 4

1 2 3 1 2 3f x x x x x x 1 2 3 4 1 2 3 4f x x x x x x x x ECE 3450 M. A. Jupina, VU, 2014

F

V DD

A

B

C

D

Given the PUN of a CMOS Circuit, Sketch the PDN.What is Logic Expression for F?

D

C

B

A

F

F = (A+B)•(C+D)ECE 3450 M. A. Jupina, VU, 2014

(a) Circuit

f x

(b) Truth table

Hi-Z x

0 1

f s

s

s

s 0 =

s 1 =

x

x

f = Hi-Z

f = x

(c) Equivalent circuit (d) Graphical symbol

f x

s

s

A Transmission Gate


(b) Graphical symbol(a) Truth table

0 0 1 1

0 1 0 1

0 1 1 0

A B

A

B

f A B =

f A B =

(c) Sum-of-products implementation

f A B =

A

B

Exclusive-OR Gate Example


A

B

F A B =

Exclusive-OR (XOR) Gate Implementation with Transmission Gates

0

on1

off

B

1

off

on0

B


(b) Equivalent circuit

(c) Truth table

x f

e

(a) A tri-state buffer

0 0 1 1

0 1 0 1

Hi-Z Hi-Z 0 1

f e x

x f

e = 0

e = 1x f

f x

e

(d) Implementation

Tri-State Buffer using TGs


x 1

x 2 f

s

A 2-to-1 Multiplexer using TGs


F

A

B

What is the Logic Function of This Circuit?

0

1

on

=B

A B F

0 0

0 1

1 0

1 1off

10

1

0

off

B1

0

XOR F A B

off


Standard Cell Frame Layout of CMOS Circuits

NMOS Transistors

PMOS Transistors


A Simplified Floor Plan of a Standard Cell Design

VDD

GND

BU

SPads

StandardCells

RoutingChannels

forWires


Standard Cell Layout Methodology

Routingchannel

VDD

GND

x x

x x

xx

xx

x

f

f

a

b

a b

x x“Stick Diagram”

Routingchannel


Standard Cell Layout Methodology

Routingchannel

VDD

GND

x x

xx

xx

f a b

D S

G

D S

G

x

S D

G

D S

G

f a

b

D S

G

D S

G

x xx x

Routingchannel


Final Circuit Schematic of the Standard Cell

a

b

f = a • b


Standard Cell Layout of a CMOS Circuit

Microwind CAD Generated Drawing “Stick” Drawing in Power Point


Nanoscale MOS Technology


Power Supply, Threshold Voltage, & Oxide Thickness

Scaling with Channel Length

Reduction


Trends in MOS Device Scaling


Constant Electric Field Scaling Example


The Future (L 10 nm) To improve performance, silicon will be mixed with

a semiconductor like germanium to produce a more spacious, strained crystalline structure that lets electric charge carriers move faster.

To reduce the leakage of current that drives up power consumption, gate oxides will be made of materials with more than eight times the dielectric constant (k) of today’s silicon dioxide.

For better control of the transistor’s on and off states, gates will be of metal, instead of polysilicon.

For better control and (again) to reduce power consumption, gates themselves will be doubled up so that two will do the job a single gate does now.


Higher Mobilities in Strained Si


MOSFETs vs. FinFETs


The FinFET


Multi-Gate FinFETsTriGate

-Gate QuadGate

Double Gate/

FinFET


Multi-Gate FinFETs

FinFETTriGate

-Gate QuadGate

Double-gate/


FinFET Advantages Excellent control of short channel effects in the deep

submicron regime exists and transistors are still scalable. Due to this reason, the small-length transistor can have a larger intrinsic gain (transconductance) compared to MOSFETs.

Much lower off-state current compared to MOSFETs. 22 nm Tri-Gate FinFETs have a 37% performance

increase and a 50% power reduction compared to 22 nm planar MOSFET technology at low voltages (< 1 V).

Allows MOS technology to stay on track with Moore’s Law.


Intel Device Technology


Intel’s Ivy Bridge: 3D ICs with FinFETs and TSVs



After FinFETs, What Is Next?

p-type TFET

A Comparison of ID Versus VG in Various Devices


TFET Advantages

■ Extends silicon-based CMOS technology possibly below 10 nm by enabling a new generation of device topologies while allowing the use of current manufacturing processes.

■ Steep sub-threshold slopes (below 60mV/decade) are possible, and therefore, even less leakage current in the "off" state


BiCMOS BiCMOS stands for Bipolar Complementary Metal-Oxide Semiconductor.

BJTs and MOSFETs are used to construct logic gates.

Additional fabrication steps are required (increased cost).

BiCMOS advantages: Better switching speed than CMOS and lower power consumption than BJT logic circuits.

p

pp

pppp+p+


NPN Bipolar Junction Transistor (BJT): Physical Layout, Circuit Symbol, & Simplified Model


Charge Storage in the Base of a NPN

n(x

)

x

EMITTER BASE COLLECTOR

Cutoff

Forward Active

Saturation

( )BQ n x dx

p

QC t RC

V


Operation of a BiCMOS Inverter


Propagation Delay


tp

CLOADCX

CMOS

BiCMOS

Propagation Delay of BiCMOS and CMOS Gates as a function of CL


Applications of BiCMOS Circuits

BiCMOS (Tri-State) buffers to drive off-chip loads

Data BusOn-Chip Clock Distribution Network

Composed of BiCMOS Inverters


ece 3450 m. a. jupina, vu, 2014 metal-oxide-semiconductor field-effect transistor digital logic...

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