ece 340 electronics i mos applications and biasing
TRANSCRIPT
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ECE 340ELECTRONICS I
MOS
APPLICATIONS AND BIASING
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MOSFET REGIONS OF OPERATION
• CUT OFF
• LINEAR, OHMIC, TRIODE
• SATURATION
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CUT OFF REGION OF OPERATION
0
D
THGSDS
i
Vvv
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LINEAR, OHMIC, TRIODE REGION OF OPERATION
2
2
1DSDSTHGSD
THGSDS
vvVvL
Wki
Vvv
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SATURATION REGION OF OPERATION
2
2
2
10
12
1
THGSD
DSTHGSD
THGSDS
VvL
Wkismall
vVvL
Wki
Vvv
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MOSFET CHARACTERISTICS
vDS
0V 2V 4V 6V 8V 10V 12V
ID
0mA
0.5mA
1.0mA
1.5mA
vGS3
vGS2
vGS1
Linear, Ohmic,Triode ROP
Saturation ROP
Cutoff ROP
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MOSFET BIASING
• SELECTION OF GATE TO SOURCE VOLTAGE
• PRODUCES DC DRAIN TO SOURCE VOLTAGE
• PRODUCES DC DRAIN CURRENT
• DEFINES REGION OF OPERATION
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DC LOAD LINE
• INPUT DC BIAS EQUATION
• OUTPUT DC BIAS EQUATION
• LINEAR EQUATION WITH SLOPE DETERMINED BY EXTERNAL RESISTORS
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MOSFET BIAS CIRCUIT
RD
RS
VDD
VGG
VDS
+
ID
-VGS
+
-
RD
RS
+
-
VDS
VGS
+
-
VDD
VGG
ID
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INPUT EQUATION
• SETS OR SELECTS DC GATE TO SOURCE VOLTAGE
• SETS OR SELECTS DC DRAIN CURRENT
• CONSTRUCTED BY PERFORMING KVL ON INPUT PORTION OF THE CIRCUIT
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KVL INPUT EQUATION
S
GSGGD
SDGGGS
SDGSGG
R
VVI
RIVV
RIVV
0
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OUTPUT EQUATION
• SELECTS OR SETS DC DRAIN TO SOURCE VOLTAGE
• SELECTS OR SETS DC DRAIN CURRENT
• CONSTRUCTED BY PERFORMING KVL ON OUTPUT PORTION OF THE CIRCUIT
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KVL OUTPUT EQUATION
SD
DDDS
SDD
SDDDDDS
SDDSDDDD
RR
VV
RRI
RRIVV
RIVRIV
1
0
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LOAD LINE EQUATION
• USED TO SELECT BIAS PARAMETERS VGS, VDS, AND ID.
SD
DDDS
SDD RR
VV
RRI
1
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vDS
0V 2V 4V 6V 8V 10V 12V
ID
0mA
0.5mA
1.0mA
1.5mA
vGS3
vGS2
vGS1
Linear, Ohmic,Triode ROP
Saturation ROP
Cutoff ROP
LOAD LINE
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BIASING CIRCUITS
• USED TO ESTABLISH
- VGG (GATE VOLTAGE)
- ID (DRAIN CURRENT)
-VDS (DRAIN TO SOURCE VOLTAGE)
• USES ONE OR TWO POWER SUPPLIES
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USING TWO POWER SUPPLIES
RD
RS
VDD
VSS
ID
+VDS
-
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DESIRED BIAS CONDITIONS
mAIVV
VV
VVVV
DDS
GS
SSDD
13
2
55
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SELECTION OF RS
kRmA
VVR
I
VVRVRIV
SS
D
SSGSSSSSDGS
31
52
0
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SELECTION OF RD
kRkmA
VVVR
RI
VVVR
VVVRRI
VRIVRIV
DD
SD
SSDSDDD
SSDSDDSDD
SSSDDSDDDD
431
535
0
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USING ONE POWER SUPPLY
R1 RD
R2 RS
VDD
VGG
-VGS
+
IG = 0
IDIX
+
-
-
VDS
+
R1 RD
R2 RSVGG
-VGS
+
IX
IG = 0
ID
-
+ -
VDS
+
VDD
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DEVELOPMENT OF GATE VOLTAGE
DDGG
XGG
GDD
X
VRR
RV
RIV
IRR
VI
21
2
2
21
0
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INPUT AND OUTPUT EQUATIONS
SD
DDDS
SDD
SDDDDDS
S
GSGGD
D
GSGGS
SDGGGS
RR
VV
RRI
RRIVV
R
VVI
I
VVR
RIVV
1
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DESIRED BIAS CONDITIONS
VVmAI
VV
VVVV
DSD
GG
GSDD
25.0
3
5.15
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SELECTION OF R1 AND R2
egerA
kARkARRR
R
V
V
RR
R
V
VV
RR
RV
DD
GGDDGG
int
35,35
312
21
2
21
2
21
2
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SELECTION OF RS AND RD
kR
kmA
VVRR
I
VVR
kRmA
VVR
I
VVR
D
DSD
DSDDD
SSD
GSGGS
3
35.0
25
35.0
5.13