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22

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24

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4‐bit4‐bit

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This lab is acontrollerdewilladda‘NWest).

6.1 Prela

Think of adduplicatingt

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6.2 Lab r

In the nightalways greereaches(attanothergreegreen‐ambedefault sideswitches(SWFigure16co

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Lab 5 –

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ab

dding the nithehardwar

If day_mo The c Else -- N The c End if ;

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code you de

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in a way thherwords,do

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controller haar on the otheriod),ifnoeen)periodfsides. For thn between stWhentheswofdayandnig

dedtrafficlig


26

ts; Advan

you developeration,let’schowgivespr

hat you emponotimplem

in lab-4

in lab-4 mo

mode fromninbothdaya

as a defaulther side.Whcarisdetectforthedefauhismode, wetates. ThesewitchisON,ight.

ghtlogicare


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ped in lab‐4.callit‘Daymrioritytoone

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night‐modeandnightmo

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de (SW [16] to switch lion‐defaultsierwiseitactsetection sens be implemethepresence

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ed in lab‐4

night-mode

me comes to

) that trafficights (amberde,thesysteslikedaymosors outputentedusingofacaront

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Table 8 – TLC

AssignedCLOCKSW[1SW[1SW[1SW[1LEDGLEDR[LEDGLEDRHEXHEX

S HEXW HEX

yourdesign.

gthecircuitnlyworksatwith your cconditionsars(countsupor is on for

o 0h once tdresetstozeerandtransi


27

LightControlle

C circuit IO defi

dPortK_50 50M17] ‘0’:d16] ‘0’:N15] Car14] Car[8] Gree[11] Red[7] Gree[0] GreeX0 4‐biX2 4‐biX4 4‐biX6 4‐bi

areabyconsnightmode.current lab‐4rerequiredtstarting0h)the same sid

the system eeroineachnitioncounter


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inition

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enters a newnewstate.r.Theyare i

tems

gram

Descriptiondclockht

ensoroutputensoroutputernfornorthnfornorth/sernforeast/ernforeast/atenumberatecounteraitcounterfoaitcounterfo

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dndndssss

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6.3 Simu

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-lab


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ed“Lab5Subelements” a

procedure,oblemsorburcuit (4 pagersandstatented VHDLTECTURE).lationWavedtoshowthntscenarioss)usingnume try to covthisisrelated


angetheVHDulationwave


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28

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Don’tforgettm for demo

ransition consandRTL aMachine Vi

enSegment

the designwred.Alsoyoultsidesanddctionalityshoms at differe

ollowtheinnight‐

esign onafterthe

tofilloutnstrated

nditions,andStateewer. It

design

works asuneedtodifferentouldalsoent time

Name

SW[0]

SW[1]

SW[2]

SW[3]

SW[4]

SW[5]

SW[6]

SW[7]

SW[8]

SW[9]

SW[10]

SW[11]

SW[12]

SW[13]

SW[14]

SW[15]

SW[16]

SW[17]

HEX0[0]

HEX0[1]

HEX0[2]

HEX0[3]

HEX0[4]

HEX0[5]

HEX0[6]

HEX1[0]

HEX1[1]

HEX1[2]

HEX1[3]

HEX1[4]

HEX1[5]

HEX1[6]

HEX2[0]

HEX2[1]

HEX2[2]

HEX2[3]

ECE124

7 Appen

Location

PIN_N25

PIN_N26

PIN_P25

PIN_AE14

PIN_AF14

PIN_AD13

PIN_AC13

PIN_C13

PIN_B13

PIN_A13

PIN_N1

PIN_P1

PIN_P2

PIN_T7

PIN_U3

PIN_U4

PIN_V1

PIN_V2

PIN_AF10

PIN_AB12

PIN_AC12

PIN_AD11

PIN_AE11

PIN_V14

PIN_V13

PIN_V20

PIN_V21

PIN_W21

PIN_Y22

PIN_AA24

PIN_AA23

PIN_AB24

PIN_AB23

PIN_V22

PIN_AC25

PIN_AC26


ndix I – D

Name

HEX2[4]

HEX2[5]

HEX2[6]

HEX3[0]

HEX3[1]

HEX3[2]

HEX3[3]

HEX3[4]

HEX3[5]

HEX3[6]

HEX4[0]

HEX4[1]

HEX4[2]

HEX4[3]

HEX4[4]

HEX4[5]

HEX4[6]

HEX5[0]

HEX5[1]

HEX5[2]

HEX5[3]

HEX5[4]

HEX5[5]

HEX5[6]

HEX6[0]

HEX6[1]

HEX6[2]

HEX6[3]

HEX6[4]

HEX6[5]

HEX6[6]

HEX7[0]

HEX7[1]

HEX7[2]

HEX7[3]

HEX7[4]


29

DE2 pin a

Location

] PIN_AB2

] PIN_AB2

] PIN_Y24

] PIN_Y23

] PIN_AA2

] PIN_AA2

] PIN_Y26

] PIN_Y25

] PIN_U22

] PIN_W24

] PIN_U9

] PIN_U1

] PIN_U2

] PIN_T4

] PIN_R7

] PIN_R6

] PIN_T3

] PIN_T2

] PIN_P6

] PIN_P7

] PIN_T9

] PIN_R5

] PIN_R4

] PIN_R3

] PIN_R2

] PIN_P4

] PIN_P3

] PIN_M2

] PIN_M3

] PIN_M5

] PIN_M4

] PIN_L3

] PIN_L2

] PIN_L9

] PIN_L6

] PIN_L7


assignme

Nam

6 HEX7

5 HEX7

KEY[

KEY[

25 KEY[

26 KEY[

LEDR

LEDR

2 LEDR

4 LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDR

LEDG

LEDG

LEDG

LEDG

LEDG

LEDG

LEDG

LEDG

LEDG

CLOC

CLOC

tems

ent file

me Loc

7[5] PIN

7[6] PIN

0] PIN

1] PIN

2] PIN

3] PIN

R[0] PIN

R[1] PIN

R[2] PIN

R[3] PIN

R[4] PIN

R[5] PIN

R[6] PIN

R[7] PIN

R[8] PIN

R[9] PIN

R[10] PIN

R[11] PIN

R[12] PIN

R[13] PIN

R[14] PIN

R[15] PIN

R[16] PIN

R[17] PIN

G[0] PIN

G[1] PIN

G[2] PIN

G[3] PIN

G[4] PIN

G[5] PIN

G[6] PIN

G[7] PIN

G[8] PIN

CK_27 PIN

CK_50 PIN

cation

_P9

_N9

_G26

_N23

_P23

_W26

_AE23

_AF23

_AB21

_AC22

_AD22

_AD23

_AD21

_AC21

_AA14

_Y13

_AA13

_AC14

_AD15

_AE15

_AF13

_AE13

_AE12

_AD12

_AE22

_AF22

_W19

_V18

_U18

_U17

_AA20

_Y18

_Y12

_D13

_N2

ece 124 lab manual spring 2014

Documents

vh2 lab

lab dix

po5 lab

po4 lab

po6 lab

po3 lab

fielda fpga

design n alysis ming