EC electronic statusS. Ahmad, P. Barrillon, S.Blin, D. Cuisy, S. Dagoret-Campagne, P. Dinaucourt, R. Sliwa, JL. Socha (LAL)

A. Ebersoldt (KIT)

EUSO-Balloon 9th progress meetingNovember 9th 2012 - Napoli

Outline• Reminders• History• EC-front unit status• EC_ASIC status• What next ?

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Reminder: EC-front unit• 3 different PCBs:

• First one (EC DYNODE board) allows to reroute half of the dynodes of 1 MAPMT so that they are aligned perpendicularly to the others. It covers the 4 MAPMTs.

• Second one (EC ANODE board) covers one MAPMT but has dimensions reduced allowing a flex pcb to get out. It is used to collect signal from the anodes and send them to the ASICs.

• Third one (EC HV board) covers one MAPMT. It welcomes the dynodes and supplies the HV to the EC-dynode board which transmits it to the 4 MAPMTs.

Per EC unit:• 1 EC-DYNODE board• 4 EC-ANODE boards• 1 EC-HV boards

UV filter

MAPMTMAPMT MAPMT

Flexible pcb toward EC-back

HV cables toward HV box3

Front view

6 mm outer diameter 3.1 mm inner diameter

this column will be removed in the final version.

Radius of the corner : R2.2

55 mm

Thickness: 1 mm

11 mm6 mm

17 mm

Outer and inner diameters10 and 6 mm

19.62 mm 19.62 mm

53 mm51 mm Thickness: 3 mm

9.3 mm

17 mm

~2 mm

Dimensions of PDM frame (old version)

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EC unit inside PDM frame

• EC_dynode is 54.5 mm x 54.5mm therefore it will lay on the PDM structure where the distance goes from 55 mm to 53 mm• 2 adjacent EC_anodes soldered to the MAPMT pins (going through holes of the EC_dynode) should fit in 53 x 53 mm• The EC_HV soldered to extensions coming from the EC_dynode should fit also in the 53 x 53 mm

MAPMT MAPMT

Ec_dynode

Ec_anode

Ec_HV

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ASIC B ASIC FASIC D

Reminder: EC_ASIC board

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• 6 EC_ASIC board grouped by pairs

• Each board has:

– 3 ASICs, with their associated passive components, on each side of the pcb

– 6 connectors (68 pins: 64 anodes + 4 gnd) on top side

– 1 connector (120 pins) on top side

68

pins

ASIC A

68

pins

ASIC C ASIC E

120 pins

A B C D E F68

pins

68

pins

68

pins

68

pins

Volume for Electronics: EC_asic, HVPS, PDM board

PDM Frame

With EC_front

MAPMT

EC front unit history and status

• First version of the EC front unit boards design was finished in May 2012• Production of the equivalent of one PDM (+ spares) in July 2012 for TA. Few of the

spares were dedicated to EUSO-Balloon prototype.• End of July, mechanical prototype of EUSO-Balloon showed that EC_anodes and

EC_HV were too large to fit in the mechanical frame• EC_anodes were modified by removing lateral parts of the pcb with no routing,

end of July• EC_HV were modified by reducing its dimensions, in September• Before receiving the electrical prototype, it was discovered that the connectors of

the EC_anodes would be on the wrong side of the pcb in the current possible assembly and design of the pcbs.

• The simplest way to cure this problem was found to be a rotation of the MAPMT print by 90° on the pcb. This implicates the re-production of all ec_anodes (straight and curved). The modifications have been applied these last days.

• Nonetheless the EC_anodes in their first version are usable to test prototype electrical functionalities. It will be done with the electrical prototype in the coming weeks.

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Problem spotted

The connectors of a pair of EC_anodes (straight and curved) have to face each other to be plugged to 2 different EC_ASIC boards like the drawing on the right.

In the current version of the EC_anodes… it is the inverse !

Should beReally is like that 8

6 mm

21.7 mm 21.1 mm

48.8 mm

Third version of the EC_anodes and EC_HVAction:EC_anodes were corrected end of October/beginning of November

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Before Now

EC-front unit Electrical prototype

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EC_ASIC history and status• First version of the EC_ASIC board design was finished in beginning of July 2012• Production of the equivalent of one PDM (+ spares) in July 2012 under the supervision of

KIT (A.E), 2 boards are used for EUSO-Balloon electrical prototype.• The cabling of 2 boards was performed in September at KIT with ASICs packaged by MATRA

in CQFP160 package.• The boards were received early October at LAL for tests with a dedicated test board.• At first all ASICs were found dead. After investigations (MATRA-LAL-KIT), it was found that

the problem is due to non-steaming of the packaged ASICs and use of lead-free soldering paste (meaning high temperature cycle). For safety TA and EUSO-Balloon EC_ASIC boards shall be soldered with lead soldering paste in the future (meaning lower temperature cycle)

• Simple tests have been performed so far• Checking ASICs integrity OK• Checking power consumption OK• Checking ASICs configuration (slow control and probes) OK• Checking pedestal levels (FSU,PA, VFS) OK • Checking DAC linearity (threshold setting) OK

• The firmware still needs some times to be finished for the data acquisition part. It should be ready beginning of next week.

• Software is pending, everything has been developed but small modifications will be needed with respect to the firmware.

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EC_asic boardTOP VIEW

A C E

F D B

BOTTOM VIEW

1 connector: HIROSE FX2-120P-1.27DS• 120 pins• Header• Right angle type• Through hole

6 connectors: HIROSE FX2CA-68S-1.27DSA• 68 pins (64 analog signals + 4 gnd)

• Receptacle

• Straight type

• Through hole

6 asics SPACIROC1• Packaging: CQFP 160 pins

• 3 on each side

115 mm

159 mm12

TEST-EC-ASIC

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120 pins

FPGACyclone III USB

AVDD:3V regulator

VH: 1.5V regulator

3.3V regulator

1.2V regulator

DVDD:3V regulator

2.5V regulator

5V+gnd power supply

connector

• Main elements:– 120 pins connector to plug the EC_ASIC– Cyclone III FPGA– USB protocole to communicate with labview running PC

TEST-EC-ASIC top view

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120

pin

conn

ecto

r

FPGA

USB

Pow

er su

pply

con

nect

orregulators

FPGA programmer connectors

40Mhz oscillator

Lemo connector

Connection EC_ASIC and TEST_EC_ASIC

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TEST_EC-ASICEC-ASIC

Pow

er

supp

ly

conn

ecto

rregulators

FPGA programmer connectors

40Mhz oscillator

Lemo connectors

120

pin

conn

ecto

r

USB

PA pedestals

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Similar for TA board

Small dispersion

FSU pedestals

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Small dispersion

Similar for TA board

VFS pedestals

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Small dispersion

Similar for TA board

DAC_FS linearity

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Good linearity

Conclusion on EC_ASIC

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At first order it looks to work nicely:• All ASICs alive• We can talk to them and be understood (slow

control and probe)• This means the daisy chain from first ASIC to

last one works fine

Next steps

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• EC front unit:• Electrical prototype for EUSO-Balloon was received the 7th of November. It will

be powered and analog signals and consumption will be checked• Depending on the results, EC_dynode will be kept unchanged• EC_anodes will be produced in their third version with no further modifications• EC_HV will be kept unchanged or reproduced in their last version with reduced

dimensions

• EC_ASIC:• November will be dedicated to intensive tests of TA and EUSO-Balloon boards

(for cross-check) at first without EC front unit, then with it.• Interface tests with PDM board should be carried out as soon as possible

(reasonably beginning of december)

BACK-UP SLIDES

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EUSO Balloon EC_ASIC issues

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• No power consumption:– Probably all bonding wires were broken in the 6 asics

• Diodes on the pad weren’t seen• No connection between two pins connected inside the asic (example vdd! pin 120 and pin79)

30s

1min30s

2min30s

3min30s

4min30s

5min30s

6min30s25

50

75

100

125

150

175

200

225

Tem

pera

ture

on

the

asic

(°C)

• Soldering temperature cycle at LAL Steaming (80°C, more than 10 hours) Oven: 4 temperature steps

With lead: 180,200,221,250°C

• ASIC n°174: steaming + two soldering cyclesÞ Asic OK

• ASIC n°138: no steaming + one soldering cycleÞ Asic HS: no bonding

Þ It looks like steaming is mandatory (MATRA agrees) and we probably should go to soldering paste with lead

EC_ASIC routing constraints

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• Asic inputs:– Group by 8 consecutive anodes according to the pattern 4 by 2– No crossing between wires for consecutive layers

• Outputs:– Only two routing wires between two connector pins in order to keep a good

isolation • More than one layer for the outputs routing

– No crossing between inputs and data outputs

• LVDS signals– Pay attention to the 40MHz clock

• Be careful to power supply planes to minimize the noise spread– Choice to have two layers for gnd and avdd

• Maximum isolation on critical signals

Configuration of the EC_ASICEach ASIC is configured via 898 bits of slow control and 265 bits for the probe set-up. The 6 ASICs of the EC_ASIC are configured in a daisy chain mode, meaning that respectively 5388 and 1590 bits are sent for the slow control and the probes. This daisy chain is done through the signals sr_in and sr_out, the sr_out of one ASIC being the sr_in of the following ones like described in the figure bellow.

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