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ARITHMETICLOGIC UNIT (ALU)

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The ALU is the part of the computer that actuallyperforms arithmetic and logical operations ondata. All of the other elements of the computersystem-control unit, registers, memory, I/O are

there mainly to bring data into the ALU for it toprocess and then to take the results back out.

An ALU and, indeed, all electronic components inthe computer are based on the use of simple

digital logic devices that can store binary digitsand perform simple Boolean logic operations.

OBE TECHNIQUE: GALLERY WALK

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Representation of integers - sign-magnitude,ones complement, twos complement.

Sign magnitude rep. - rep., drawbacks

2s complement rep.- characteristics,examples, geometric depiction,adv.,specialcases, use of value-box for conversion, signextension

Arithmetic with 2s complement numbers-Addition/Subtraction/Multiplication/Division

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Computer do not store numbers or letters

Computers store bit sequences

The bit sequences can be interpreted asrepresenting integers or floating point numbers

Arithmetic is accomplished by the directhardware implementation of the arithmeticalgorithms.

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Does the calculations Everything else in the computer is there to

service this unit

Handles integers May handle floating point (real) numbers

May be separate Floating Point Unit (mathsco-processor)

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Only have 0 & 1 to represent everything 8 bits word could be used to represent the non-negative

numbers from 0 to 255.

Positive numbers stored in binary

e.g. 41=00101001

No minus sign and No period (radix point) for computerstorage and processing

General - n-bit sequence: an-1 an-2 ..a1a0 is interpreted asunsigned integer A, then

n-1

A = 2i

ai i=0

Representation of negative integers - Sign-Magnitude, onescomplement, Twos complement, Biased

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Left most bit is sign bit 0 means positive 1 means negative +24 = 00011000

-24 = 10011000 n-2 A = 2i ai , if an-1=0 i=0 General case A = n-2 A = - 2i ai , if an-1 = 1

i=0 The rule for forming the negation of an integer is

invert the sign bit.

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For taking n-bit integer and store in m bits,m>n

For signmagnitude, move the sign bit tothe new left-most position and fill in withzeros.

+18 = 0001 0010 (signmagnitude,8bits)

+18=0000 0000 0001 0010 (16 bits) -18= 1001 0010 (8 bits)

-18=1000 0000 0001 0010 (16 bits)

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Adders: Logical gates to add two numbers

We need to use a circuit

with more than oneoutput, which clearly

more powerful than a

Boolean expression.

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Consider adding two 1-bit binary numbers xand y

0+0 = 0

0+1 = 1

1+0 = 1

1+1 = 10

Carry is xAND y

Sum is xXORy

The circuit to compute this is called a halfadder

x y Carry Sum

0 0 0 0

0 1 0 1

1 0 0 11 1 1 0

Half adder implementedusing XOR and AND gates

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x y s c

1 1 0 1

1 0 1 0

0 1 1 0

0 0 0 0Half adder implemented using OR, AND andNOT gates

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HAX

Y

S

C

HAX

Y

S

C

x

y

c

c

s

x 1 1 1 1 0 0 0 0

y 1 1 0 0 1 1 0 0

c 1 0 1 0 1 0 1 0

s (sum) 1 0 0 1 0 1 1 0

c (carry) 1 1 1 0 1 0 0 0

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The full circuitry of the full adder

14

x

y

s

c

c

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Just chain one half adder and full adders together,e.g., to add x=x3x2x1x0and y=y3y2y1y0we need:

15

HAX

Y

S

C

FAC

Y

X

S

C

FAC

Y

X

S

C

FAC

Y

X

S

C

x1y1

x2y2x3y3

x0

y0

s0

s1

s2

s3c

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A half adder has 4 logic gates A full adder has two half adders plus a OR gate

Total of 9 logic gates

To add nbit binary numbers, you need 1 HA and

n-1 FAs To add 32 bit binary numbers, you need 1 HA and

31 FAs Total of 4+9*31 = 283 logic gates

To add 64 bit binary numbers, you need 1 HA and

63 FAs Total of 4+9*63 = 571 logic gates

16

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An n-bit adder may be constructed bycascading n 1-bit address. Sum will bedelayed with respect to CARRY. In the case ofan n-bit parallel adder, the carry delay.Parallel adders are digital circuits that

compute the addition of variable binarystrings of equivalent or different size inparallel.

Parallel Adder block diagram

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Introduction

Shift registers are a type of sequential logiccircuit, mainly for storage of digital data. Theyare a group of flip-flops connected in a chain

so that the output from one flip-flop becomesthe input of the next flip-flop.Most of the registers possess no characteristic

internal sequence of states. All flip-flop isdriven by a common clock, and all are set orreset simultaneously.

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Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike combinational logic isnot only affected by the present inputs, but also, by the prior history. In other words, sequential logic

remembers past events. Shift registers produce a discrete delay of a digital signal or waveform. A waveform synchronized to a

clock, a repeating square wave, is delayed by "n"discrete clock times, where "n"is the number of shiftregister stages. Thus, a four stage shift register delays "data in" by four clocks to "data out". The stagesin a shift register are delay stages, typically type "D"Flip-Flops or type "JK"Flip-flops.

Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert paralleldata to serial form. Serial data communications replaces many slow parallel data wires with a singleserial high speed circuit.

Serial data over shorter distances of tens of centimeters, uses shift registers to get data into and out ofmicroprocessors. Numerous peripherals, including analog to digital converters, digital to analogconverters, display drivers, and memory, use shift registers to reduce the amount of wiring in circuitboards.

Some specialized counter circuits actually use shift registers to generate repeating waveforms. Longershift registers, with the help of feedback generate patterns so long that they look like random noise,

pseudo-noise.

Basic shift registers are classified by structure according to the following types:

Serial-in/serial-out

Parallel-in/serial-out

Serial-in/parallel-out Universal parallel-in/parallel-out

Ring counter

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Serial-in, serial-out shift registers delay

data by one clock time for each stage.

They will store a bit of data for each

register. A serial-in, serial-out shift register

may be one to 64 bits in length, longer if

registers or packages are cascaded.

Serial in/serial Out shift register using type

D flip-flop

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A serial-in/parallel-out shift register is

similar to the serial-in/ serial-out shift

register in that it shifts data into internalstorage elements and shifts data out at the

serial-out, data-out, pin. It is different in that

it makes all the internal stages available as

outputs. Therefore, a serial-in/parallel-out

shift register converts data from serial

format to parallel format. If four data bits

are shifted in by four clock pulses via a

single wire at data-in, below, the data

becomes available simultaneously on thefour Outputs QAto QDafter the fourth clock

pulse.

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The purpose of the parallel-in/parallel-out shift register is to take inparallel data, shift it, then output it asshown below. A universal shift registeris a do-everything device in addition tothe parallel-in/ parallel-out function.

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The 74HC195 can be used for parallel in/parallelout operation, serial in/serial out and serialin/parallel out operations. Q3 is the outputwhen it is used for parallel in/serial out

operation.

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FUNCTIONAL DESCRIPTION

The Logic Diagram and Truth Table indicate thefunctional characteristics of the LS195A 4-Bit ShiftRegister. The device is useful in a wide variety ofshifting, counting and storage applications. It performsserial, parallel, serial to parallel, or parallel to serialdata transfers at very high speeds.

The LS195A has two primary modes of operation, shiftright (Q0 " Q1) and parallel load which are controlled bythe state of the Parallel Enable (PE) input. When the PEinput is HIGH, serial data enters the first flip-flop Q0via the J and K inputs and is shifted one bit in thedirection Q0 " Q1 " Q2 "Q3 following each LOW to HIGHclock transition. The JK inputs provide the flexibility of

the JK type input for special applications, and thesimple D type input for general applications by tyingthe two pins together.

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When the PE input is LOW, the LS195A appearsas four common clocked D flip-flops. The data on the parallel

inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,Q2, Q3 outputs following the LOW to HIGH clock transition.Shift left operations (Q3 "Q2) can be achieved by tying the QnOutputs to the Pn1 inputs and holding the PE input LOW.

All serial and parallel data transfers are synchronous,

occurring after each LOW to HIGH clock transition. Since theLS195A utilizes edge-triggering, there is no restriction on theactivity of the J, K, Pn and PE inputs for logic operation except for the set-up and release time requirements.A LOW on the asynchronous Master Reset (MR) input setsall Q outputs LOW, independent of any other input condition.

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THREE logical operations in ALU : AND, OR andNOT. The truth table of the three logics operationrespectively shown below.

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Multiplexer(Mux) A combinational circuit that receives binary information from one of 2ninput data

lines and directs it to a single output line A 2n-to 1 multiplexer has 2ninput data linesand

n input selection lines(Data Selector) 4-to-1 multiplexer Diagram : Fig. 2-4 4-to-1 multiplexer Function Table : Tab. 2-3

Quadruple 2-to-1 Multiplexer Quadruple 2-to-1 Multiplexer : F ig. 2-5 Select Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

I

0

I

1

I

2

I

3

S0

S1

Y

Tab. 2-3 Function Table for

4-to-1 line Multiplexter

Fig. 2-4 4-to-1 Line Multiplexer

Select Output

E S Y

0 0 All 0's

1 0 A

1 1 B

Quadruple

2 x 1Mux

A

0

A

1

A

2

A

3

B

0

B

1

B

2

B

3

Y

0

Y

1

Y

2

Y

3

Enable

Select

Fig. 2-5 Quadruple 2-to-1

line Multiplexter

a) Function Table b) Block Diagram

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You can make even larger multiplexers, following the same pattern. A 2n-to-1 multiplexer routes one of 2n input lines to the output line. There are 2n data inputs, so there must also be n select inputs.

The output is a single bit. Here is an 8-to-1 multiplexer, probably the biggest well see in this

class.

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Two multiplexers in single IC at gate level

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