dynamic switching test technology for igbt chip under high power … · 2017. 3. 26. · 7 june...

7 June 2005 Y.Masuma 1

Y. Y. MasumaMasumaA.Yoshida, K.Yamada, S. SumiE-mail: [email protected]

Fuji Electric Device Technology Co., Ltd.

South West Test Workshop-2005

Dynamic Switching Test Technology Dynamic Switching Test Technology for IGBT Chipfor IGBT Chip

Under Under High Power Operating ConditionHigh Power Operating Condition


Contents

1. Introduction

2. Dynamic Switching Test

3. The Key Technology of This Development

3.1 Probe mark depth control under Wire Diffusion Bonding Depth(WDBD).

3.2 To overcome trade-off between Probe mark depth & Contact resistance(CRES).

3.3 The design　criteria for Probe Assembly

4.The Design Criteria Verification

5. Conclusion


1.Introduction

IGBT Module

IGBT Chip

IGBT Chip

IGBT Chip

FWD

FWD

FWD 6 in 1 Package Module

450A 1.7kV

Applications: Inverter

NC Machine Tools

Industrial Robots

High Speed Elevator


1.Introduction

Market Trend of IGBT Module

0.0

200.0

400.0

600.0

800.0

1,000.0

1,200.0

Y゜02 Y゜03 Y゜04 Y゜05 Y゜0６ Y゜07

Mar

ket S

ize(

Milli

on U

S$)

EV

New Energy Gen.

Power Supply

UPS

Traction

Pacage Air-Con

Elevator

Robotics/Motion

AC Drive

Washing Machine

Refrigerator

Room Air-Con


Power Loss Improvement

1.Introduction: IGBT Development Focus

1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.40

2

4

6

8

10

12Tj=125oCVcc=600VIc =50ARg = recommend valueVge=+/-15V

Vce(sat) (V)

Turn

Off

Loss

(mJ

/ Pul

se)

Planer PT-IGBT

Planer NPT-IGBTTrench FS-IGBT

1200V / 50A DeviceThe focus of IGBT development used to be minimizing of Vce(sat) and Turn Off Loss to reduce power consumption.


Planer PT-IGBT Planer NPT-IGBT Trench FS-IGBT

1.Introduction: How to improve the power loss

ＥｍｉｔｔｅｒＧａｔｅ

p+-collector

n+-buffer

n--base

350u

m 180u

m


p-collector

n--base


n+-buffer140u

m

n--base

p-collector

Thinner

　　　Current Density ×2.3

Approx. 100A/cm2 in rating ‘88 ‘90 ‘92 ‘94 ‘96 ‘98 ‘00 ‘02 ‘04 ‘06(Year）

1.0

1.5

2.0

3.0

4.0

2.5

3.5

Vce(

sat)(

V) (@

125℃

） SmallerAND


2.Dynamic Switching Test


Process Flow

Solution for saving the Earth

2.Dynamic Switching Test

Wafer process & Test

ShippingPass

Reject Disposition

Module assembly process

Module assembly

Dynamic Switching Test By Module Costly!

Wafer process & Test

Module assembly process

Dynamic Switching Test by Chip

Disposition

Pass

Reject

Shipping

Cost saving & environment

friendly


2.Dynamic Switching Test : Current densityDynamic Switching Test by Module

Ic(rating)×2

IGBT Module

Dynamic Test Circuit (For 2 in 1 IGBT Module)

Regulation of RBSOARBSOA for 600V Device

0

1X

2X

3X

4X

5X

0 200 400 600 800

Rated Vce(V)

Mag

nific

atio

ns

to R

atin

g

Curr

ent,Ic

(A)

Guarantied Icx2Safety Operation Area

RBSOA=Reverse

BiasSafetyOperationArea

Dynamic Switching Test by ChipIc is rating×2　 approx. 200A/cm2 !

No Way!

Too High!


3.The Key Technology of This Development

1) Development Theme:

The Realization of the Dynamic Switching Test for IGBT Chip

2) Technical Issue：

　 The Contact Technology under High Current(200A/cm2)

3) The Key Technology of This Development ：

3.1 Probe mark depth control under WDBD.

3.2 To overcome trade-off between Probe mark depth & CRES

3.3 The design　criteria for Probe Assembly:current distribution in Probe Assembly & maximum current per probe


3.1 Probe mark depth control under WDBD

Shallow Probe Mark Depth

High & Instability CRES RegionTrade Off

Probe mark depth( ) is proportional to Hertz pressure(P0)

　　

R：Probe Tip Curvature(um)、W：Load（gf）E*：Elastic Modulus

31

2

31

23

2*

0 .6

=

=∝

RWconst

RWEP

πδ

Hertz pressure controls Probe mark depth( ) under WDBD

δR

W

Electrode on ChipP0

δ

δ

0

WDBD

0 0.05 0.1 0.15 0.2 0.25 0.3

Pro

be m

ark

dept

h（um

）

0

0 Hertz Pressure(Pa)

CR

ES

（Ω

）

Under WDBD region

High & Instability region

σ3+

σ3−


Cracks on 80nm carbon film（SEM-Image）（Ando et al. IEICE‘96）

Cracks

ProbeOxide Film

Electrode on Chip

Load

　　　　　　

　　 Electrode

Current


Minimization of CRES:

Probe touching down on chip makes nano-cracks

Joule heat enlarges nano-cracks.

CRES decrease

nano- Spot welding

BB--Fritting PhenomenaFritting Phenomena


Fritting phenomena（B-Fritting）

Based on the law of Widemann-Franz-Lorenz

θσκ

⋅= L

[ ]21

20

2 )(4 θθ −= LVc

2

KV

κ：Thermal Conductivity 、σ=1/ρ：Electrical Conductivity、L：Lorenz-Number（2.45E-8　　　）、θ：Temp. at contact point

According to this relationship between thermal and electrical conductivity, the voltage drop(Vc) at actual contact point is expressed (on steady state) ;

[ ]I

LIVcCRES

21

20

2 )(4 θθ −==

CRES is,

Fritting phenomena


Effect of Fritting phenomena

Theory = 0.26/I

0

0 Current per probe(A/probe)

CR

ES

（Ω

） P0= Low

Middle

High

CRES decrease with

Fritting phenomena

In low Hertz pressure region, Fritting phenomena realized.


Non Fritting and after Fritting probe mark


Non Fritting After Fritting

(High CRES) (Lower CRES)

Fritting-Mark

Cross section

Fritting Phenomena Occurred



Low CRES is realized by Fritting phenomena under WDBD region (low Hertz pressure region).

0

0 Hertz Pressure（Pa）

CR

ES

（Ω

）

CRESdecreases

Before Frittng

AfterFrittng

Under Wire Diffusion Bonding Depth

CRES　after Fritting;

Ave.+3σ=Const. (Design parameter)

0.01 0.1 1.01

.1

1

51020305070809095

99

99.9

99.99

Normal Probability Plot of CRES

CRES(arbitrary unit）

Fre

quency(

%)

CRES is Normal distribution


3.3 The design criteria for Probe Assembly

1) Current distribution in Probe Assembly

2) Maximum current per probe


0%

10%

20%

30%

0 0.5 1 1.5 2

Normalized Current

Fre

quency

(%)

σ

　Ave-3σ　　　　　　　　　　　　　　　　　　　Ave+3σ

Current tolerance

=Ave±3σ

（Average）


1) Current distribution in Probe Assembly

CRES distribution after Fritting is normal distribution

Current distribution obeys CRES distribution(assumption)

Current tolerance(in normalized)=Ave.±3σ

Normalized Ave.=1 & σ


2) Maximum current per probe is derived by the numerical analysis of un-steady state heat transfer


Model

Electrode(Al-Si):<933K

Si(Chip Material)

CRES:Heat Generated

Current:Ic

Probe

ρκ

θθ

⋅=

⋅=

+∂∂

=∂∂

p

c

CD

(t)ICRESQ

Qx

Dt

2

2

2

D:Thermal diffusivityθ : Temperature(K)

κ : Thermal Conductivityρ : Mass Density

Cp: Specific Heat at Const. Pressure


2) Maximum current per probe


Load Condition Calculated ResultsMaximum Current per Probe(Under Al-Si Melting Point at 933K）

0

Current（A/Probe）

Cre

s（Ω

）

Turn On Duration30 20 10 5usec

Ex.) Max. current at 20usec

CRES After Fritting


4. The Design Criteria Verification



Ex.) Design for 50A at 600V IGBT chip

Test condition:

Ic= 100A =50A×2(rating ×2)

Turn On Duration = 20usGDU

R L

IGBT Chip

L

ChipSize 6.5mm□

Ic=1

00A

Probe Assembly Design:・The number of probe tolerance　1)Min. ; limited by Max. current 　2)Max. ; limited by chip size

・Design Results：　The number of probes ： Max.　Ave. current　　　：100A / Max.　Current tolerance ： Ave.±3σ　　　　　　　　　　　（Ave. – 3σ～Ave.+3σ)

2obePitchPrChipAreaobeNumberPrMaximum =

0 Min.The Number of Probes

Cur

rent

Per

Pro

be（A

）

Max. current=Ave.+3

Ave. Current

Max. CurrentCriteria

σ


1) Probe Assembly & IGBT Chip 2) Test Waveform


Magnified at Turn Off

Ic=100A Vce=600V

Ic=0A

On Duration=20usec

Turn Off

6.5mm□IGBT Chip

Probe Assembly


Ave. ： 97% of design value　σ ： 68% of design value

Ave.±3σ: In Design Range

Ave. Depth : 49% of WDBD Ave. +3σ 　: 79% of WDBDSamples : 84points

3) Current distribution（30 samples ） 4) Probe mark depth


Measured by laser microscope(VK-8500)Typical 4 Probe Current


5) Stability of Probe mark depth


0%

20%

40%

60%

80%

100%

0 500 1000 1500 2000

The Number of Chips

Rat

e to

WD

BD

(%)

Probe mark depth(Ave.+3σ） keeps under WDBD.


5. Conclusion

1) Probe mark depth:

Hertz pressure achieved under WDBD.

2) For trade off for minimization of Probe mark depth and CRES:

Utilization of Fritting phenomena realized simultaneous achievement of CRES and Probe mark depth targets.

3) The design criteria for high current contact probe was established.

The current per probe and distribution are in design range.

4) The Dynamic Switching Test for IGBT Chip applied to our outgoing test in production line.

dynamic switching test technology for igbt chip under high power … · 2017. 3. 26. · 7 june...

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