dual 12-/14-/16-bit, 1 gsps, digital-to-analog converters ...€¦ · dual 12-/14-/16-bit, 1 gsps,...

Dual 12-/14-/16-Bit,1 GSPS, Digital-to-Analog Converters

AD9776/AD9778/AD9779

Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.

FEATURES

Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions

SFDR = 78 dBc to fOUT = 100 MHz Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA,

RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator

allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP package

APPLICATIONS Wireless infrastructure

WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM Digital high or low IF synthesis Internal digital upconversion capability Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

GENERAL DESCRIPTION

The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high dynamic range, digital-to-analog converters (DACs) that pro-vide a sample rate of 1 GSPS, permitting multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quad-rature modulators such as the AD8349. A serial peripheral interface (SPI®) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The devices are manufactured on an advanced 0.18 μm CMOS process and operate on 1.8 V and 3.3 V supplies for a total power consumption of 1.0 W. They are enclosed in 100-lead TQFP packages.

PRODUCT HIGHLIGHTS

1. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances dynamic performance.

3. The current outputs are easily configured for various single-ended or differential circuit topologies.

4. CMOS data input interface with adjustable set up and hold. 5. Novel 2×, 4×, and 8× interpolator/coarse complex

modulator allows carrier placement anywhere in DAC bandwidth.

TYPICAL SIGNAL CHAIN 05

361-

114

FPGA/ASIC/DSP

DC

COMPLEX I AND Q

DC LO

QUADRATUREMODULATOR/

MIXER/AMPLIFIER

I DAC

Q DAC

DIGITAL INTERPOLATION FILTERS

AD9779

POST DACANALOG FILTER

A

Figure 1.

http://www.analog.com

AD9776/AD9778/AD9779

Rev. A | of 56

TABLE OF CONTENTS Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Typical Signal Chain......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Digital Specifications ................................................................... 6

Digital Input Data Timing Specifications ................................. 7

AC Specifications.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 15

Terminology .................................................................................... 24

Theory of Operation ...................................................................... 25

Serial Peripheral Interface ......................................................... 25

MSB/LSB Transfers..................................................................... 26

SPI Register Map ............................................................................ 27

Interpolation Filter Architecture .................................................. 31

Interpolation Filter Minimum and Maximum Bandwidth Specifications .............................................................................. 35

Driving the REFCLK Input....................................................... 35

Internal PLL Clock Multiplier/Clock Distribution................ 36

Full-Scale Current Generation ................................................. 38

Power Dissipation....................................................................... 39

Power-Down and Sleep Modes................................................. 41

Interleaved Data Mode .............................................................. 41

Timing Information ................................................................... 41

Synchronization of Input Data to DATACLK Output (Pin 37)........................................................................... 43

Synchronization of Input Data to the REFCLK Input (Pin 5 and Pin 6) with PLL Enabled or Disabled............................... 43

Evaluation Board Operation ......................................................... 46

Modifying the Evaluation Board to Use the AD8349 On-Board Quadrature Modulator................................................... 48

Evaluation Board Schematics ................................................... 49

Outline Dimensions ....................................................................... 56

Ordering Guide .......................................................................... 56

REVISION HISTORY

3/07—Rev. 0 to Rev. A

Changes to Features.......................................................................... 1 Changes to Applications .................................................................. 1 Changes to General Product Highlights........................................ 1 Added Figure 1, Renumbered Figures Sequentially..................... 1 Changes to Table 1............................................................................ 4 Changes to Table 2............................................................................ 5 Changes to Table 3............................................................................ 5 Changes to Figure 53 and Figure 54............................................. 26 Changes to Table 12........................................................................ 29 Changes to Power Dissipation Section ........................................ 39

Added Table 19, Renumbered Tables Sequentially .................... 41 Changes to Figure 92 and Figure 93............................................. 42 Changes to Figure 94...................................................................... 42 Added New Figure 95, Renumbered Figures Sequentially ....... 42 Changes to Synchronization of Input Data to the REFCLK Input (Pin 5 and Pin 6) with PLL Enabled or Disabled Section ......... 43 Added New Figure 96, Renumbered Figures Sequentially ....... 43 Changes to Figure 106 ................................................................... 51 7/05—Revision 0: Initial Version

AD9776/AD9778/AD9779

Rev. A | of 56

FUNCTIONAL BLOCK DIAGRAM

10

10

10

10

CLOCK GENERATION/DISTRIBUTION

DATAASSEMBLER

DIGITAL CONTROLLER

2× 2×

SYNC1

CLOCKMULTIPLIER

2×/4×/8×

16-BITIDAC

CLK+

CLK–

IOUT1_P

IOUT1_N

AUX1_PAUX1_NAUX2_PAUX2_N

IOUT2_P

IOUT2_N

GAIN

GAIN

GAIN

GAIN

16-BITQDAC

2×

SYNC1

ILATCH

DELAYLINE

QLATCH

P2D(15:0)

P1D(15:0)

SYNC_O

SYNC_IDATACLK_OUT

2× 2× 2×

n × fDAC/8n = 0, 1, 2 ... 7

POWER-ONRESET

SDO

SDIO

SCL K

CSB

SERIALPERIPHERALINTERFACE

CO

MPL

EXM

OD

ULA

TOR

REF

EREN

CE

AN

D B

IAS

VREF

I120

DELAYLINE

0536

1-00

1

Figure 2. Functional Block Diagram

AD9776/AD9778/AD9779

Rev. A | of 56

SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, = 20 mA, maximum sample rate, unless

otherwise noted. SOUTFI

Table 1. AD9776, AD9778, and AD9779 DC Specifications AD9776 AD9778 AD9779 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 14 16 Bits ACCURACY

Differential Nonlinearity (DNL) ±0.1 ±0.65 ±2.1 LSB Integral Nonlinearity (INL) ±0.6 ±1 ±3.7 LSB

MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR Gain Error (with Internal Reference)

±2 ±2 ±2 % FSR

Full-Scale Output Current1 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 −1.0 +1.0 −1.0 +1.0 V Output Resistance 10 10 10 MΩ Gain DAC Monotonicity Guaranteed Guaranteed Guaranteed

MAIN DAC TEMPERATURE DRIFT Offset 0.04 0.04 0.04 ppm/°C Gain 100 100 100 ppm/°C Reference Voltage 30 30 30 ppm/°C

AUX DAC OUTPUTS Resolution 10 10 10 Bits Full-Scale Output Current1 −1.998 +1.998 −1.998 +1.998 −1.998 +1.998 mA Output Compliance Range (Source)

0 1.6 0 1.6 0 1.6 V

Output Compliance Range (Sink)

0.8 1.6 0.8 1.6 0.8 1.6 V

Output Resistance 1 1 1 MΩ Aux DAC Monotonicity Guaranteed

REFERENCE Internal Reference Voltage 1.2 1.2 1.2 V Output Resistance 5 5 5 kΩ

ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V

DIGITAL SUPPLY VOLTAGES DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V

POWER CONSUMPTION 1× Mode, fDAC = 100 MSPS, IF = 1 MHz

250 300 250 300 250 300 mW

2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL Off

498 498 498 mW

2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL On

588 588 588 mW

4× Mode, fDAC/4 Modulation, fDAC = 500 MSPS, IF = 137.5 MHz, Q DAC Off

572 572 572 mW

AD9776/AD9778/AD9779

Rev. A | of 56

AD9776 AD9778 AD9779 Parameter Min Typ Max Min Typ Max Min Typ Max Unit

8× Mode, fDAC/4 Modulation, fDAC = 1 GSPS, IF = 262.5 MHz

980 980 980 mW

Power-Down Mode 2 3.7 2 3.7 2 3.7 mW Power Supply Rejection Ratio, AVDD33

−0.3 +0.3 −0.3 +0.3 −0.3 +0.3 % FSR/V

OPERATING RANGE −40 +25 +85 −40 +25 +85 −40 +25 +85 °C 1 Based on a 10 kΩ external resistor.

AD9776/AD9778/AD9779

Rev. A | of 56

DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, = 20 mA, maximum sample rate, unless

otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. SOUTFI

Table 2. AD9776, AD9778, and AD9779 Digital Specifications Parameter Conditions Min Typ Max Unit CMOS INPUT LOGIC LEVEL

Input VIN Logic High 2.0 V Input VIN Logic Low 0.8 V Maximum Input Data Rate at Interpolation

1× 300 MSPS 2× 250 MSPS 4× 200 MSPS 8× 125 MSPS

CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)1 Output VOUT Logic High 2.4 V Output VOUT Logic Low 0.4 V

LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) SYNC_I+ = VIA, SYNC_I− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN

2 80 120 Ω LVDS Input Rate 125 MSPS Set-Up Time, SYNC_I to DAC Clock −0.2 ns Hold Time, SYNC_I to DAC Clock 1 ns

LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination Output Voltage High, VOA or VOB 825 1575 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, RO Single-ended 80 100 120 Ω Maximum Clock Rate 1 GHz

DAC CLOCK INPUT (CLK+, CLK−) Differential Peak-to-Peak Voltage (CLK+, CLK−)3 400 800 2000 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate4 1 GSPS

SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High 12.5 ns Minimum Pulse Width Low 12.5 ns

1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests

using an external buffer for this signal. 2 Guaranteed at 25°C. Can drift above 120 Ω at temperatures above 25°C. 3 When using the PLL, a differential swing of 2 V p-p is recommended. 4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.

AD9776/AD9778/AD9779

Rev. A | of 56

DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications Parameter Min Typ Max Unit INPUT DATA (ALL MODES, −40°C to +85°C)1

Set-Up Time, Input Data to DATACLK +2.5 ns Hold Time, Input Data to DATACLK −0.4 ns Set-Up Time, Input Data to REFCLK −0.8 ns Hold Time, Input Data to REFCLK +2.9 ns

1 Timing vs. temperature and data valid keep out windows are delineated in Table 19.

AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, = 20 mA, maximum sample rate, unless

otherwise noted. SOUTFI

Table 4. AD9776, AD9778, and AD9779 AC Specifications AD9776 AD9778 AD9779

Parameter Min Typ Max Min Typ Max Min Typ Max Unit SPURIOUS FREE DYNAMIC RANGE (SFDR)

fDAC = 100 MSPS, fOUT = 20 MHz 82 82 82 dBc fDAC = 200 MSPS, fOUT = 50 MHz 81 81 82 dBc fDAC = 400 MSPS, fOUT = 70 MHz 80 80 80 dBc fDAC = 800 MSPS, fOUT = 70 MHz 85 85 87 dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)

fDAC = 200 MSPS, fOUT = 50 MHz 87 87 91 dBc fDAC = 400 MSPS, fOUT = 60 MHz 80 85 85 dBc fDAC = 400 MSPS, fOUT = 80 MHz 75 81 81 dBc fDAC = 800 MSPS, fOUT = 100 MHz 75 80 81 dBc

NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING

fDAC = 200 MSPS, fOUT = 80 MHz −152 −155 −158 dBm/Hz fDAC = 400 MSPS, fOUT = 80 MHz −155 −159 −160 dBm/Hz fDAC = 800 MSPS, fOUT = 80 MHz −157.5 −160 −161 dBm/Hz

WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

fDAC = 491.52 MSPS, fOUT = 100 MHz 76 78 79 dBc fDAC = 491.52 MSPS, fOUT = 200 MHz 69 73 74 dBc

WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER

fDAC = 491.52 MSPS, fOUT = 100 MHz 77.5 80 81 dBc fDAC = 491.52 MSPS, fOUT = 200 MHz 76 78 78 dBc

AD9776/AD9778/AD9779

Rev. A | of 56

ABSOLUTE MAXIMUM RATINGS Table 5.

Parameter

With Respect To Rating

AVDD33, DVDD33 AGND, DGND, CGND

−0.3 V to +3.6 V

DVDD18, CVDD18 AGND, DGND, CGND

−0.3 V to +1.98 V

AGND DGND, CGND

−0.3 V to +0.3 V

DGND AGND, CGND

−0.3 V to +0.3 V

CGND AGND, DGND

−0.3 V to +0.3 V

I120, VREF, IPTAT AGND −0.3 V to AVDD33 + 0.3 V IOUT1-P, IOUT1-N, IOUT2-P, IOUT2-N, Aux1-P, Aux1-N, Aux2-P, Aux2-N

AGND −1.0 V to AVDD33 + 0.3 V

P1D15 to P1D0, P2D15 to P2D0

DGND −0.3 V to DVDD33 + 0.3 V

DATACLK, TXENABLE DGND −0.3 V to DVDD33 + 0.3 V CLK+, CLK− CGND −0.3 V to CVDD18 + 0.3 V RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO

DGND −0.3 V to DVDD33 + 0.3 V

Junction Temperature +125°C Storage Temperature

Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE 100-lead, thermally enhanced TQFP_EP package, θJA = 19.1°C/W with the bottom EPAD soldered to the PCB. With the bottom EPAD not soldered to the PCB, θJA = 27.4°C/W. These specifications are valid with no airflow movement.

ESD CAUTION

AD9776/AD9778/AD9779

Rev. A | of 56

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

74 VREF73 IPTAT72 AGND

69 CSB

70 RESET

71 IRQ

75 I120

68 SCLK67 SDIO66 SDO

64 DGND63 SYNC_O+62 SYNC_O–61 DVDD3360 DVDD1859 NC58 NC57 NC56 NC55 P2D<0>54 DGND53 DVDD1852 P2D<1>51 P2D<2>

65 PLL_LOCK

PIN 1

100

AVD

D33

99

AG

ND

98

AVD

D33

97

AG

ND

96

AVD

D33

95

AG

ND

94

AG

ND

93

OU

T1_P

92

OU

T1_N

91

AG

ND

90

AU

X1_P

89

AU

X1_N

88

AG

ND

87

AU

X2_N

86

AU

X2_P

85

AG

ND

84

OU

T2_N

83

OU

T2_P

82

AG

ND

81

AG

ND

80

AVD

D33

79

AG

ND

78

AVD

D33

77

AG

ND

76

AVD

D33

26

P1D

<4>

27

P1D

<3>

28

P1D

<2>

29

P1D

<1>

30

P1D

<0>

31

NC

32

DG

ND

33

DVD

D18

34

NC

35

NC

36

NC

37

DA

TAC

LK

38

DVD

D33

39

TXEN

AB

LE

40

P2D

<11>

41

P2D

<10>

42

P2D

<9>

43

DVD

D18

44

DG

ND

45

P2D

<8>

46

P2D

<7>

47P2

D<6

>48

P2D

<5>

49

P2D

<4>

50

P2D

<3>

2CVDD183CGND4CGND

7CGND

6CLK–

5CLK+

1CVDD18

8CGND9CVDD1810CVDD18

12AGND13SYNC_I+14SYNC_I–15DGND16DVDD1817P1D<11>18P1D<10>19P1D<9>20P1D<8>21P1D<7>22DGND23DVDD1824P1D<6>25P1D<5>

11CGND

AD9776TOP VIEW

(Not to Scale)

ANALOG DOMAIN

DIGITAL DOMAIN

NC = NO CONNECT

0536

1-00

2

Figure 3. AD9776 Pin Configuration

Table 6. AD9776 Pin Function Descriptions Pin No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 2 CVDD18 1.8 V Clock Supply. 3 CGND Clock Common. 4 CGND Clock Common. 5 CLK+1 Differential Clock Input. 6 CLK−1 Differential Clock Input. 7 CGND Clock Common. 8 CGND Clock Common. 9 CVDD18 1.8 V Clock Supply. 10 CVDD18 1.8 V Clock Supply. 11 CGND Clock Common. 12 AGND Analog Common. 13 SYNC_I+ Differential Synchronization Input. 14 SYNC_I− Differential Synchronization Input. 15 DGND Digital Common. 16 DVDD18 1.8 V Digital Supply. 17 P1D<11> Port 1, Data Input D11 (MSB). 18 P1D<10> Port 1, Data Input D10. 19 P1D<9> Port 1, Data Input D9.

Pin No. Mnemonic Description 20 P1D<8> Port 1, Data Input D8. 21 P1D<7> Port 1, Data Input D7. 22 DGND Digital Common. 23 DVDD18 1.8 V Digital Supply. 24 P1D<6> Port 1, Data Input D6. 25 P1D<5> Port 1, Data Input D5. 26 P1D<4> Port 1, Data Input D4. 27 P1D<3> Port 1, Data Input D3. 28 P1D<2> Port 1, Data Input D2. 29 P1D<1> Port 1, Data Input D1. 30 P1D<0> Port 1, Data Input D0 (LSB). 31 NC No Connect. 32 DGND Digital Common. 33 DVDD18 1.8 V Digital Supply. 34 NC No Connect. 35 NC No Connect. 36 NC No Connect. 37 DATACLK Data Clock Output. 38 DVDD33 3.3 V Digital Supply.

AD9776/AD9778/AD9779

Rev. A | of 56

Pin No. Mnemonic Description 39 TXENABLE Transmit Enable. 40 P2D<11> Port 2, Data Input D11 (MSB). 41 P2D<10> Port 2, Data Input D10. 42 P2D<9> Port 2, Data Input D9. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<8> Port 2, Data Input D8. 46 P2D<7> Port 2, Data Input D7. 47 P2D<6> Port 2, Data Input D6. 48 P2D<5> Port 2, Data Input D5. 49 P2D<4> Port 2, Data Input D4. 50 P2D<3> Port 2, Data Input D3. 51 P2D<2> Port 2, Data Input D2. 52 P2D<1> Port 2, Data Input D1. 53 DVDD18 1.8 V Digital Supply. 54 DGND Digital Common. 55 P2D<0> Port 2, Data Input D0 (LSB). 56 NC No Connect. 57 NC No Connect. 58 NC No Connect. 59 NC No Connect. 60 DVDD18 1.8 V Digital Supply. 61 DVDD33 3.3 V Digital Supply. 62 SYNC_O− Differential Synchronization Output. 63 SYNC_O+ Differential Synchronization Output 64 DGND Digital Common 65 PLL_LOCK PLL Lock Indicator 66 SDO SPI Port Data Output 67 SDIO SPI Port Data Input/Output 68 SCLK SPI Port Clock 69 CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 72 AGND Analog Common.

Pin No. Mnemonic Description 73 IPTAT Factory Test Pin. Output current is

proportional to absolute temperature, approximately 10 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating.

74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76 AVDD33 3.3 V Analog Supply. 77 AGND Analog Common. 78 AVDD33 3.3 V Analog Supply. 79 AGND Analog Common. 80 AVDD33 3.3 V Analog Supply. 81 AGND Analog Common. 82 AGND Analog Common. 83 OUT2_P Differential DAC Current Output, Channel 2. 84 OUT2_N Differential DAC Current Output, Channel 2. 85 AGND Analog Common. 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 88 AGND Analog Common. 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 91 AGND Analog Common. 92 OUT1_N Differential DAC Current Output, Channel 1. 93 OUT1_P Differential DAC Current Output, Channel 1. 94 AGND Analog Common. 95 AGND Analog Common. 96 AVDD33 3.3 V Analog Supply. 97 AGND Analog Common. 98 AVDD33 3.3 V Analog Supply. 99 AGND Analog Common. 100 AVDD33 3.3 V Analog Supply. 1 The combined differential clock input at the CLK+ and CLK– pins are referred

to as REFCLK.

AD9776/AD9778/AD9779

Rev. A | of 56


69 CSB

70 RESET

71 IRQ

75 I120


64 DGND63 SYNC_O+62 SYNC_O–61 DVDD3360 DVDD1859 NC58 NC57 P2D<0>56 P2D<1>55 P2D<2>54 DGND53 DVDD1852 P2D<3>51 P2D<4>

65 PLL_LOCK

PIN 1

100

AVD

D33

99

AG

ND

98

AVD

D33

97

AG

ND

96

AVD

D33

95

AG

ND

94

AG

ND

93

OU

T1_P

92

OU

T1_N

91

AG

ND

90

AU

X1_P

89

AU

X1_N

88

AG

ND

87

AU

X2_N

86

AU

X2_P

85

AG

ND

84

OU

T2_N

83

OU

T2_P

82

AG

ND

81

AG

ND

80

AVD

D33

79

AG

ND

78

AVD

D33

77

AG

ND

76

AVD

D33

26

P1D

<6>

27

P1D

<5>

28

P1D

<4>

29

P1D

<3>

30

P1D

<2>

31

P1D

<1>

32

DG

ND

33

DVD

D18

34

P1D

<0>

35

NC

36

NC

37

DA

TAC

LK

38

DVD

D33

39

TXEN

AB

LE

40

P2D

<13>

41

P2D

<12>

42

P2D

<11>

43

DVD

D18

44

DG

ND

45P2

D<1

0>46

P2D

<9>

47

P2D

<8>

48

P2D

<7>

49

P2D

<6>

50

P2D

<5>

2CVDD183CGND4CGND

7CGND

6CLK–

5CLK+

1CVDD18



11CGND

AD9778TOP VIEW

(Not to Scale)

ANALOG DOMAIN

DIGITAL DOMAIN

NC = NO CONNECT

0536

1-00

3


Table 7. AD9778 Pin Function Description Pin No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 2 CVDD18 1.8 V Clock Supply. 3 CGND Clock Common. 4 CGND Clock Common. 5 CLK+1 Differential Clock Input. 6 CLK−1 Differential Clock Input. 7 CGND Clock Common. 8 CGND Clock Common. 9 CVDD18 1.8 V Clock Supply. 10 CVDD18 1.8 V Clock Supply. 11 CGND Clock Common. 12 AGND Analog Common. 13 SYNC_I+ Differential Synchronization Input. 14 SYNC_I− Differential Synchronization Input. 15 DGND Digital Common. 16 DVDD18 1.8 V Digital Supply. 17 P1D<13> Port 1, Data Input D13 (MSB). 18 P1D<12> Port 1, Data Input D12. 19 P1D<11> Port 1, Data Input D11. 20 P1D<10> Port 1, Data Input D10.

Pin No. Mnemonic Description 21 P1D<9> Port 1, Data Input D9. 22 DGND Digital Common. 23 DVDD18 1.8 V Digital Supply. 24 P1D<8> Port 1, Data Input D8. 25 P1D<7> Port 1, Data Input D7. 26 P1D<6> Port 1, Data Input D6. 27 P1D<5> Port 1, Data Input D5. 28 P1D<4> Port 1, Data Input D4. 29 P1D<3> Port 1, Data Input D3. 30 P1D<2> Port 1, Data Input D2. 31 P1D<1> Port 1, Data Input D1. 32 DGND Digital Common. 33 DVDD18 1.8 V Digital Supply. 34 P1D<0> Port 1, Data Input D0 (LSB). 35 NC No Connect. 36 NC No Connect. 37 DATACLK Data Clock Output. 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE Transmit Enable. 40 P2D<13> Port 2, Data Input D13 (MSB).

AD9776/AD9778/AD9779

Rev. A | of 56

Pin No. Mnemonic Description 41 P2D<12> Port 2, Data Input D12. 42 P2D<11> Port 2, Data Input D11. 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<10> Port 2, Data Input D10. 46 P2D<9> Port 2, Data Input D9. 47 P2D<8> Port 2, Data Input D8. 48 P2D<7> Port 2, Data Input D7. 49 P2D<6> Port 2, Data Input D6. 50 P2D<5> Port 2, Data Input D5. 51 P2D<4> Port 2, Data Input D4. 52 P2D<3> Port 2, Data Input D3. 53 DVDD18 1.8 V Digital Supply. 54 DGND Digital Common. 55 P2D<2> Port 2, Data Input D2. 56 P2D<1> Port 2, Data Input D1. 57 P2D<0> Port 2, Data Input D0 (LSB). 58 NC No Connect. 59 NC No Connect. 60 DVDD18 1.8 V Digital Supply. 61 DVDD33 3.3 V Digital Supply. 62 SYNC_O− Differential Synchronization Output. 63 SYNC_O+ Differential Synchronization Output. 64 DGND Digital Common. 65 PLL_LOCK PLL Lock Indicator. 66 SDO SPI Port Data Output. 67 SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 72 AGND Analog Common. 73 IPTAT Factory Test Pin. Output current is


Pin No. Mnemonic Description 74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76 AVDD33 3.3 V Analog Supply. 77 AGND Analog Common. 78 AVDD33 3.3 V Analog Supply. 79 AGND Analog Common. 80 AVDD33 3.3 V Analog Supply. 81 AGND Analog Common. 82 AGND Analog Common. 83 OUT2_P Differential DAC Current Output,

Channel 2. 84 OUT2_N Differential DAC Current Output,

Channel 2. 85 AGND Analog Common. 86 AUX2_P Auxiliary DAC Current Output,

Channel 2. 87 AUX2_N Auxiliary DAC Current Output,

Channel 2. 88 AGND Analog Common. 89 AUX1_N Auxiliary DAC Current Output,

Channel 1. 90 AUX1_P Auxiliary DAC Current Output,

Channel 1. 91 AGND Analog Common. 92 OUT1_N Differential DAC Current Output,

Channel 1. 93 OUT1_P Differential DAC Current Output,

Channel 1. 94 AGND Analog Common. 95 AGND Analog Common. 96 AVDD33 3.3 V Analog Supply. 97 AGND Analog Common. 98 AVDD33 3.3 V Analog Supply. 99 AGND Analog Common. 100 AVDD33 3.3 V Analog Supply. 1 The combined differential clock input at the CLK+ and CLK– pins are referred

to as REFCLK.

AD9776/AD9778/AD9779

Rev. A | of 56


69 CSB

70 RESET

71 IRQ

75 I120


64 DGND63 SYNC_O+62 SYNC_O–61 DVDD3360 DVDD1859 P2D<0>58 P2D<1>57 P2D<2>56 P2D<3>55 P2D<4>54 DGND53 DVDD1852 P2D<5>51 P2D<6>

65 PLL_LOCK

PIN 1

100

AVD

D33

99

AG

ND

98

AVD

D33

97

AG

ND

96

AVD

D33

95

AG

ND

94

AG

ND

93

OU

T1_P

92

OU

T1_N

91

AG

ND

90

AU

X1_P

89

AU

X1_N

88

AG

ND

87

AU

X2_N

86

AU

X2_P

85

AG

ND

84

OU

T2_N

83

OU

T2_P

82

AG

ND

81

AG

ND

80

AVD

D33

79

AG

ND

78

AVD

D33

77

AG

ND

76

AVD

D33

26

P1D

<8>

27

P1D

<7>

28

P1D

<6>

29

P1D

<5>

30

P1D

<4>

31

P1D

<3>

32

DG

ND

33

DVD

D18

34

P1D

<2>

35

P1D

<1>

36

P1D

<0>

37

DA

TAC

LK

38

DVD

D33

39

TXEN

AB

LE

40

P2D

<15>

41

P2D

<14>

42

P2D

<13>

43

DVD

D18

44

DG

ND

45

P2D

<12>46

P2D

<11>

47

P2D

<10>

48

P2D

<9>

49

P2D

<8>

50

P2D

<7>

2CVDD183CGND4CGND

7CGND

6CLK–

5CLK+

1CVDD18



11CGND

AD9779TOP VIEW

(Not to Scale)

ANALOG DOMAIN

DIGITAL DOMAIN

0536

1-00

4


Table 8. AD9779 Pin Function Descriptions Pin No. Mnemonic Description 1 CVDD18 1.8 V Clock Supply. 2 CVDD18 1.8 V Clock Supply. 3 CGND Clock Common. 4 CGND Clock Common. 5 CLK+1 Differential Clock Input. 6 CLK−1 Differential Clock Input. 7 CGND Clock Common. 8 CGND Clock Common. 9 CVDD18 1.8 V Clock Supply. 10 CVDD18 1.8 V Clock Supply. 11 CGND Clock Common. 12 AGND Analog Common. 13 SYNC_I+ Differential Synchronization Input. 14 SYNC_I− Differential Synchronization Input. 15 DGND Digital Common. 16 DVDD18 1.8 V Digital Supply. 17 P1D<15> Port 1, Data Input D15 (MSB). 18 P1D<14> Port 1, Data Input D14. 19 P1D<13> Port 1, Data Input D13. 20 P1D<12> Port 1, Data Input D12. 21 P1D<11> Port 1, Data Input D11.

Pin No. Mnemonic Description 22 DGND Digital Common. 23 DVDD18 1.8 V Digital Supply. 24 P1D<10> Port 1, Data Input D10. 25 P1D<9> Port 1, Data Input D9. 26 P1D<8> Port 1, Data Input D8. 27 P1D<7> Port 1, Data Input D7. 28 P1D<6> Port 1, Data Input D6. 29 P1D<5> Port 1, Data Input D5. 30 P1D<4> Port 1, Data Input D4. 31 P1D<3> Port 1, Data Input D3. 32 DGND Digital Common. 33 DVDD18 1.8 V Digital Supply. 34 P1D<2> Port 1, Data Input D2. 35 P1D<1> Port 1, Data Input D1. 36 P1D<0> Port 1, Data Input D0 (LSB). 37 DATACLK Data Clock Output. 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE Transmit Enable. 40 P2D<15> Port 2, Data Input D15 (MSB). 41 P2D<14> Port 2, Data Input D14. 42 P2D<13> Port 2, Data Input D13.

AD9776/AD9778/AD9779

Rev. A | of 56

Pin No. Mnemonic Description 43 DVDD18 1.8 V Digital Supply. 44 DGND Digital Common. 45 P2D<12> Port 2, Data Input D12. 46 P2D<11> Port 2, Data Input D11. 47 P2D<10> Port 2, Data Input D10. 48 P2D<9> Port 2, Data Input D9. 49 P2D<8> Port 2, Data Input D8. 50 P2D<7> Port 2, Data Input D7. 51 P2D<6> Port 2, Data Input D6. 52 P2D<5> Port 2, Data Input D5. 53 DVDD18 1.8 V Digital Supply. 54 DGND Digital Common. 55 P2D<4> Port 2, Data Input D4. 56 P2D<3> Port 2, Data Input D3. 57 P2D<2> Port 2, Data Input D2. 58 P2D<1> Port 2, Data Input D1. 59 P2D<0> Port 2, Data Input D0 (LSB). 60 DVDD18 1.8 V Digital Supply. 61 DVDD33 3.3 V Digital Supply. 62 SYNC_O− Differential Synchronization Output. 63 SYNC_O+ Differential Synchronization Output. 64 DGND Digital Common. 65 PLL_LOCK PLL Lock Indicator. 66 SPI_SDO SPI Port Data Output. 67 SPI_SDIO SPI Port Data Input/Output. 68 SCLK SPI Port Clock. 69 SPI_CSB SPI Port Chip Select Bar. 70 RESET Reset, Active High. 71 IRQ Interrupt Request. 72 AGND Analog Common. 73 IPTAT Factory Test Pin. Output current is


Pin No. Mnemonic Description 74 VREF Voltage Reference Output. 75 I120 120 μA Reference Current. 76 AVDD33 3.3 V Analog Supply. 77 AGND Analog Common. 78 AVDD33 3.3 V Analog Supply. 79 AGND Analog Common. 80 AVDD33 3.3 V Analog Supply. 81 AGND Analog Common. 82 AGND Analog Common. 83 OUT2_P Differential DAC Current Output,

Channel 2. 84 OUT2_N Differential DAC Current Output,

Channel 2. 85 AGND Analog Common. 86 AUX2_P Auxiliary DAC Current Output, Channel 2. 87 AUX2_N Auxiliary DAC Current Output, Channel 2. 88 AGND Analog Common. 89 AUX1_N Auxiliary DAC Current Output, Channel 1. 90 AUX1_P Auxiliary DAC Current Output, Channel 1. 91 AGND Analog Common. 92 OUT1_N Differential DAC Current Output,

Channel 1. 93 OUT1_P Differential DAC Current Output,

Channel 1. 94 AGND Analog Common. 95 AGND Analog Common. 96 AVDD33 3.3 V Analog Supply. 97 AGND Analog Common. 98 AVDD33 3.3 V Analog Supply. 99 AGND Analog Common. 100 AVDD33 3.3 V Analog Supply. 1 The combined differential clock input at the CLK+ and CLK– pins are referred

to as REFCLK.

AD9776/AD9778/AD9779

Rev. A | of 56

TYPICAL PERFORMANCE CHARACTERISTICS 4

–60

CODE

INL

(16-

BIT

LSB

)

3

2

1

0

–1

–2

–3

–4

–5

10k 20k 30k 60k50k40k

0536

1-00

5

Figure 6. AD9779 Typical INL

1.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

0 60k50k40k30k20k10kCODE

DN

L (1

6-B

IT L

SB)

0536

1-00

6

Figure 7. AD9779 Typical DNL

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 160MSPS

fDATA = 200MSPS

fDATA = 250MSPS

0536

1-00

7

Figure 8. AD9779 In-Band SFDR vs. fOUT, 1x Interpolation

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 160MSPS

fDATA = 200MSPS

fDATA = 250MSPS

0536

1-00

8

Figure 9. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 100MSPS fDATA = 200MSPS

fDATA = 150MSPS

0536

1-00

9


100

500 50

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

10 20 30 40

fDATA = 50MSPS fDATA = 100MSPS

fDATA = 125MSPS05

361-

010


AD9776/AD9778/AD9779

Rev. A | of 56

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 200MSPS

fDATA = 160MSPS

fDATA = 250MSPS

0536

1-01

1

Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 150MSPS

fDATA = 100MSPS

fDATA = 200MSPS

0536

1-01

2


100

500 50

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

10 20 30 40

fDATA = 50MSPSfDATA = 100MSPS

fDATA = 125MSPS

0536

1-01

3


100

500 4

fOUT (MHz)

SFD

R (d

Bc)

0

90

80

70

60

10 20 30

PLL OFF

PLL ON

0536

1-01

4

Figure 15. AD9779 In-Band SFDR, 4× Interpolation,

fDATA = 100 MSPS, PLL On/Off

100

500 8

fOUT (MHz)

SFD

R (d

Bc)

0

90

80

70

60

20 40 60

–3dBFS

0dBFS

–6dBFS

0536

1-01

5

Figure 16. AD9779 In-Band SFDR vs. Digital Full-Scale Input

100

500 8

fOUT (MHz)

SFD

R (d

Bc)

0

90

80

70

60

20 40 60

10mA

20mA

30mA

0536

1-01

6

Figure 17. AD9779 In-Band SFDR vs. Output Full-Scale Current

AD9776/AD9778/AD9779

Rev. A | of 56

100

500 120

fOUT (MHz)

IMD

(dB

c)

90

80

70

60

20 40 60 80 100

fDATA = 200MSPS

fDATA = 250MSPS

fDATA = 160MSPS

0536

1-01

7

Figure 18. AD9779 Third-Order IMD vs. fOUT, 1× Interpolation

100

500 20 40 60 80 100 120 140 160 180 200 220

fOUT (MHz)

IMD

(dB

c)

90

80

70

60

fDATA = 160MSPS

fDATA = 250MSPS

fDATA = 200MSPS

0536

1-01

8


100

500 400

fOUT (MHz)

IMD

(dB

c)

90

80

70

60

40 80 120 160 200 240 280 320 360

fDATA = 150MSPS

fDATA = 200MSPS

fDATA = 100MSPS

0536

1-01

9


fOUT (MHz)

IMD

(dB

c)

fDATA = 75MSPS

fDATA = 125MSPS

fDATA = 100MSPS

90

100

80

70

60

50

450

425

400

375

350

325

300

275

250

225

200

175

150

125

1007550250

fDATA = 50MSPS

0536

1-02

0


100

500 200

fOUT (MHz)

IMD

(dB

c)

90

80

70

60

10020 40 60 80 120 140 160 180

PLL OFF

PLL ON

0536

1-02

1

Figure 22. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation,

fDATA = 100 MSPS, PLL On vs. PLL Off

100

95

50

55

0 400360fOUT (MHz)

IMD

(dB

c)

90

80

85

70

75

60

65

40 80 120 160 200 240 280 320

0536

1-02

2

Figure 23. AD9779 Third-Order IMD vs. fOUT, over 50 Parts,4× Interpolation,

fDATA = 200 MSPS

AD9776/AD9778/AD9779

Rev. A | of 56

100

50

55

60

65

70

75

80

85

90

95

0 400fOUT (MHz)

IMD

(dB

c)

80 160 240 36032040 120 200 280

0536

1-11

7

0dBFS

–3dBFS

–6dBFS

Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation, fDATA = 200 MSPS

100

50

55

60

65

70

75

80

85

90

95

0 400fOUT (MHz)

IMD

(dB

c)

80 160 240 36032040 120 200 280

0536

1-11

8

20mA

10mA

30mA

Figure 25. IMD Performance vs. Full-Scale Output Current, 4× Interpolation,

fDATA = 200 MSPS

STOP 400.0MHzSWEEP 1.203s (601 pts)VBW 20kHz

START 1.0MHz*RES BW 20kHz

REF 0dBm*PEAKLog10dB/

LGAV51W1S3

£(f):FTUNSWP

S2FCAA

*ATTEN 20dB

EXT REFDC COUPLED

0536

1-02

3

Figure 26. AD9779 Single Tone, 4× Interpolation, fDATA = 100 MSPS,

fOUT = 30 MHz

STOP 400.0MHzSWEEP 1.203s (601 pts)VBW 20kHz

START 1.0MHz*RES BW 20kHz

REF 0dBm*PEAKLog10dB/

LGAV51W1S3

£(f):FTUNSWP

S2FCAA

*ATTEN 20dB

EXT REFDC COUPLED

0536

1-02

4

Figure 27. AD9779 Two-Tone Spectrum, 4× Interpolation,

fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz

–142

–146

–150

–154

–158

–162

–166

–1700

fOUT (MHz)

NSD

(dB

m/H

z)

20 40 60 80

0dBFS

–3dBFS

–6dBFS

0536

1-02

5

Figure 28. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone

Input, fDATA = 200 MSPS, 2× Interpolation

–150

–1700 100

fOUT (MHz)

NSD

(dB

m/H

z)

–154

–158

–162

–166

20 40 60 80

fDAC = 800MSPS

fDAC = 400MSPS

fDAC = 200MSPS05

361-

026

Figure 29. AD9779 Noise Spectral Density vs. fDAC, Eight-Tone Input

with 500 kHz Spacing, fDATA = 200 MSPS

AD9776/AD9778/AD9779

Rev. A | of 56

–150

–1700 100

fOUT (MHz)

NSD

(dB

m/H

z)

–154

–158

–162

–166

20 40 60 80

fDAC = 800MSPS

fDAC = 400MSPSfDAC = 200MSPS

0536

1-02

7

Figure 30. AD9779 Noise Spectral Density vs. fDAC, Single-Tone Input at −6 dBFS

–55

–900 260

fOUT (MHz)

AC

LR (d

Bc)

–60

–65

–70

–75

–80

–85

20 40 60 80 100 120 140 160 180 200 220 240

–6dBFS

–3dBFS

0dBFS – PLL ON

0dBFS

0536

1-02

8

Figure 31. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF

–55

–900 260

fOUT (MHz)

AC

LR (d

Bc)

–60

–65

–70

–75

–80

–85

20 40 60 80 100 120 140 160 180 200 220 240

–6dBFS

–3dBFS

0dBFS – PLL ON

0dBFS

0536

1-02

9

Figure 32. AD9779 ACLR for Second Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates

Baseband Signal to IF

–55

–900 260

fOUT (MHz)

AC

LR (d

Bc)

–60

–65

–70

–75

–80

–85

20 40 60 80 100 120 140 160 180 200 220 240

–6dBFS

–3dBFS

0dBFS – PLL ON

0dBFS

0536

1-03

0

Figure 33. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF

AD9776/AD9778/AD9779

Rev. A | of 56

SPAN 50MHzSWEEP 162.2ms (601 pts)VBW 300kHz

CENTER 143.88MHz*RES BW 30kHz

RMS RESULTSCARRIER POWER–12.49dBm/3.84000MHz

FREQ OFFSET5.000MHz10.00MHz15.00MHz

REF BW3.840MHz3.840MHz3.840MHz

dBc–76.75–80.94–79.95

dBm–89.23–93.43–92.44

LOWERdBc–77.42–80.47–78.96

dBm–89.91–92.96–91.45

UPPER

REF –25.28dBm*AVGLog10dB/

PAVG10W1 S2

*ATTEN 4dB

EXT REF

0536

1-03

1

Figure 34. AD9779 WCDMA Signal, 4× Interpolation,

fDATA =122.88 MSPS, fDAC/4 Modulation



1 –17.87dBm2 –20.65dBm3 –18.26dBm4 –18.23dBm

TOTAL CARRIER POWER –12.61dBm/15.3600MHzREF CARRIER POWER –17.87dBm/3.84000MHz


INTEG BW3.840MHz3.840MHz3.840MHz

dBc–67.70–70.00–71.65

dBm–85.57–97.87–99.52

LOWERdBc–67.70–69.32–71.00

dBm–85.57–87.19–88.88

UPPER


PAVG10W1 S2

*ATTEN 4dB

EXT REF

0536

1-03

2

Figure 35. AD9779 Multicarrier WCDMA Signal, 4× Interpolation,

fDAC =122.88 MSPS, fDAC/4 Modulation

1.5

0CODE

INL

(14-

BIT

LSB

)

10k

1.0

0.5

0

–0.5

–1.0

–1.52k 4k 6k 8k

0536

1-03

3


0.6

0CODE

DN

L (1

4-B

IT L

SB)

–0.2

–1.016k14k12k10k8k6k4k2k

0.4

0.2

0

–0.4

–0.6

–0.8

0536

1-03

4


AD9776/AD9778/AD9779

Rev. A | of 56

100

500 400

fOUT (MHz)

IMD

(dB

c)

90

80

70

60

40 80 120 160 200 240 280 320 360

4× 200MSPS

4× 150MSPS

4× 100MSPS

0536

1-03

5

Figure 38. AD9778 IMD, 4× Interpolation

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 250MSPS

fDATA = 200MSPSfDATA = 160MSPS

0536

1-03

6

Figure 39. AD9778 In-Band SFDR, 2× Interpolation

–900 250

fOUT (MHz)

AC

LR (d

Bc) –70

–80

–60

25 50 75 100 125 150 175 200 225

1ST ADJ CHAN

2ND ADJ CHAN

3RD ADJ CHAN

0536

1-03

7

Figure 40. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation, fDATA = 122.88 MSPS, Amplitude = −3 dBFS






dBc–76.49–80.13–80.90

dBm–89.23–92.87–93.64

LOWERdBc–76.89–80.02–79.53

dBm–89.63–92.76–92.27

UPPER


PAVG10W1 S2

*ATTEN 4dB

0536

1-03

8

Figure 41. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,

fDAC/4 Modulation

–150

–1700 100

fOUT (MHz)

NSD

(dB

m/H

z)–154

–158

–162

–166

20 40 60 80

fDAC = 800MSPS

fDAC = 400MSPS

fDAC = 200MSPS

0536

1-03

9

Figure 42. AD9778 Noise Spectral Density vs. fDAC Eight-Tone Input

with 500 kHz Spacing, fDATA = 200 MSPS

–150

–1700 100

fOUT (MHz)

NSD

(dB

m/H

z)

–154

–158

–162

–166

20 40 60 80

fDAC = 800MSPS

fDAC = 400MSPS

fDAC = 200MSPS05

361-

040

Figure 43. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input at −6 dBFS, fDATA = 200 MSPS

AD9776/AD9778/AD9779

Rev. A | of 56

0.4

0 4096CODE

INL

(12-

BIT

LSB

)

–0.4512 1024 256020481536 3072 3584

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

0536

1-04

1


0.20

0 4096CODE

DN

L (1

2-B

IT L

SB)

2048–0.20

512 1024 1536 2560 3072 3584

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

0536

1-04

2


100

500 400

fOUT (MHz)

IMD

(dB

c)

40 80 120 160 200 240 280 320 360

4× 200MSPS4× 100MSPS

4× 150MSPS

95

90

85

80

75

70

65

60

55

0536

1-04

3

Figure 46. AD9776 IMD, 4× Interpolation

100

500 100

fOUT (MHz)

SFD

R (d

Bc)

90

80

70

60

20 40 60 80

fDATA = 250MSPS

fDATA = 200MSPS

fDATA = 160MSPS

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Figure 47. AD9776 In-Band SFDR, 2× Interpolation

–900 250

FOUT (MHz)

AC

LR (d

Bc)

–55

25 50 75 100 125 150 175 200 225

1ST ADJ CHAN

2ND ADJ CHAN

3RD ADJ CHAN

–60

–65

–70

–75

–80

–85

0536

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5

Figure 48. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation






dBc–75.00–78.05–77.73

dBm–87.67–90.73–90.41

LOWERdBc–75.30–77.99–77.50

dBm–87.97–90.66–90.17

UPPER


PAVG10W1 S2

*ATTEN 4dB

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Figure 49. AD9776, Single Carrier WCDMA, 4× Interpolation,

fDATA = 122.88 MSPS, Amplitude = −3 dBFS

AD9776/AD9778/AD9779

Rev. A | of 56

–150

–1700 100

fOUT (MHz)

NSD

(dB

m/H

z)

–154

–158

–162

–166

20 40 60 80

fDAC = 800MSPS

fDAC = 400MSPS

fDAC = 200MSPS

10 30 50 70 90

0536

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7

Figure 50. AD9776 Noise Spectral Density vs. fDAC, Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS

–150

–1700 100

fOUT (MHz)

NSD

(dB

m/H

z)

–154

–158

–162

–166

20 40 60 80

fDAC = 800MSPS

fDAC = 400MSPS

fDAC = 200MSPS

10 30 50 70 90

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Figure 51. AD9776 Noise Spectral Density vs. fDAC, Single-Tone Input at −6 dBFS, fDATA = 200 MSPS

AD9776/AD9778/AD9779

Rev. A | of 56

TERMINOLOGY Integral Nonlinearity (INL)

INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.

Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1.

B

Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.

Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius.

Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.

Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition.

In-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate.

Out-of-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the Nyquist frequency of the DAC output sample rate. Normally, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output.

Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic com-ponents to the rms value of the measured fundamental. It is expressed as a percentage or in decibels.

Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.

Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed.

Adjacent Channel Leakage Ratio (ACLR) The ratio in dBc between the measured power within a channel relative to its adjacent channel.

Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

AD9776/AD9778/AD9779

Rev. A | of 56

THEORY OF OPERATION The AD9776/AD9778/AD9779 combine many features that make them very attractive DACs for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available DACs. The digital engine uses a break-through filter architecture that combines the interpolation with a digital quadrature modulator. This allows the parts to conduct digital quadrature frequency upconversion. They also have features that allow simplified synchronization with incoming data and between multiple parts.

The serial port configuration is controlled by Register 0x00, Bits<6:7>. It is important to note that the configuration changes immediately upon writing to the last bit of the byte. For multi-byte transfers, writing to this register can occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle.

The same considerations apply to setting the software reset, RESET (Register 0x00, Bit 5) or pulling the RESET pin (Pin 70) high. All registers are set to their default values, except Register 0x00 and Register 0x04, which remain unchanged.

Use of only single-byte transfers when changing serial port configurations or initiating a software reset is recommended to prevent unexpected device behavior.

As described in this section, all serial port data is transferred to/from the device in synchronization to the SCLK pin. If synchronization is lost, the device has the ability to asynchro-nously terminate an I/O operation, putting the serial port controller into a known state and, thereby, regaining synchronization.

SERIAL PERIPHERAL INTERFACE

SPI_SDO

SPIPORT

66

SPI_SDI 67

SPI_SCLK 68

SPI_CSB 69

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Figure 52. SPI Port

The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro-controllers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9776/ AD9778/AD9779. Single or multiple byte transfers are sup-

ported, as well as MSB-first or LSB-first transfer formats. The serial interface ports can be configured as a single pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO).

General Operation of the Serial Interface

There are two phases to a communication cycle with the AD977x. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device.

A logic high on the CSB pin followed by a logic low resets the SPI port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation, regardless of the state of the internal registers or the other signal levels at the inputs to the SPI port. If the SPI port is in an instruction cycle or a data transfer cycle, none of the present data is written.

The remaining SCLK edges are for Phase 2 of the communica-tion cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes as determined by the instruction byte. Using one multibyte transfer is preferred. Single-byte data transfers are useful in reducing CPU overhead when register access requires only one byte. Registers change immediately upon writing to the last bit of each transfer byte.

Instruction Byte

The instruction byte contains the information shown in Table 9.

Table 9. SPI Instruction Byte MSB LSB I7 I6 I5 I4 I3 I2 I1 I0 R/W N1 N0 A4 A3 A2 A1 A0

R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates a read operation. Logic 0 indicates a write operation.

N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are listed in Table 10.

A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0, respec-tively, of the instruction byte determine the register that is accessed during the data transfer portion of the communication cycle.

AD9776/AD9778/AD9779

Rev. A | of 56

For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the device based on the LSB-first bit (Register 0x00, Bit 6).

Table 10. Byte Transfer Count N1 N0 Description 0 0 Transfer one byte 0 1 Transfer three bytes 1 0 Transfer two bytes 1 1 Transfer four bytes

Serial Interface Port Pin Descriptions

Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CSB) Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle.

Serial Data I/O (SDIO) Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional.

Serial Data Out (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

MSB/LSB TRANSFERS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by Register Bit LSB_FIRST (Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0).

When LSB-first = 0 (MSB-first) the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from high address to low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle.

When LSB-first = 1 (LSB-first) the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by mul-tiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle.

The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x1F for multibyte I/O operations if the LSB-first mode is active.

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6N D5N D00D10D20D30

D7 D6N D5N D00D10D20D30

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

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Figure 53. Serial Register Interface Timing MSB-First

A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D7ND6ND5ND4N

D00 D10 D20 D7ND6ND5ND4N

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

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Figure 54. Serial Register Interface Timing LSB-First

INSTRUCTION BIT 6INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDS tDH

tPWH tPWL

tSCLK

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Figure 55. Timing Diagram for SPI Register Write

DATA BIT n–1DATA BIT n

CSB

SCLK

SDIOSDO

tDV

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Figure 56. Timing Diagram for SPI Register Read

AD9776/AD9778/AD9779

Rev. A | of 56

SPI REGISTER MAP Table 11. Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Def.

Comm 0x00 00 SDIO Bidirectional

LSB/MSB First Software Reset

Power-Down Mode

Auto Power-Down Enable

PLL Lock Indicator (Read Only)

0x00

0x01 01 Filter Interpolation Factor<1:0> Filter Modulation Mode<3:0> Zero Stuffing Enable

0x00 Digital Control

0x02 02 Data Format Dual/Interleaved Data Bus Mode

Real Mode Data Clock Delay Enable

Inverse Sinc Enable

DATACLK Invert

TxEnable Invert

Q First 0x00

Sync Control

0x03 03 Data Clock Delay Mode<1:0> Data Clock Divide Ratio<1:0>

Reserved 0x00

0x04 04 Data Clock Delay<3:0> Output Sync Pulse Divide<2:0> Sync Out Delay<4>

0x00

0x05 05 Sync Out Delay<3:0> Input Sync Pulse Frequency Ratio<2:0> Sync Input Delay<4>

0x00

0x06 06 Sync Input Delay<3:0> Input Sync Pulse Timing Error Tolerance<3:0> 0x00

0x07 07 Sync Receiver Enable

Sync Driver Enable

Sync Triggering Edge

DAC Clock Offset<4:0> 0x00

PLL Control

0x08 08 PLL Band Select<5:0> PLL VCO AGC Gain<1:0>

0xCF

0x09 09 PLL Enable PLL VCO Divider Ratio<1:0> PLL Loop Divide

Ratio<1:0>

PLL Bias Setting<2:0> 0x37

Misc Control

0x0A 10 PLL Control Voltage Range<2:0> (Read Only) PLL Loop Bandwidth Adjustment<4:0> 0x38

0x0B 11 I DAC Gain Adjustment<7:0> 0xF9 I DAC Control Register

0x0C 12 I DAC Sleep I DAC Power Down

I DAC Gain Adjustment<9:8>

0x01

0x0D 13 Auxiliary DAC1 Data<7:0> 0x00 Aux DAC1 Control Register

0x0E 14 Auxiliary DAC1 Sign

Auxiliary DAC1 Current Direction

Auxiliary DAC1

Power-Down

Auxiliary DAC1 Data<9:8>

0x00

0x0F 15 Q DAC Gain Adjustment<7:0> 0xF9 Q DAC Control Register

0x10 16 Q DAC Sleep Q DAC Power-Down

Q DAC Gain Adjustment<9:8>

0x01

0x11 17 Auxiliary DAC2 Data<7:0> 0x00

0x12 18 Auxiliary DAC2 Sign

Auxiliary DAC2 Current Direction

Auxiliary DAC2

Power-Down

Auxiliary DAC2 Data<9:8>

0x00

Aux DAC2 Control Register

0x13 to 0x18

19 to 24 Reserved

0x19 25 Sync Delay IRQ Sync Delay

IRQ Enable

Internal Sync

Loopback

0x00 Interrupt Register

0x1A to 0x1F

26 to 31 Reserved

AD9776/AD9778/AD9779

Rev. A | of 56

Table 12. SPI Register Description Address Register Name Reg. No. Bits Description Function Default Comm Register 00 7 SDIO bidirectional 0: use SDIO pin as input data only 0 1: use SDIO as both input and output data 00 6 LSB/MSB first 0: first bit of serial data is MSB of data byte 0 1: first bit of serial data is LSB of data byte 00 5 Software reset Bit must be written with a 1, then 0 to soft

reset SPI register map 0

00 4 Power-down mode 0: all circuitry is active 1: disable all digital and analog circuitry,

only SPI port is active

00 3 Auto power-down enable Controls auto power-down mode, see the Power-Down and Sleep Modes section

0

00 1 PLL lock (read only) 0: PLL is not locked 1: PLL is locked 0 Digital Control Register 01 7:6 Filter interpolation factor 00: 1× interpolation 00 01: 2× interpolation 10: 4× interpolation 11: 8× interpolation 01 5:2 Filter modulation mode See Table 21 for filter modes 0000 01 0 Zero stuffing 0: zero stuffing off 0 1: zero stuffing on 02 7 Data format 0: signed binary 0 1: unsigned binary 02 6 Dual/interleaved data bus mode 0: both input data ports receive data 0 1: Data Port 1 only receives data 02 5 Real mode 0: enable Q path for signal processing 0 1: disable Q path data (internal Q channel

clocks disabled, I and Q modulators disabled)

02 4 DATACLK delay enable See the Using Data Delay to Meet Timing Requirements section.

02 3 Inverse sinc enable 0: inverse sinc filter disabled 0 1: inverse sinc filter enabled 02 2 DATACLK invert 0: output DATACLK same phase as internal

capture clock 0

1: output DATACLK opposite phase as internal capture clock

02 1 TxEnable invert Inverts the function of TxEnable Pin 39, see the Interleaved Data Mode section

0

02 0 Q first 0: first byte of data is always I data at beginning of transmit

1: first byte of data is always Q data at beginning of transmit

Sync Control Register 03 7:6 Data clock delay mode 00: manual 00 03 5:4 Extra data clock divide ratio Data clock output divider (see Table 22 for

divider ratio) 00

03 3:0 Reserved 000 04 7:4 Data clock delay Sets delay of REFCLK in to DATACLK out 0000 04 3:1 Output sync pulse divide Sets frequency of SYNC_O pulses 000 04 0 Sync out delay Sync output delay, Bit 4 05 7:4 Sync out delay Sync output delay, Bits<3:0> 0 05 3:1 Input sync pulse frequency Input sync pulse frequency divider, see the

AN-822 application note 000

05 0 Sync input delay Sync input delay, Bit 4 0

http://www.analog.com/UploadedFiles/Application_Notes/53160361088434AN_822.pdf

AD9776/AD9778/AD9779

Rev. A | of 56

Address Register Name Reg. No. Bits Description Function Default Sync Control Register 06 7:4 Sync input delay See the Multiple DAC Synchronization

section for details on using these registers to synchronize multiple DACs

0

06 3:0 Input sync pulse timing error tolerance

0

07 7 Sync receiver enable 0 07 6 Sync driver enable 0 07 5 Sync triggering edge 0 07 4:0 SYNC_I to input data sampling

clock offset 0

PLL Control 08 7:2 PLL band select VCO frequency range vs. PLL band select value (see Table 18)

111001

08 1:0 VCO AGC gain control Lower number (low gain) is generally better for performance

11

09 7 PLL enable 0: PLL off, DAC rate clock supplied by outside source

0

1: PLL on, DAC rate clock synthesized internally from external reference clock via PLL clock multiplier

09 6:5 PLL VCO divide ratio FVCO/fDAC 00 × 1 01 × 2 10 × 4 11 × 8 09 4:3 PLL loop divide ratio fDAC/fREF 00 × 2 01 × 4 10 × 8 11 × 16 09 2:0 PLL bias setting Always set to 010 010

0A 7:5 PLL control voltage range 000 to 111, proportional to voltage at PLL loop filter output, readback only

Misc Control

0A 4:0 PLL loop bandwidth adjustment See PLL Loop Filter Bandwidth section for details

I DAC Control Register 0B 7:0 I DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word for I DAC

11111001

0C 7 I DAC sleep 0: I DAC on 0 1: I DAC off 0C 6 I DAC power-down 0: I DAC on 0 1: I DAC off 0C 1:0 I DAC gain adjustment (9:8) MSB slice of 10-bit gain setting word

for I DAC 01

0D 7:0 Aux DAC1 gain adjustment (7:0) LSB slice of 10-bit gain setting word for Aux DAC1

00000000

0E 7 Aux DAC1 sign 0: positive 1: negative 0E 6 Aux DAC1 current direction 0: source 0 1: sink 0E 5 Aux DAC1 power-down 0: Aux DAC1 on 0 1: Aux DAC1 off


0E 1:0 Aux DAC1 gain adjustment (9:8) MSB slice of 10-bit gain setting word for Aux DAC1

00

AD9776/AD9778/AD9779

Rev. A | of 56

Address Register Name Reg. No. Bits Description Function Default Q DAC Control Register 0F 7:0 Q DAC gain adjustment (7:0) LSB slice of 10-bit gain setting word for

Q DAC 11111001

10 7 Q DAC sleep 0: Q DAC on 0 1: Q DAC off 10 6 Q DAC power-down 0: Q DAC on 0 1: Q DAC off 10 1:0 Q DAC gain adjustment (9:8) MSB slice of 10-bit gain setting word

for Q DAC

11 7:0 Aux DAC2 gain adjustment (7:0) LSB slice of 10-bit gain setting word for Aux DAC2

00000000

12 7 Aux DAC2 sign 0: positive 1: negative 12 6 Aux DAC2 current direction 0: source 0 1: sink 12 5 Aux DAC2 power-down 0: Aux DAC2 on 0 1: Aux DAC2 off


12 1:0 Aux DAC2 gain adjustment (9:8) MSB slice of 10-bit gain setting word for Aux DAC2

00

Interrupt Register 19 7 0 19 6 Sync delay IRQ Readback, must write 0 to clear 0 19 5 0 19 3 0 19 2 Sync delay IRQ enable 0 19 1 0 19 0 Internal sync loopback 0

AD9776/AD9778/AD9779

Rev. A | of 56

INTERPOLATION FILTER ARCHITECTURE The AD9776/AD9778/AD9779 can provide up to 8× interpola-tion, or the interpolation filters can be entirely disabled. It is important to note that the input signal should be backed off by approximately 0.01 dB from full scale to avoid overflowing the interpolation filters. The coefficients of the low-pass filters and the inverse sinc filter are given in Table 13, Table 14, Table 15, and Table 16. Spectral plots for the filter responses are shown in Figure 57, Figure 58, and Figure 59.

Table 13. Half-Band Filter 1 Lower Coefficient Upper Coefficient Integer Value H(1) H(55) −4 H(2) H(54) 0 H(3) H(53) +13 H(4) H(52) 0 H(5) H(51) −34 H(6) H(50) 0 H(7) H(49) +72 H(8) H(48) 0 H(9) H(47) −138 H(10) H(46) 0 H(11) H(45) +245 H(12) H(44) 0 H(13) H(43) −408 H(14) H(42) 0 H(15) H(41) +650 H(16) H(40) 0 H(17) H(39) −1003 H(18) H(38) 0 H(19) H(37) +1521 H(20) H(36) 0 H(21) H(35) −2315 H(22) H(34) 0 H(23) H(33) +3671 H(24) H(32) 0 H(25) H(31) −6642 H(26) H(30) 0 H(27) H(29) +20,755 H(28) +32,768

Table 14. Half-Band Filter 2 Lower Coefficient Upper Coefficient Integer Value H(1) H(23) −2 H(2) H(22) 0 H(3) H(21) +17 H(4) H(20) 0 H(5) H(19) −75 H(6) H(18) 0 H(7) H(17) +238 H(8) H(16) 0 H(9) H(15) −660 H(10) H(14) 0 H(11) H(13) +2530 H(12) +4096

Table 15. Half-Band Filter 3 Lower Coefficient Upper Coefficient Integer Value H(1) H(15) −39 H(2) H(14) 0 H(3) H(13) +273 H(4) H(12) 0 H(5) H(11) −1102 H(6) H(10) 0 H(7) H(9) +4964 H(8) +8192

Table 16. Inverse Sinc Filter Lower Coefficient Upper Coefficient Integer Value H(1) H(9) +2 H(2) H(8) −4 H(3) H(7) +10 H(4) H(6) −35 H(5) +401

10

–100–4 4

fOUT (× Input Data Rate)

ATT

ENU

ATI

ON

(dB

)

–3 –2 –1 0 1 2 3

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

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Figure 57. 2× Interpolation, Low-Pass Response to ±4× Input Data Rate

(Dotted Lines Indicate 1 dB Roll-Off)

10

–100–4 4


ATT

ENU

ATI

ON

(dB

)

–3 –2 –1 0 1 2 3

0

–10

–20

–30

–40

–50

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–70

–80

–90

0536

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AD9776/AD9778/AD9779

Rev. A | of 56

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–100–4 4


ATT

ENU

ATI

ON

(dB

)

–3 –2 –1 0 1 2 3

0

–10

–20

–30

–40

–50

–60

–70

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–90

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With the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the Nyquist region of the DAC output sample rate. When the input signal is complex, this architecture allows modulation of the input signal to positive or negative Nyquist regions (see Table 17).

The Nyquist regions of up to 4× the input data rate can be seen in Figure 60.

–4×

–8

–3×

–6

–2×

–4

–1×

–2

DC

1

1×

3

2×

5

3×

7–7 –5 –3 –1 2 4 6 8

4× 0536

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Figure 60. Nyquist Zones

Figure 57, Figure 58, and Figure 59 show the low-pass response of the digital filters with no modulation. By turning on the modulation feature, the response of the digital filters can be tuned to anywhere within the DAC bandwidth. As an example, Figure 61 to Figure 67 show the nonshifted mode filter responses (refer to Table 17 for shifted/nonshifted mode filter responses).

10

–100–4 4–3 –2 –1 0 1 2 3

0

–10

–20

–30

–40

–50

–60

–70

–80

–90


ATT

ENU

ATI

ON

(dB

)

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Figure 61. Interpolation/Modulation Combination of 4 fDAC/8 Filter

10

–100–4 4–3 –2 –1 0 1 2 3

0

–10

–20

–30

–40

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–60

–70

–80

–90


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ON

(dB

)

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Figure 62. Interpolation/Modulation Combination of −3 fDAC/8 Filter

10

–100–4 4–3 –2 –1 0 1 2 3

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AD9776/AD9778/AD9779

Rev. A | of 56

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–100–4 4–3 –2 –1 0 1 2 3

0

–10

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–30

–40

–50

–60

–70

–80

–90


ATT

ENU

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ON

(dB

)

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Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter

10

–100–4 4–3 –2 –1 0 1 2 3

0

–10

–20

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–60

–70

–80

–90


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ENU

ATI

ON

(dB

)

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Figure 66. Interpolation/Modulation Combination of

2 fDAC/8 Filter in Shifted Mode

10

–100–4 4–3 –2 –1 0 1 2 3

0

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1-06

4

Figure 67. Interpolation/Modulation Combination of

3 fDAC/8 Filter in Shifted Mode

Shifted mode filter responses allow the pass band to be centered around ±0.5 fDATA, ±1.5 fDATA, ±2.5 fDATA, and ±3.5 fDATA. Switching to the shifted mode response does not modulate the signal. Instead, the pass band is simply shifted. For example, picture the response shown in Figure 67 and assume the signal in-band is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If the even mode filter response is then selected, the pass band becomes centered at 3.5 fDATA. However, the signal remains at the same place in the spectrum. The shifted mode capability allows the filter pass band to be placed anywhere in the DAC Nyquist bandwidth.

The AD9776/AD9778/AD9779 are dual DACs with internal complex modulators built into the interpolating filter response. In dual channel mode, the devices expect the real and the imaginary components of a complex signal at Digital Input Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC outputs then represent the real and imaginary components of the input signal, modulated by the complex carrier fDAC/2, fDAC/4, or fDAC/8.

With Register 2, Bit 6 set, the device accepts interleaved data on Port 1 in the I, Q, I, Q . . . sequence. Note that in interleaved mode, the channel data rate at the beginning of the I and the Q data paths are now half the input data rate because of the inter-leaving. The maximum input data rate is still subject to the maximum specification of the device. This limits the synthesis bandwidth available at the input in interleaved mode.

With Register 0x02, Bit 5 (real mode) set, the Q channel and the internal I and Q digital modulation are turned off. The output spectrum at the I DAC then represents the signal at Digital Input Port 1, interpolated by 1×, 2×, 4×, or 8×.

The general recommendation is that if the desired signal is within ±0.4 × fDATA, the odd filter mode should be used. Outside of this, the even filter mode should be used. In any situation, the total bandwidth of the signal should be less than 0.8 × fDATA.

AD9776/AD9778/AD9779

Rev. A | of 56

Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>)

Interpolation Factor <7:6>

Filter Mode <5:2> Modulation

Nyquist Zone Pass Band F_Low1 Center1 F_High1 Comments

8 0x00 DC 1 −0.05 0 +0.05 8 0x01 DC shifted 2 0.0125 0.0625 0.1125 8 0x02 F/8 3 0.075 0.125 0.175 8 0x03 F/8 shifted 4 0.1375 0.1875 0.2375 8 0x04 F/4 5 0.2 0.25 0.3 8 0x05 F/4 shifted 6 0.2625 0.3125 0.3625 8 0x06 3F/8 7 0.325 0.375 0.425 8 0x07 3F/8 shifted 8 0.3875 0.4375 0.4875 8 0x08 F/2 −8 −0.55 −0.5 −0.45 8 0x09 F/2 shifted −7 −0.4875 −0.4375 −0.3875 8 0x0A −3F/8 −6 −0.425 −0.375 −0.343 8 0x0B −3F/8 shifted −5 −0.3625 −0.3125 −0.2625 8 0x0C −F/4 −4 −0.3 −0.25 −0.2 8 0x0D −F/4 shifted −3 −0.2375 −0.1875 −0.1375 8 0x0E −F/8 −2 −0.175 −0.125 −0.075 8 0x0F −F/8 shifted −1 −0.1125 −0.0625 −0.0125

In 8× interpolation; BW (min) = 0.0375 × fDAC BW (max) = 0.1 × fDAC

4 0x00 DC 1 −0.1 0 +0.1 4 0x01 DC shifted 2 0.025 0.125 0.225 4 0x02 F/4 3 0.15 0.25 0.35 4 0x03 F/4 shifted 4 0.275 0.375 0.475 4 0x04 F/2 −4 −0.6 −0.5 −0.4 4 0x05 F/2 shifted −3 −0.475 −0.375 −0.275 4 0x06 −F/4 −2 −0.35 −0.25 −0.15 4 0x07 −F/4 shifted −1 −0.225 −0.125 −0.025


2 0x00 DC 1 −0.2 0 +0.2 2 0x01 DC shifted 2 0.05 0.25 0.45 2 0x02 F/2 −2 −0.7 −0.5 −0.3 2 0x03 F/2 shifted −1 −0.45 −0.25 −0.05


1 Frequency normalized to fDAC.

AD9776/AD9778/AD9779

Rev. A | of 56

INTERPOLATION FILTER MINIMUM AND MAXIMUM BANDWIDTH SPECIFICATIONS The AD977x uses a novel interpolation filter architecture that allows DAC IF frequencies to be generated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note that there are no possible filter modes in which the carrier can be placed near 0.5 × fDATA, 1.5 × fDATA, 2.5 × fDATA, and so on.

10

–80–4 4

fOUT (× Input Data Rate),ASSUMING 8× INTERPOLATION

ATT

ENU

ATI

ON

(dB

)

0

–10

–20

–30

–40

–50

–60

–70

–3 –2 –1 0 1 2 3

+fD

AC

/2

+fD

AC

/4

+fD

AC

/8

BA

SEB

AN

D

–fD

AC

/8

–fD

AC

/4

–fD

AC

/2

0536

1-06

5

Figure 68. Traditional Bandwidth Options for TxDAC Output IF

The filter architecture not only allows the interpolation filter pass bands to be centered in the middle of the input Nyquist zones (as explained in this section), but also allows the possi-bility of a 3 × fDAC/8 modulation mode. With all of these filter combinations, a carrier of given bandwidth can be placed anywhere in the spectrum and fall into a possible pass band of the interpolation filters. The possible bandwidths accessible with the filter architecture are shown in Figure 69 and Figure 70. Note that the shifted and nonshifted filter modes are all accessible by programming the filter mode for the particular interpolation rate.

10

–80–4 4


ATT

ENU

ATI

ON

(dB

)

0

–10

–20

–30

–40

–50

–60

–70

–3 –2 –1 0 1 2 3

–fD

AC

/2

–3×

f DA

C/8

–fD

AC

/4

–fD

AC

/8

BA

SEB

AN

D

+fD

AC

/8

+fD

AC

/4

+3×

f DA

C/8

+fD

AC

/2

0536

1-06

6

Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture

10

–80–4 4


ATT

ENU

ATI

ON

(dB

)

0

–10

–20

–30

–40

–50

–60

–70

–3 –2 –1 0 1 2 3

SHIF

TED

–3×

f DA

C/8

SHIF

TED

–fD

AC

/4

SHIF

TED

–fD

AC

/8

SHIF

TED

–DC

SHIF

TED

–DC

SHIF

TED

–fD

AC

/8

SHIF

TED

–fD

AC

/4

SHIF

TED

–3×

f DA

C/8

0536

1-06

7

Figure 70. Shifted Bandwidths Accessible with the Filter Architecture

With this filter architecture, a signal placed anywhere in the spectrum is possible. However, the signal bandwidth is limited by the input sample rate of the DAC and the specific placement of the carrier in the spectrum. The bandwidth restriction resulting from the combination of filter response and input sample rate is often referred to as the synthesis bandwidth, since this is the largest bandwidth that the DAC can synthesize.

The maximum bandwidth condition exists if the carrier is placed directly in the center of one of the filter pass bands. In this case, the total 0.1 dB bandwidth of the interpolation filters is equal to 0.8 × fDATA. As Table 17 shows, the synthesis band-width as a fraction of DAC output sample rate drops by a factor of 2 for every doubling of interpolation rate. The minimum bandwidth condition exists, for example, if a carrier is placed at 0.25 × fDATA. In this situation, if the nonshifted filter response is enabled, the high end of the filter response cuts off at 0.4 × fDATA, thus limiting the high end of the signal bandwidth. If the shifted filter response is enabled instead, then the low end of the filter response cuts off at 0.1 × fDATA, thus limiting the low end of the signal bandwidth. The minimum bandwidth specification that applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The minimum bandwidth behavior is repeated over the spectrum for carriers placed at (±n ± 0.25) × fDATA, where n is any integer.

DRIVING THE REFCLK INPUT The REFCLK input requires a low jitter differential drive signal. It is a PMOS input differential pair powered from the 1.8 V supply, therefore, it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the 400 mV common-mode voltage. While these input levels are not directly LVDS-compatible, REFCLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 71.

AD9776/AD9778/AD9779

Rev. A | of 56

LVDS_P_IN CLK+

50Ω

50Ω

0.1μF

0.1μFLVDS_N_IN CLK–

VCM = 400mV

0536

1-06

8

Figure 71. LVDS REFCLK Drive Circuit

If a clean sine clock is available, it can be transformer-coupled to REFCLK, as shown in Figure 71. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS to LVDS translator, then ac-coupled, as described in this section. Alternatively, it can be transformer-coupled and clamped, as shown in Figure 72.

50Ω

50Ω

TTL OR CMOSCLK INPUT CLK+

CLK–

VCM = 400mV

BAV99ZXCTHIGH SPEEDDUAL DIODE

0.1μF05

361-

069

Figure 72. TTL or CMOS REFCLK Drive Circuit

A simple bias network for generating VCM is shown in Figure 73. It is important to use CVDD18 and CGND for the clock bias circuit. Any noise or other signal that is coupled onto the clock is multiplied by the DAC digital input signal and can degrade DAC performance.

0.1μF 1nF1nF

VCM = 400mV

CVDD18

CGND

1kΩ

287Ω

0536

1-07

0

Figure 73. REFCLK VCM Generator Circuit

INTERNAL PLL CLOCK MULTIPLIER/CLOCK DISTRIBUTION The internal clock structure on the devices allows the user to drive the differential clock inputs with a clock at 1× or an integer multiple of the input data rate or at the DAC output sample rate. An internal PLL provides input clock multiplication and provides all the internal clocks required for the interpolation filters and data synchronization.

The internal clock architecture is shown in Figure 74. The reference clock is the differential clock at Pin 5 and Pin 6. This clock input can be run differentially or singled-ended by driving Pin 5 with a clock signal and biasing Pin 6 to the midswing point of the signal at Pin 5. The clock architecture can be run in the following configurations:

PLL Enabled (Register 0x09, Bit 7 = 1)

The PLL enable switch shown in Figure 74 is connected to the junction of the N1 dividers (PLL VCO divide ratio) and N2 dividers (PLL loop divide ratio). Divider N3 determines the interpolation rate of the DAC, and the ratio N3/N2 determines the ratio of reference clock/input data rate. The VCO runs optimally over the range of 1.0 GHz to 2.0 GHz, so that N1 keeps the speed of the VCO within this range, although the DAC sample rate can be lower. The loop filter components are entirely internal and no external compensation is necessary.

PLL Disabled (Register 0x09, Bit 7 = 0)

The PLL enable switch shown in Figure 74 is connected to the reference clock input. The differential reference clock input is the same as the DAC output sample rate. N3 determines the interpolation rate.

ADC

PHASEDETECTION VCO

DACINTERPOLATION

RATE

INTERNALLOOP

FILTER

0x0A (4:0)LOOP FILTERBANDWIDTHREFERENCE CLOCK

(PINS 5 AND 6)

0x0A (7:5)PLL CONTROLVOLTAGE RANGE

0x08 (7:2)VCO RANGE

0x09 (7)PLL ENABLE

INTERNAL DAC SAMPLERATE CLOCK

DATACLK OUT (PIN 37)

0x01 (7:6)

0x09 (6:5)PLL VCO

DIVIDE RATIO

0x09 (4:3)PLL LOOP

DIVIDE RATIO

÷N3

÷N2 ÷N1

0536

1-07

1

Figure 74. Internal Clock Architecture

AD9776/AD9778/AD9779

Rev. A | of 56

Table 18. VCO Frequency Range vs. PLL Band Select Value Typical PLL Lock Ranges

VCO Frequency Range in MHz Typ at 25°C Typ over Temp

PLL Band Select

fLOW fHIGH fLOW fHIGH

111111 (63) Auto mode Auto mode 111110 (62) 2056 2170 2105 2138 111101 (61) 2002 2113 2048 2081 111100 (60) 1982 2093 2029 2061 111011 (59) 1964 2075 2010 2043 111010 58) 1947 2057 1992 2026 111001 (57) 1927 2037 1971 2006 111000 (56) 1907 2016 1951 1986 110111 (55) 1894 2003 1936 1972 110110 (54) 1872 1981 1913 1952 110101 (53) 1852 1960 1892 1931 110100 (52) 1841 1948 1881 1920 110011 (51) 1816 1923 1855 1895 110010 (50) 1796 1903 1835 1874 110001 (49) 1789 1895 1828 1867 110000 (48) 1764 1871 1803 1844 101111 (47) 1746 1853 1784 1826 101110 (46) 1738 1842 1776 1815 101101 (45) 1714 1820 1752 1794 101100 (44) 1700 1804 1737 1779 101011 (43) 1689 1790 1726 1764 101010 (42) 1657 1757 1695 1734 101001 (41) 1641 1738 1679 1714 101000 (40) 1610 1707 1649 1684 100111 (39) 1597 1689 1635 1666 100110 (38) 1568 1661 1607 1639 100101 (37) 1553 1641 1592 1617 100100 (36) 1525 1613 1562 1592 100011 (35) 1511 1595 1548 1572 100010 (34) 1484 1570 1519 1549 100001 (33) 1470 1552 1506 1528 100000 (32) 1441 1525 1474 1504 011111 (31) 1429 1509 1463 1487 011110 (30) 1403 1485 1433 1464 011101 (29) 1390 1469 1422 1447 011100 (28) 1362 1443 1391 1423 011011 (27) 1352 1429 1380 1407 011010 (26) 1325 1405 1352 1385 011001 (25) 1314 1390 1340 1369 011000 (24) 1290 1368 1315 1350 010111 (23) 1276 1351 1302 1332 010110 (22) 1253 1331 1277 1313 010101 (21) 1239 1313 1264 1295 010100 (20) 1183 1255 1205 1240 010011 (19) 1204 1275 1227 1259 010010 (18) 1151 1221 1172 1207 010001 (17) 1171 1240 1193 1224 010000 (16) 1148 1218 1170 1204 001111 (15) 1137 1204 1159 1189

Typical PLL Lock Ranges VCO Frequency Range in MHz

Typ at 25°C Typ over Temp PLL Band Select

fLOW fHIGH fLOW fHIGH

001110 (14) 1116 1184 1137 1170 001101 (13) 1106 1171 1127 1157 001100 (12) 1086 1152 1106 1138 001011 (11) 1075 1138 1095 1124 001010 (10) 1055 1119 1075 1106 001001 (9) 1045 1107 1065 1093 001000 (8) 1027 1090 1047 1076 000111 (7) 1016 1076 1034 1062 000110 (6) 998 1059 1016 1046 000101 (5) 987 1046 1005 1032 000100 (4) 960 1017 977 1004 000011 (3) 933 989 949 976 000010 (2) 908 962 923 950 000001 (1) 883 936 898 925 000000 (0) 859 911 873 899

VCO Frequency Ranges

Because the PLL band covers greater than a 2× frequency range, there can be two options for the PLL band select: one at the low end of the range and one at the high end of the range. Under these conditions, the VCO phase noise is optimal when the user selects the band select value corresponding to the high end of the frequency range. Figure 75 shows how the VCO bandwidth and the optimal VCO frequency varies with the band select value.

VCO Frequency Ranges over Temperature

The specifications given over temperature in Table 18 are for a single part in a single lot. Part-to-part, and lot-to-lot, these specifications can exhibit a mean shift of several register settings. Systems should be designed to take this potential shift into account to maintain optimal PLL performance.

PLL Loop Filter Bandwidth

The loop filter bandwidth of the PLL is programmed via SPI Register 0x0A, Bits<4:0>. Changing these values switches capacitors on the internal loop filter. No external loop filter components are required. This loop filter has a pole at 0 (P1), and then a zero (Z1) pole (P2) combination. Z1 and P2 occur within a decade of each other. The location of the zero pole is determined by Bits<4:0>. For a setting of 00000, the zero pole occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2 combination can be lowered to approximately 1 MHz. The relationship between Bits<4:0> and the position of the zero pole between 1 MHz and 10 MHz is linear. The internal components are not low tolerance, however, and can drift by as much as ±30%.

For optimal performance, the bandwidth adjustment (Register 0x0A, Bits<4:0>) should be set to 11111 for all operating modes with PLL enabled. The PLL bias settings

AD9776/AD9778/AD9779

Rev. A | of 56

(Register 0x09, Bits<2:0>) should be set to 111. The PLL control voltage (Register 0x0A, Bits<7:5>) is read back and is propor-tional to the dc voltage at the internal loop filter output. With the PLL bias settings given in this section, the readback from the PLL control voltage should typically be 010, or possibly 001 or 011. Anything outside of this range indicates that the PLL is not operating correctly.

048

12162024283236404448525660

850

2150

2050

1950

1850

1750

1650

1450

1550

1350

1250

1150

105095

0

FVCO (MHz)

PLL

BA

ND

0536

1-07

2

Figure 75. Typical PLL Band Select vs. Frequency at 25°C

048

12162024283236404448525660

850

2150

2050

1950

1850

1750

1650

1450

1550

1350

1250

1150

105095

0

FVCO (MHz)

PLL

BA

ND

0536

1-11

3

Figure 76. Typical PLL Band Select vs. Frequency over Temperature

The AD977x has an autosearch feature that determines the optimal settings for the PLL. To enable the autosearch mode, set Register 0x08, Bits<7:2> to 11111b, and read back the value from Register 0x08, Bits<7:2>. Autosearch mode is intended to find the optimal PLL settings only, after which the same settings should be applied in manual mode. It is not recommended that the PLL be set to autosearch mode during regular operation.

FULL-SCALE CURRENT GENERATION Internal Reference

Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to I120 (Pin 75). A simplified block diagram of the reference circuitry is shown in Figure 77. The recommended value for the

external resistor is 10 kΩ, which sets up an IREFERENCE in the resistor of 120 μA, which in turn provides a DAC output full-scale current of 20 mA. Because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. Internal current mirrors provide a current-gain scaling, where I DAC or Q DAC gain is a 10-bit word in the SPI port register (Register 0x0A, Register 0x0B, Register 0x0E, and Register 0x0F). The default value for the DAC gain registers gives an IFS of approximately 20 mA, where IFS is equal to

321024

61227V2.1

×⎟⎠⎞

⎜⎝⎛

⎟⎠⎞

⎜⎝⎛ ×+× gainDAC

R

I DAC

DAC FULL-SCALEREFERENCECURRENT

CURRENTSCALING

I DAC GAIN

Q DAC GAINQ DAC

AD9779

VREF

10kΩ

1.2V BAND GAP

0.1μF I120

0536

1-07

3

Figure 77. Reference Circuitry

35

00 1000

DAC GAIN CODE

I FS

(mA

)

30

25

20

15

10

5

200 400 600 800

0536

1-07

4

Figure 78. IFS vs. DAC Gain Code

Application of Auxiliary DACs in Single Sideband Transmitter

Two auxiliary DACs are provided on the AD977x. The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor. The gain scale from the ref-erence amplifier current IREFERENCE to the auxiliary DAC reference current is 16.67 with the auxiliary DAC gain set to full scale (10-bit values, SPI Register 0x0D and SPI Register 0x11), this gives a full-scale current of approximately 2 mA for auxiliary DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not differential. Only one side of the auxiliary DAC (P or N) is active at one time. The inactive side goes into a high impedance state (>100 kΩ). In addition, the P or N outputs can act as current sources or sinks. The control of the P and N side for both auxiliary DACs is via Register 0x0E and Register 0x10, Bits<7:6>. When sourcing current, the output compliance

AD9776/AD9778/AD9779

Rev. A | of 56

voltage is 0 V to 1.6 V. When sinking current, the output compliance voltage is 0.8 V to 1.6 V.

The auxiliary DACs can be used for local oscillator (LO) cancella-tion when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and can degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 79 and Figure 80. Often, the input common-mode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling or a dc level shift is necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, then the dc blocking capacitors in Figure 79 can be removed. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. Placing the filter at the location shown in Figure 79 and Figure 80 allows easy design of the filter, as the source and load impedances can easily be designed close to 50 Ω.

0536

1-11

5

AD9779Q DAC

AD9779AUX

DAC2

25Ω TO 50Ω

0.1μF

0.1μF

OPTIONALPASSIVE

FILTERING

QUADRATUREMODULATOR V+

QUAD MODQ INPUTS

AD9779I DAC

AD9779AUX

DAC1

25Ω TO 50Ω

0.1μF

0.1μF

OPTIONALPASSIVE

FILTERING


QUAD MODI INPUTS

Figure 79. Typical Use of Auxiliary DACs AC Coupling to

Quadrature Modulator

0536

1-11

6

AD9779I OR Q DAC

AD9779AUX

DAC1 OR 2

25Ω TO 50Ω 25Ω TO 50Ω

OPTIONALPASSIVE

FILTERING


QUAD MODI OR Q INPUTS

Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature

Modulator with DC Shift

POWER DISSIPATION Figure 81 to Figure 89 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC and dual DAC modes. In addition to this, the power dissipation/current

of the 3.3 V supply (mode and speed independent) in single DAC mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. Furthermore, when the PLL is enabled, it adds 90 mW/50 mA to the 1.8 V clock supply regardless of the mode of the AD9779.

00 250

fDATA (MSPS)

POW

ER (W

)

0.6

0.7

0.5

0.4

0.3

0.2

0.1

25 50 75 100 125 150 175 200 225

8× INTERPOLATION,ZERO STUFFING

8× INTERPOLATION

4× INTERPOLATION


2× INTERPOLATION

1× INTERPOLATION



0536

1-07

6

Figure 81. Total Power Dissipation, I Data Only, Real Mode

00 250

fDATA (MSPS)

POW

ER (W

)0.4

25 50 75 100 125 150 175 200 225

8× INTERPOLATION 4× INTERPOLATION

2× INTERPOLATION

1× INTERPOLATION

0.3

0.2

0.1

0536

1-07

8

Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,

Does Not Include Zero Stuffing

00 250

fDATA (MSPS)

POW

ER (W

)

0.08

25 50 75 100 125 150 175 200 225

8× INTERPOLATION4× INTERPOLATION

2× INTERPOLATION

1× INTERPOLATION

0.06

0.04

0.02

0536

1-07

9

Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,

Includes Modulation Modes, Does Not Include Zero Stuffing

AD9776/AD9778/AD9779

Rev. A | of 56

00 250

fDATA (MSPS)

POW

ER (W

)

0.075

25 50 75 100 125 150 175 200 225

0.050

0.025

ALL INTERPOLATION MODES

0536

1-08

0

Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation

Modes and Zero Stuffing

00 300250 275

fDATA (MSPS)

POW

ER (W

) 0.6

1.0

0.7

0.8

0.9

0.5

0.4

0.3

0.2

0.1

25 50 75 100 125 150 175 200 225

0536

1-07

7

1× INTERPOLATION


2× INTERPOLATION,ALL MODULATION MODES


4× INTERPOLATION,ALL MODULATIONMODES


8× INTERPOLATION, ALLMODULATION MODES8× INTERPOLATION,

ZERO STUFFING

Figure 85. Total Power Dissipation, Dual DAC Mode

00 250

fDATA (MSPS)

POW

ER (W

)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

25 50 75 100 125 150 175 200 225

2× INTERPOLATION

4× INTERPOLATION

1× INTERPOLATION,NO MODULATION

8× INTERPOLATION, fDAC/8,fDAC/4,fDAC/2,

NO MODULATION

0536

1-08

1

Figure 86. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC

Mode, Does Not Include Zero Stuffing

00 250

fDATA (MSPS)

POW

ER (W

)

0.125

25 50 75 100 125 150 175 200 225

2× INTERPOLATION

4× INTERPOLATION

1× INTERPOLATION,NO MODULATION

8× INTERPOLATION, fDAC/8,fDAC/4,fDAC/2,

NO MODULATION0.100

0.075

0.050

0.025

0536

1-08

2

Figure 87. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC

Mode, Does Not Include Zero Stuffing

00 250

fDATA (MSPS)

POW

ER (W

)

0.075

25 50 75 100 125 150 175 200 225

0.050

0.025

ALL INTERPOLATION MODES

0536

1-08

3

Figure 88. Digital 3.3 V Supply, I and Q Data, Dual DAC Mode

0.16

00 1200

fDAC (MSPS)

POW

ER (W

)

0.14

0.12

0.10

0.08

0.06

0.04

0.02

200 400 600 800 1000

0536

1-08

4

Figure 89. Power Dissipation of Inverse Sinc Filter

AD9776/AD9778/AD9779

Rev. A | of 56

POWER-DOWN AND SLEEP MODES INTERLEAVED DATA MODE

The AD977x has a variety of power-down modes, so that the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the SPI port, the main TxDACs can be placed in sleep or power-down mode. In sleep mode, the TxDAC output is turned off, thus reducing power dissipation. The reference remains powered on, however, so that recovery from sleep mode is very fast. With the power-down mode bit set (Register 0x00, Bit 4), all analog and digital circuitry, including the reference, is powered down. The SPI port remains active in this mode. This mode offers more substantial power savings than sleep mode, but the turn-on time is much longer. The auxiliary DACs also have the capability to be programmed into sleep mode via the SPI port. The auto power-down enable bit (Register 0x00, Bit 3) controls the power-down function for the digital section of the devices. The auto power-down function works in conjunction with the TXENABLE pin (Pin 39) according to the following:

The TxEnable bit is dual function. In dual port mode, it is simply used to power down the digital section of the devices. In interleaved mode, the IQ data stream is synchronized to TXENABLE. Therefore, to achieve IQ synchronization, TXENABLE should be held low until an I data word is present at the inputs to Data Port 1. If a DATACLK rising edge occurs while TXENABLE is at a high logic level, IQ data becomes synchronized to the DATACLK output. TXENABLE can remain high and the input IQ data remains synchronized. To be backwards-compatible with previous DACs from Analog Devices, Inc. such as the AD9777 and AD9786, the user can also toggle TXENABLE once during each data input cycle, thus continually updating the synchronization. If TXENABLE is brought low and held low for multiple REFCLK cycles, then the devices flush the data in the interpolation filters, and shut down the digital engine after the filters are flushed. The amount of REFCLK cycles it takes to go into this power-down mode is then a function of the length of the equivalent 2×, 4×, or 8× interpolation filter. The timing of TXENABLE, I/Q select, filter flush, and digital power-down are shown in Figure 91.

TXENABLE (Pin 39) =

0: autopower-down enable = 0: flush data path with 0s 1: flush data for multiple REFCLK cycles; then automatically place the digital engine in power-down state. DACs, reference, and SPI port are not affected.

INTERLEAVEDINPUT DATA

TxENABLE CAN REMAINHIGH OR TOGGLE FORI/Q SYNCHRONIZATION

I1 Q1 I2 Q2

TxENABLE

FLUSHINGINTERPOLATION

FILTERS

POWERDOWN DIGITAL

SECTION 0536

1-08

5

or TXENABLE (Pin 39) =

1: normal operation

As shown in Figure 90, the power dissipation saved by using the power down mode is nearly proportional to the duty cycle of the signal at the TXENABLE pin.

Figure 91. TXENABLE Function

The TXENABLE function can be inverted by changing the status of Register 0x02, Bit 1. The other bit that controls IQ ordering is the Q-first bit (Register 0x02, Bit 0). With the Q-first bit reset to the default of 0, the IQ pairing that is latched is the I1Q1, I2Q2, and so on. With IQ first set to 1, the first I data is discarded and the pairing is I2Q1, I3Q2, and so on. Note that with IQ-first set, the I data is still routed to the internal I channel, the Q data is routed to the internal Q channel, and only the pairing changes.

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

00 10080604020

DUTY CYCLE (%)

POW

ER S

AVI

NG

S

0536

1-11

9

2× INT fDATA = 50MSPS


2× INT fDATA = 200MSPS4× INT fDATA = 50MSPS4× INT fDATA = 200MSPS


TIMING INFORMATION Figure 92 to Figure 95 show some of the various timing possibilities when the PLL is enabled. The combination of the settings of N2 and N3 from Figure 74 means that the reference clock frequency can be a multiple of the actual input data rate. Figure 92 to Figure 95 show, respectively, what the timing looks like when N2/N3 = 1 and 2.

Figure 90. Power Savings Based on Duty Cycle of TxEnable

If the TxEnable invert bit (Register 0x02, Bit 1) is set, the function of this TXENABLE pin is inverted. In interleaved mode, set-up and hold times of DATACLK out to

data in are the same as those shown in Figure 92 to Figure 95. It is recommended that any toggling of TXENABLE occur concurrently with the digital data input updating. In this way, timing margins between DATACLK, TXENABLE, and digital input data are optimized.



AD9776/AD9778/AD9779

Rev. A | of 56

0536

1-12

0

REFERENCECLOCK IN

DATACLOCK OUT

INPUTDATA

tSREFCLK tHREFCLKtSDATACLK tHDATACLK

Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1×

REFERENCECLOCK IN

DATACLOCK OUT

SYNC_IN

tS_SYNC

tH_SYNC

0536

1-12

1

INPUTDATA

tSREFCLK

tHREFCLK

tSDATACLK tHDATACLK


0536

1-12

2

REFERENCECLOCK IN

DATACLOCK OUT

INPUTDATA


tS_SYNC

tH_SYNC

SYNC_IN


REFERENCECLOCK IN

DATACLOCK OUT

0536

1-12

3

INPUTDATA


SYNC_IN

tS_SYNC

tH_SYNC


AD9776/AD9778/AD9779

Rev. A | of 56

Specifications are given in Table 19 for the drift of input data set up and hold time vs. temperature, as well as the data keep out window (KOW). Note that although these specifications do drift, the length of the keep out window, where input data is invalid, changes very little over temperature.

Table 19. AD9779 Timing Specifications vs. Temperature

Timing Parameter Temperature

Min tS (ns)

Min tH (ns)

Max KOW (ns)

REFCLK to DATA −40°C −0.8 +2.2 +1.3 +25°C −1.1 +2.5 +1.4 +85°C −1.3 +2.9 +1.5 DATACLK to DATA −40°C +1.8 −0.4 +1.3 +25°C +2.1 −0.7 +1.4 +85°C +2.5 −0.9 +1.5 SYNC_I to REFCLK

−40°C to +85°C −0.2 +1.0 +0.8

SYNCHRONIZATION OF INPUT DATA TO DATACLK OUTPUT (PIN 37)

Synchronizing the input data bus to the DATACLK out signal is achieved by meeting the timing relationships between DATACLK and DATA timing specified in Table 19. If the user is synchro-nizing the input data to the DATACLK out, the sync input (SYNC_I) signal does not need to be applied and can be ignored (connect to GND).

SYNCHRONIZATION OF INPUT DATA TO THE REFCLK INPUT (PIN 5 AND PIN 6) WITH PLL ENABLED OR DISABLED Synchronizing the input data bus to the REFCLK input requires the use of the SYNC_I input pins (Pin 13 and Pin 14). If the SYNC_I input is not used, there is a phase ambiguity between the DATACLK out and the REFCLK in. This ambiguity matches the interpolation rate in which the AD9779, for example, is currently operating. Because input data is latched on the rising edge of DATACLK, it is impossible for the user to determine onto which one of the multiple internal DACCLK edges (as an example, one of four edges in 4× interpolation) the input data actually latches. For the user to specifically determine the exact edge of REFCLK on which the data is being latched, a rising edge must be periodically applied to SYNC_I. The frequency of the SYNC_I signal must be equal to fDAC/2N, N being an integer,

and must be no greater than DATACLK for proper synchronization. There is no limit on how slow the SYNC_I signal can be driven. As long as the set up and hold timing relationship between SYNC_I and REFCLK given in Table 19 is met, the input data is latched on the immediate next rising edge of REFCLK. Note that a rising edge of DATACLK out occurs concurrently with the next REFCLK rising edge, after a short propagation delay. Although this propagation delay is not specified, input data setup and hold timing information is given with respect to REFCLK in and DATACLK out in Figure 92 to Figure 95. Also, note that in 1× interpolation, because there is no phase ambiguity, there is no need to use the SYNC_I signal.

Valid Timing Window In addition to the timing requirements of SYNC_I with respect to REFCLK, it is important to understand that the valid timing window for SYNC_I is limited by the internal DAC sample rate. This is shown in Figure 96. When the tS and tH requirements are met, the valid timing window for SYNC_I extends only as far as one period of the internal DAC sample rate (minus tS and tH). Failure to meet this timing specification can potentially result in erroneous data being latched into the AD9779 digital inputs.

As an example, if the AD9779 input data rate is 122.88 MSPS and the REFCLK is the same, with the AD9779 in 4× interpola-tion, the DAC sample rate is 1/491.52 MHz or about 2 ns. With a tS of −0.2 ns and tH of 1.0 ns, this gives a valid timing window for SYNC_I of

2 ns − 0.8 ns = 1.2 ns

The timing window of the digital input data to REFCLK can be moved in increments of one internal REFCLK cycle by using the REFCLK OFFSET register (Register 0x7, Bits<4:0>).

Because SYNC_I can be run at the same frequency as REFCLK when the PLL is enabled, best practice suggests that in this con-dition, REFCLK and SYNC_I originate from the same source. This limits the variation in time between these two signals and makes the overall timing budget easier to achieve. A slight delay may be necessary on the REFCLK path in this configuration to add more timing margin between REFCLK and SYNC_I (see Table 19 for timing relationship).

0536

1-12

4

REFCLK

SYNC_I

tS tH

tDAC_SAMPLEtDAC_SAMPLE

Figure 96. Valid Timing Relationship for SYNC_I to REFCLK

AD9776/AD9778/AD9779

Rev. A | of 56

Using Data Delay to Meet Timing Requirements

To meet strict timing requirements at input data rates of up to 250 MSPS, the AD977x has a fine timing feature. Fine timing adjustments are made by programming values into the data clock delay register (Register 0x04, Bits<7:4>). This register can be used to add delay between the REFCLK in and the DATACLK out. Figure 97 shows the default delay present when DATACLK delay is disabled. The disable function bit is found in Register 0x02, Bit 4. Figure 98 shows the delay present when DATACLK delay is enabled and set to 0000. Figure 99 indicates the delay when DATACLK delay is enabled and set to 1111. Note that the setup and hold times specified for data to DATACLK are defined for DATACLK delay disabled.

CH1 1.00VΩ

TEK RUN: 5.00GS/s SAMPLE

CH2 500mVΩ M2.00ns CH1 420mV

Δ: 4.48nS@: 40.28nS

2

1

0536

1-08

9

Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled

CH1 1.00VΩ



Δ: 4.76nS@: 35.52nS

2

1

0536

1-09

0

Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000

CH1 1.00VΩ



Δ: 7.84nS@: 32.44nS

2

1

0536

1-09

1

Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111

The difference between the minimum delay shown in Figure 98 and the maximum delay shown in Figure 99 is the range programmable using the DATACLK delay register. The delay (in absolute time) when programming DATACLK delay between 0000 and 1111 is a linear extrapolation between these two figures. The typical delays per increment over temperature are shown in Table 20.

Table 20. Data Delay Line Typical Delays Over Temperature Delays −40°C +25°C +85°C Unit Delay Between Disabled and Enabled

370 416 432 ps

Average Delay per Increment 171 183 197 ps

The frequency of DATACLK out depends on several program-mable settings: interpolation, zero stuffing, and interleaved/ dual port mode, all of which have an effect on the REFCLK frequency. The divisor function between REFCLK and DATACLK is equal to the values shown in Table 21.

Table 21. REFCLK to DATACLK Divisor Ratio Interpolation Zero Stuffing Input Mode Divisor 1 Disabled Dual port 1 2 Disabled Dual port 2 4 Disabled Dual port 4 8 Disabled Dual port 8 1 Disabled Interleaved Invalid 2 Disabled Interleaved 1 4 Disabled Interleaved 2 8 Disabled Interleaved 4 1 Enabled Dual port 2 2 Enabled Dual port 4 4 Enabled Dual port 8 8 Enabled Dual port 16 1 Enabled Interleaved 1 2 Enabled Interleaved 2 4 Enabled Interleaved 4 8 Enabled Interleaved 8

AD9776/AD9778/AD9779

Rev. A | of 56

In addition to this divisor function, DATACLK can be divided by up to an additional factor of 4, according to the state of the DATACLK divide register (Register 0x03, Bits<5:4>). For more details, see Table 22).

Table 22. Extra DATACLK Divisor Ratio Register 0x03, Bits<5:4> Divider Ratio 00 1 01 2 10 4 11 1

The maximum divisor resulting from the combination of the values in Table 21, and the DATACLK divide register is 32.

Manual Input Timing Correction

Correction of input timing can be achieved manually. The correction function is controlled by Register 0x03, Bits<7:6>. The function is programmed as shown in Table 23.

Table 23. Input Timing Correction Mode Register 0x03, Bits<7:6> Function 00 Error check disabled 01 Reserved 10 Reserved 11 Reserved

Necessary corrections can be made by adjusting DATACLK delay and the DATACLK invert bit (Register 2, Bit 2). DATACLK delay can then be swept to find the range over which the timing is valid. The final value for data delay should be the value that corresponds to the middle of the valid timing range. If a valid timing range is not found during this sweep, the user should invert the DATACLK invert bit and repeat the process.

Multiple DAC Synchronization

The AD9779 has programmable features that allow the CMOS digital data bus inputs and internal filters on multiple devices to be synchronized. This means that the DATACLK output signal on one AD9779 can be used to register the output data for a data bus delivering data to multiple AD9779s. The details of this opera-tion are given in the Analog Devices Application Note AN-822.

http://www.analog.com/UploadedFiles/Application_Notes/53160361088434AN_822.pdf

AD9776/AD9778/AD9779

Rev. A | of 56

EVALUATION BOARD OPERATION The AD977x evaluation board is designed to optimize the DAC performance and the speed of the digital interface, yet remains user friendly. To operate the board, the user needs a power source, a clock source, and a digital data source. The user also needs a spectrum analyzer or an oscilloscope to look at the DAC output. The diagram in Figure 100 illustrates the test setup. A sine or square wave clock works well as a clock source. The dc offset on the clock is not a problem, since the clock is ac-coupled on the evaluation board before the REFCLK inputs. All necessary connections to the evaluation board are shown in more detail in Figure 101.

The evaluation board comes with software that allows the user to program the SPI port. Via the SPI port, the devices can be programmed into any of its various operating modes. When first operating the evaluation board, it is useful to start with a simple configuration, that is, a configuration in which the SPI port settings are as close as possible to the default settings. The default software window is shown in Figure 102. The arrows indicate which settings need to be changed for an easy first time evaluation. Note that this implies that the PLL is not being used and that the clock being used is at the speed of the DAC output sample rate. For a more detailed description of how to use the PLL, see the PLL Loop Filter Bandwidth section.

DIGITALPATTERN

GENERATOR

ADAPTERCABLES

CLOCKGENERATOR

AD9779EVALUATION

BOARD

CLKIN SPI PORT

DATACLK OUTCLOCK IN

SPECTRUMANALYZER

1.8V POWER SUPPLY

3.3V POWER SUPPLY

0536

1-09

7

Figure 100. Typical Test Setup

SPI PORT

AD9779

J1 CLOCK INP4 Digital Input Connector

S7 DCLKOUT

AUX33 DVDD18 DVDD33 CVDD18 AVDD33J2

5V Supply

ANALOG DEVICES

AD9779/8/6REV D

S5 OUTPUT 1

S6 OUTPUT 2

AD8349

LOCAL OSCINPUT

MODULATOROUTPUT

+5VGND

JP4JP15JP8JP14

JP3JP16JP2JP17

0536

1-09

8

Figure 101. AD977x Evaluation Board Showing All Connections

AD9776/AD9778/AD9779

Rev. A | of 56

1. SET INTERPOLATION RATE

2. SET INTERPOLATION FILTER MODE

3. SET INPUT DATA FORMAT

4. SET DATACLK POLARITY TO MATCH INPUT TIMING

0536

1-09

9

Figure 102. SPI Port Software Window

The default settings for the evaluation board allow the user to view the differential outputs through a transformer that converts the DAC output signal to a single-ended signal. On the evaluation board, these transformers are designated T1A, T2A, T3A, and T4A. There are also four common-mode transformers on the board that are designated T1B, T2B, T3B, and T4B. The recommended operating setup places the transformer and common-mode transformer in series. A pair of transformers

and common-mode transformers are installed on each DAC output, so that the pairs can be set up in either order. As an example, for the frequency range of dc to 30 MHz, it is recommended that the transformer be placed right after the DAC. Above DAC output frequencies of 30 MHz, it is recommended that the common-mode transformer is placed right after the DAC outputs, followed by the transformer.

AD9776/AD9778/AD9779

Rev. A | of 56

MODIFYING THE EVALUATION BOARD TO USE THE AD8349 ON-BOARD QUADRATURE MODULATOR The evaluation board contains an Analog Devices AD8349 quadrature modulator. The AD977x and AD8349 provide an easy-to-interface DAC/modulator combination that can be easily evaluated on the evaluation board. To route the DAC output signal to the quadrature modulator, the following jumper settings must be made:

Unsoldered: JP14, JP15, JP16, JP17 Soldered: JP2, JP3, JP4, JP8

The DAC output area of the evaluation board is shown in Figure 103. The jumpers that need to be changed to use the AD8349 are circled. Also circled are the 5 V and GND connections for the AD8349.

0536

1-10

0

Figure 103. Photo of Evaluation Board, DAC Output Area

http://www.analog.com/AD8349





AD9776/AD9778/AD9779

Rev. A | of 56

EVALUATION BOARD SCHEMATICS

C69

0.1μ

F+

CVD

D18

TP2

BLA

CK

TP17

RED

TP1

RED

L1EX

C-C

L453

2U1

L6

EXC

-CL4

532U

1

C68

0.1μ

FC

7722

μF 16V

CVD

D18

_IN

C66

0.1μ

F+

VDD

M

DG

ND

22

TP14

RED

TP15

BLA

CK

L12

EXC

-CL4

532U

1

L16

EXC

-CL4

532U

1

C67

0.1μ

FC

4622

μF 16V

VDD

M_I

N

DG

ND

2

TP13

RED

R51

9kΩ

R52

10kΩ

R55

10kΩ

C26

0.1μ

F+

AVD

D33

TP8

BLA

CK

TP19

RED

TP5

RED

L3EX

C-C

L453

2U1

L13

EXC

-CL4

532U

1

C28

0.1μ

FC

2022

μF 16V

AVD

D33

_IN

C49

0.1μ

F+

DPW

R33

TP10

BLA

CK

TP21

RED

TP7

RED

L5EX

C-C

L453

2U1

L15

EXC

-CL4

532U

1

C48

0.1μ

FC

2222

μF 16V

DPW

R33

_IN

+C

700.

1μF

DVD

D18

TP4

BLA

CK

TP18

RED

TP3

RED

L2EX

C-C

L453

2U1

L7

EXC

-CL4

532U

1

C71

0.1μ

FC

7622

μF 16V

DVD

D18

_IN

C42

0.1μ

F+

DVD

D33

TP9

BLA

CK

TP20

RED

TP6

RED

L4EX

C-C

L453

2U1

L14

EXC

-CL4

532U

1

C45

0.1μ

FC

2122

μF 16V

DVD

D33

_IN

3U

64

74A

C14

11U

610

74A

C14

9U

68

74A

C14

5U

66

74A

C14

2U

5

CSB

S1SW

SEC

MA

S3SW

SEC

MA

S2SW

SEC

MA

11

32

74A

C14

SPI_

CSB

SPI_

CLK

SPI_

SDI

SPI_

SDO

4U

53

74A

C14 6U

55

74A

C14 1U

62

74A

C14

12U

513

74A

C14

10U

511

74A

C14 8U

59

74A

C14

13U

612

74A

C14

P11 2 3 4 5 6

R53

9kΩ

R54

9kΩ

SDI

132

SCLK

132

S4SW

SEC

MA

TP16

RED

TJA

K06

RA

PC

LASS

= IO

FCI-6

8898

SDO

132

0536

1-10

1

Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface

AD9776/AD9778/AD9779

Rev. A | of 56

6

AU

X1_N

AU

X1_P

AU

X2_P

CLK

_NC

LK_P

DC

LK

I120

IOU

T1_N

IOU

T1_P

IOU

T1_N

IOU

T1_P

IOU

T2_P

IOU

T2_N

IOU

T2_P

IOU

T2_N

IPTA

T

IRQ

P1D

0P1

D1

P1D

10

P1D

11P1

D12

P1D

13P1

D14

P1D

15

P1D

2

P1D

3P1

D4

P1D

5P1

D6

TP12

RED

P1D

7P1

D8

P1D

9

P2D

0P2

D1

P2D

10P2

D11

P2D

12

P2D

13P2

D14

P2D

15

P2D

2P2

D3

P2D

4

P2D

5P2

D6

P2D

0P2

D1

P2D

2P2

D3

P2D

4

P2D

5P2

D6

P2D

7

JP7

JP18

U11

U1

9779

TQFP

+ C44.7µF

C291nF

VOLTDVDD33

DVDD18

P2D

8P2

D9

PAD

PLL_

LOC

K

RES

ET

SPI_

CLK

SPI_

CSB

SPI_

SDI

SPI_

SDO

SPI_

CLK

SPI_

CSB

SPI_

SDI

SPI_

SDO

SYN

C_1

NSY

NC

_1P

SYN

C_O

NSY

NC

_OP

VDD

18_4

3

VDD

A33

_76

VDD

A33

_78

VDD

A33

_80

VDD

C18

_1

VDD

C18

_10

VDD

C18

_2

VDD

C18

_9

VDD

D18

_23

VDD

D18

_33

VDD

D18

_53

VDD

D18

_60

VDD

D18

VDD

D33

_38

VDD

D33

_61

VREF

_74

VSSA

_77

VSSA

_79

VSSA

_81

VSSA

_82

VSSA

_85

VSSA

_88

VSSA

_91

VSSA

_94

VSSA

_95

VSSC

_11

VSSC

_3VS

SC_4

VSSC

_7VS

SC_8

VSSD

_15

VSSD

_22

VSSD

_32

VSSD

_44

VSSD

_54

VSSD

_64

VSS_

12

VSS_

72

TX

AU

X2_N

AU

X1_N

AU

X1_P

AU

X2_P

AU

X2_N

VDD

A33

_100

VSSA

_99

VDD

A33

_98

VSSA

_97

VDD

A33

_96

90 89 8687

65 37

759293 8384 73 71

3635242120191817 3431302928272625

59 58

474645424140

57 56 55 52 51504948

PAD

VCC

Y

NCA

GND 32

5

4

SN74LVC1G34

1

6570 6869 67 66

1413

6263

43

100

7678809698

1 102 9 23 33

5360

16 38

61747779818285889194959799

113 4 7 8 15 22 32 44

5464

12

72

39

DVDD18

DVDD33

P2D15

DPWR33

DPWR33

DPWR33

TP11

RED

+

C120.1µF

C301nF

C130.1µF

R5922Ω

R2622Ω

R2622Ω

C54.7µF

C581nF

VOLT

CVDD18

AVDD33

CLK_NCLK_P

+

C550.1µF

C570.1µF

C561nF

C311nF

S151

2

C140.1µF

C64.7µF

C400.1µF

VOLT +

C361nF

C351nF

C390.1µF

C271nF

C110.1µF

C34.7µF

C331nF

JP4D1ND1P

JP8

VOLT

+

C370.1µF

C241nF

C90.1µF

C14.7µF

+

C620.1µF

C341nF

VOLT

+

C380.1µF

C251nF

C100.1µF

C24.7µF

C591nF

C611nF

C600.1µF

C181nF

C810µF

6.3V

VOLT

VOLT+

C151nF

C74.7µF

C320.1µF

+

C784.7µF

S2

S7DATACLK

1

2

1

2

S161

2

U10

74LCX112 74LCX112

K CLR

PREJ

Q_

Q 5

2

15

431

65

3

1

42

R6310Ω

R70Ω

R1150Ω

R1050Ω

R80Ω

R3225Ω

R5822Ω

7

U10

K CLR

PREJ

Q_

Q 9

12

14

101113

C840.1µF

R5610Ω

R641kΩ

CR1VAL

JP13

JP3D2PD2N

JP2

JP16

JP17

R641kΩ

DPWR33

DGND;5

CR2VAL

34

12SW

1

4

6P

3

S

ADTL1-12

T4B

1

3

11

42

2

TC1-1T

T4A S6

6

4

6P

3

S

ADTL1-12

T3B

1

3

1

42

TC1-1T

T3A

6

1

3S

6

P

ADTL1-12

T1B

4

TC1-1T

T1A

1

3S

6

P

ADTL1-12

T2B

4

1

3

62

1

32

TC1-1T

T2A

4

6

412

S5

R60Ω

R1150Ω

R950Ω

R50Ω

JP14

JP15

0536

1-10

2

Figure 105. Evaluation Board, Rev. D, Circuitry Local to Devices

AD9776/AD9778/AD9779

Rev. A | of 56

G2

ENB

LVP

S1

G1A

G1B

LOIP

VPS2

G4A

G4B

QB

BP

VOU

TG

3

IBB

PIB

BN

QB

BN

LOINA

D83

49

9873 4 6

12131416 11 10

1 215

5

U9

VDDM

DGND2

VDDM

R141kΩ

JP1

J4C47

100pF

C720.1µF

C730.1µF

C4110µF10V

2 2

1

DGND2

2

DGND2

2

DGND22

DGND22

DGND2

DGND2

MODULATED OUTPUT

2

J5

JP9

2

1

DGND2

LOCAL OSC OUTPUTC74

100pF

C540.1µF

C7917.2pF

C6517.2pF

C75100pF

C510.1µF

+

JP13

R6040Ω

R2150Ω

R3150Ω

R25150Ω

R6140Ω

1

3P

52 S

ETC1-1-13

T4

4

64

P1

S

AD

TL1-

12

T3

3

JP10

R2420Ω

R62147.5Ω

C822.1pF

L1155nH

C4317.2pF

C4417.2pF

C832.1pF

L1055nH

R27300Ω

D2N

D2P

AUX2_P

AUX2_N

R2320Ω

C530.1µF

C5217.2pF

C5017.2pF

JP13

R2040Ω

R4150Ω

R12150Ω

R17150Ω

R2140Ω

6 4P

1

S AD

TL1-

12

T5

3

R1520Ω

R22147.5Ω

C812.1pF

L1155nH

C6317.2pF

C6417.2pF

C802.1pF

L1055nH

R19300Ω

D1N

D1P

AUX1_P

AUX1_N

R1620Ω

0536

1-10

3

Figure 106. Evaluation Board, Rev. D, AD8349 Quadrature Modulator

4

5S

32R13

VAL

R301kΩ

R31300Ω

R2825Ω

R2925Ω

P

ETC1-1-13

T2J1

CLKIN

C190.1μF C16

DNB

CVDD18

CLK_P

CLK_N

C170.1μF

C230.1μF

1

0536

1-10

4

Figure 107. Evaluation Board, Rev. D, DAC Clock Interface

AD9776/AD9778/AD9779

Rev. A | of 56

A1P4

PKG_TYPE = MOLEX110VAL

A2A3A4A5A6A7A8A9

A10A11

A15A16A17A18A19A20A21A22A23A24A25

C1P4


C2C3C4C5C6C7C8C9

C10C11

C15C16C17C18C19C20C21C22C23C24C25

CSBSD1P2D0P2D2P2D4P2D6P2D8P2D10P2D12P2D14

P1D0P1D2P1D4P1D6P1D8P1D10P1D12P1D14

DGNDBLK

E1P4


E2E3E4E5E6E7E8E9E10E11

E15E16E17E18E19E20E21E22E23E24E25

SCLKSD0P2D1P2D3P2D5P2D7P2D9P2D11P2D13P2D15

P1D1P1D3P1D5P1D7P1D9P1D11P1D13P1D15

B1P4


B2B3B4B5B6B7B8B9

B10B11

B15B16B17B18B19B20B21B22B23B24B25

D1P4


D2D3D4D5D6D7D8D9

D10D11

D15D16D17D18D19D20D21D22D23D24D25

DGND1BLK

0536

1-10

5

Figure 108. Evaluation Board, Rev. D, Digital Input Buffers

VALCNTERM_2P

1

2J2

5V

123

4

U2

ADP3339-1-8

CVDD18_IN

JP19C851μF

C861μF1

P2

2

123

4

U8

ADP3339-3-3

DPWR33_IN

JP23C971μF

C961μF

123

4

U7

ADP3339-3-3

AVDD33_IN

JP22C941μF

C931μF

123

4

U4

ADP3339-3-3

DVDD33_IN

JP21C911μF

C921μF

123

4

U3

ADP3339-1-8

DVDD18_IN

JP20C881μF

C891μF

0536

1-10

6

Figure 109. Evaluation Board, On-Board Voltage Regulators

AD9776/AD9778/AD9779

Rev. A | of 56

0536

1-10

7

Figure 110. Evaluation Board, Rev. D, Top Silk Screen

0536

1-10

8

Figure 111. Evaluation Board, Rev. D, Top Layer

AD9776/AD9778/AD9779

Rev. A | of 56

0536

1-10

9

Figure 112. Evaluation Board, Rev. D, Layer 2

0536

1-11

0

Figure 113. Evaluation Board, Rev. D, Layer 3

AD9776/AD9778/AD9779

Rev. A | of 56

0536

1-11

1

Figure 114. Evaluation Board, Rev. D, Bottom Layer

0536

1-11

2

Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen

AD9776/AD9778/AD9779

Rev. A | of 56

OUTLINE DIMENSIONS

NOTES1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

1

2526 50

7610075

51

14.00 BSC SQ16.00 BSC SQ

0.270.220.17

0.50 BSC

1.051.000.95

0.150.05

0.750.600.45

SEATINGPLANE

1.20MAX

1

252650

76 10075

51

6.50NOM7°

3.5°0°

COPLANARITY0.08

0.200.09

TOP VIEW(PINS DOWN)

BOTTOM VIEW(PINS UP)

CONDUCTIVEHEAT SINK

PIN 1

Figure 116. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-1) Dimensions shown in millimeters

ORDERING GUIDE Model Temperature Range Package Description Package Option AD9776BSVZ1 −40°C to +85°C 100-lead TQFP_EP SV-100-1

AD9776BSVZRL1 −40°C to +85°C 100-lead TQFP_EP SV-100-1

AD9778BSVZ1 −40°C to +85°C 100-lead TQFP_EP SV-100-1


AD9779BSVZ1 −40°C to +85°C 100-lead TQFP_EP SV-100-1


AD9776-EB Evaluation Board AD9778-EB Evaluation Board AD9779-EBZ1 Evaluation Board 1 Z = RoHS Compliant Part.

©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05361-0-3/07(A)

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