dsp/bios system integration workshop copyright © 2004 texas instruments. all rights reserved. t to...

DSP/BIOS System Integration Workshop

Copyright © 2004 Texas Instruments. All rights reserved. T TO

Technical Training Organization 1

1. Introduction2. Real-Time System Design Considerations3. Hardware Interrupts (HWI)4. Software Interrupts (SWI)5. Task Authoring (TSK)6. Data Streaming (SIO) 7. Multi-Threading (CLK, PRD)8. BIOS Instrumentation (LOG, STS, SYS, TRC)9. Static Systems (GCONF, TCONF)10. Cache (BCACHE)11. Dynamic Systems (MEM, BUF)12. Flash Programming (HexAIS, Flashburn)13. Inter-Thread Communication (MSGQ, ...) 14. DSP Algorithm Standard (XDAIS)15. Input Output Mini-Drivers (IOM) 16. Direct Memory Access (DMA)17. Review

Learning Objectives

Describe the concepts of foreground / background processing

List details of the Idle (IDL) thread

Compare Hardware Interrupts (HWI) to ISR’s

Demonstrate how to invoke Interrupt Preemption

Describe the purpose of the Interrupt Monitor

Create an HWI object using CCS Gconf tool

Add an idle thread to a given CCS project

Observe performance of threads using CCS

T TOTechnical Training

Organization 2

Hardware Interrupts

Concepts

Idle (IDL)

Hardware Interrupts (HWI)

Interrupt Preemption

Interrupt Monitor

Lab

Foreground (HWI)

Background (IDL)


Organization 3

Foreground / Background Scheduling

main()

{init

while(1)

nonRT}

IDL events run in sequence when no HWIs are posted HWI is ISR with automatic vector table generation Any HWI preempts IDL, HWI may preempt other HWI if desired If multiple HWI are present in IDL, control passes to highest priority HWI

ISRget buffer

process printf()

main(){

initreturn

}

BIO

S S

ch

ed

ule

r

HWIget bufferprocessLOG_printf()

IDLnonRT

+ instrumentation


Organization 4

Foreground / Background

HWI

Highest Priority

Lowest Priority

ProcessSample

ProcessSample

ProcessSample

Background

Background scheduler allows you to defer less urgent processes from hardware interrupt service routines to the background


Organization 5

Interrupt Enable Management Concepts Interrupt response is managed by a 2 level enable system:

Global Interrupt Enable (GIE) bit – indicates if any interrupts will be taken Interrupt Enable (IE) register – indicates which interrupts are of interest Pending interrupt signals are maintained in an Interrupt Flag (IF) register

until responded to, and are automatically cleared when serviced

On reset, GIE and all IE bits are cleared In main() whichever interrupts are desired initially should be enabled by

ORing 1s to their corresponding bit position(s) in the IE When main() exits, GIE is automatically enabled as part of the start of the

BIOS scheduler environment When an HWI is recognized: IF bit & GIE are cleared. GIE is cleared to avoid

preemption amongst HWI. On return from the HWI, GIE status is restored Using the dispatcher on an HWI allows re-enable of GIE within the HWI if

preemption is desired. Dispatcher also allows the selection of which other HWIs will be able to preempt the given HWI

101001

010111

1

IF IE

GIEInterruptSources

Event!

pGIE = GIEIFn = GIE = 0stack = PCPC = vectorb HWIcontext saveHWI runs { ... }context restore

GIE = pGIEPC = prior PC


Organization 6

ICR ISR

Hardware Interrupts

Concepts

Idle (IDL)



Interrupt Monitor

Lab

Foreground (HWI)

Background (IDL)


Organization 8

Idle IDL

Lowest priority - soft real-time - no deadline Idle functions executes sequentially Priority at which real-time analysis is passed to host

Likely IDL Activities Low power systems - idle the processor Systems in test - instrumentation User interfaces Defragmentation Garbage collection

Return from main( )Inactive Ready

Running

StartedResume

Preempted


Organization 9

Creating a New Idle Object Via GCONF 1/4

Creating a new Idl Obj1. right click on IDL mgr2. select “Insert IDL”


Organization 10

Creating a new Idl Obj1. right click on IDL mgr2. select “insert IDL”


Creating a new Idl Obj1. right click on IDL mgr2. select “Insert IDL”3. type object name


Organization 11



Organization

Creating a new Idl Obj1. right click on IDL mgr2. select “Insert IDL”3. type object name4. right click on new IDL5. select “Properties”

12

Creating a new Idl Obj1. right click on IDL mgr2. select “insert IDL”3. right click on new IDL4. select “rename”5. type new name6. right click on new IDL7. select “properties”


Creating a new Idl Obj1. right click on IDL mgr2. select “Insert IDL”3. type object name4. right click on new IDL5. select “Properties”6. indicate desired • User Comment (FYI)• Function to run in IDL• Whether to include this

function in the CPU load display


Organization 13

Hardware Interrupts

Concepts

Idle (IDL)



Interrupt Monitor

Lab

Foreground (HWI)

Background (IDL)


Organization 14

Hardware Interrupts Much like “ISR”s (interrupt service routines) Vector table automatically rendered Add interrupt keyword in front of function declaration Context switch (save/restore of state of CPU around the

HWI on the system stack) automatically performed when interrupt keyword is used

Are a priority foreground activity that preempt background activity

HWIs are taken in order of priority Default is one HWI does not preempt another: when a

running HWI returns, then execution will pass to the highest priority HWI then available (or back to IDL if no HWI are flagged)

Foreground

BackgroundT TO


HWI_c (p4)HWI_c (p4)

HWI_a (p6)HWI_a (p6)

IDLIDL

HWI_b (p5)HWI_b (p5)

HWI Scheduling ExampleHighest Priority

Lowest Priority

LegendRunningReady

Any HWI will preempt IDL Standard practice is that no HWIs preempt any other running HWI On return from an HWI, control is passed to highest pending HWI Is it always desirable to make high priority HWIs wait for lower priority

HWIs to conclude before they are serviced?

time

1

1

1

2

2

2

12

Context SaveContext Restore


Organization 16

Creating a New HWI Object Via GCONF 1/2

Creating a new HWI Obj

3. select “Properties”

1. expand the HWI mgr


Organization

2. right click on desired HWI

17

Creating a New HWI Object Via GCONF 2/2

4. select interrupt source

and function to run


Organization

Creating a new HWI Obj

1. expand the HWI mgr

2. right click on desired HWI

3. select “Properties”

18

Hardware Interrupts

Concepts

Idle (IDL)



Interrupt Monitor

Lab

Foreground (HWI)

Background (IDL)


Organization 19

Adding Preemption to HWIs When preemption amongst HWIs is desired, default

HWI scheduling can be manually overriden

Developer can use the dispatcher in CCS to make any desired HWI preemptible

Preemption can be on all higher numbered HWIs, or on any selected group of higher or lower HWI

Adding the dispatcher increases context save and restore effort, some extra system overhead incurred

Use of the dispatcher requires removing the interrupt keyword in the function declaration

While seemingly desirable, HWI preemption will be seen to be only one of several scheduling options - handy in some cases, unneeded in othersT TO


HWI_c (p4)HWI_c (p4)

HWI_a (p6)HWI_a (p6)

IDLIDL

HWI_b (p5)HWI_b (p5)

Preemptive HWI Scheduling Example

RunningReady

Legend

Any HWI will preempt IDL HWI priority 3 does not preempt HWI priority 2 HWI priority 1 preempts HWI priority 2 note: if the dispatcher had been differently configured, HWI_a

could have as easily preempted HWI_b, and HWI_c not so allowed

time

Highest Priority

Lowest Priority


Organization 21

Enabling Preemption via the Dispatcher

Right click on an HWI and select the “properties” option

Select the Dispatcher tab in the properties dialog box

Check the Use Dispatcher box

Select HWIs that will preempt this HWI via the Interrupt mask

Option: Arg field allows an argument to be passed to the HWI

Be sure to remove ‘interrupt’ keyword in front of ISR when using dispatcher ! !

To activate the dispatcher for a particular HWI:


Organization 22

Assembly Code Dispatch Option

myISR: HWI_enter ABMASK, CMASK, IEMASK, CCMASK...SWI_post(&mySwi);...HWI_exit ABMASK CMASK IERRESTOREMASK CCMASK

HWI_enter() and HWI_exit() are assembly macros Use _enter at the start of an HWI and _exit at the end of the HWI Allows BIOS calls to be correctly invoked between the functions User specifies preemption by other HWIs (IEMASK) GIE enabled on _enter and restored on _exit User specifies registers to save/restore (ABMASK, CMASK) User specifies cache control options (CCMASK) Cannot be used on HWIs that employ the BIOS dispatcher! Do not use interrupt keyword when using _enter and _exit ! Usually use BIOS dispatcher, for final optimization consider _enter, _exit

stack

A1

A2

...

CPU

A1

A2

...Interrupt preemption

enabled here


Organization 23

Comparison of Interrupt Options

Ease of use Easy Easy Demanding

Post to scheduler? Yes NO Yes

Chance of error Low Medium High

Speed Medium Fast Can be fastest

Code size Smaller Smaller Larger

BIOS Dispatcher Interrupt Keyword HWI_enter, HWI_exit

Recommended: Use the BIOS dispatcher as a first choice Allows for selectable nesting of interrupts and BIOS scheduler calls Easy to set up and manage via the config tool

Use HWI_enter and HWI_exit to optimize extremely speed critical HWI Can specify which registers to save, cache details, etc Still allows BIOS calls and preemption Requires knowing which registers to save for the given HWI

Interrupt keyword allows fast and small HWI – but no BIOS kernel API Any calls of BIOS API that prompt kernel scheduler action are prohibited Nesting of HWI requires manual management of GIE and IER

ONLY CHOOSE ONE OF THE ABOVE OPTIONS PER HWIT TO


HWI API Summary

HWI_enter Tell BIOS an HWI is running, GIE enabled HWI_exit Tell BIOS HWI about to exit HWI_enable Turns on GIE bit, enables ISRs to run HWI_disable Sets GIE to 0, returns prior GIE state HWI_restore Restor GIE to given state before HWI_disable

HWI API Description

HWI_dispatchPlug Write a fetch packet into the vector table – dynamic ISR creation

Mod7


Organization 25

Interrupt management intrinsics: Faster than the BIOS API

Unsigned int _disable_interrupts();

Unsigned int _enable_interrupts();

Void _restore_interrupts(unsigned int);

Hardware Interrupts

Concepts

Idle (IDL)



Interrupt Monitor

Lab

Foreground (HWI)

Background (IDL)


Organization 26

Hardware Interrupts

Concepts

Idle (IDL)



Interrupt Monitor

Lab

Foreground (HWI)

Background (IDL)


Organization 31

FIR Filter Overview

- -302928......10

Read new data from ADC

i-31A/D SP 31 Store to top of delay line


Organization 32

c0c1c2c3......

c30c31

xxxx

xx

++++

+=

FIR Filter Overview

- -302928......10


i-31A/D SP

y(31) = c0*x(31) + c1*x(30) + c2*x(29) + ... + c30*x(1) + c31*x(0)

Send results to DAC

Convolve with coefficients31

Store to top of delay line

D/Aout31 SP


Organization 33

c0c1c2c3......

c30c31

xxxx

xx

++++

+=

FIR Filter Overview

- -302928......10


in31A/D SP

D/Aout31 SP

y(31) = c0*x(31) + c1*x(30) + c2*x(29) + ... + c30*x(1) + c31*x(0)

Manage delay line

Send results to DAC

Convolve with coefficients31

Store to top of delay line- -313029......21

y(32) = c0*x(32) + c1*x(31) + c2*x(30) + ... + c30*x(2) + c31*x(1)

. . .

y(n) = c0*x(n) + c1*x(n-1) + c2*x(n-2) + ... + c30*x(n-30) + c31*x(n-31)


Organization 34

Audio Output

(48 KHz)

Lab 3: Hardware Interrupt - HWI

ADCAIC33

Audio Input

(48 KHz)

McBSPDRR

FIR.c

FIR Code

DACAIC33

McBSPDXR

isrAudio

hist[0]=MCBSP_DRR

if( sw0 == 1 )

dataOut=FIR(hist...)

for (i = N-1; i >= 0; i--)

hist[i+1] = hist[i];

else {dataOut=hist[0]}

MCBSP_DXR = dataOut

mcbsp.c

coeffs.c

Coefficients

BIOS\Labs\HW BIOS\Labs\Work BIOS\Labs\Algos

Create a new project, define build options Add the components noted below Set up a BIOS configuration, define the HWI Build the project, download and debug on the EVM Add an IDL object to monitor 2 EVM DIP switches


Organization 35

void isrAudio(void) {static short i; // loop indexstatic int dataIn, dataOut; // interface to MCBSP read/writestatic short dataOutL, dataOutR; // FIR results of L & R channels

dataIn = MCBSP1_DRR_32BIT; // Get one stereo sample (L & R Data)buf[0] = (short)dataIn; // Place Left data sample in delay linebuf[1] = (short)(dataIn >> 16); // Put Right data sample in delay line

for (i = FIRSZ-2; i >= 0; i--) // for 2*(#coeffs-1)buf[i+2] = buf[i]; // move all data down 1 pair

if( sw0 == 1 ) { // If filtering is on...fir(&buf[0], &coeffs[sw1][0], &dataOutL, FIRSZ, 1); // left channel FIRfir(&buf[1], &coeffs[sw1][0], &dataOutR, FIRSZ, 1); // right channel FIRdataOut = 0x0000FFFF & dataOutL; // get left value for outputdataOut |= 0xFFFF0000 & (dataOutR << 16); // or in right chan in MSBs

}else // if filtering is 'off'...

dataOut = dataIn; // new input copied to outputMCBSP1_DXR_32BIT = dataOut; // Send data to codec, (single channel)

}

FIR.c

in \Algos

mcbsp.c

in \HW

mcbsp.c

in \HW

audio.c : HWI Function Encapsulation

36

includedheaders

includedheaders

globalvariables

globalvariables

main()- init arrays- init HW- enable Int

main()- init arrays- init HW- enable Int

HWI- read A/D- if ‘on’, call FIR - else ‘out’ = ‘in’- write D/A

HWI- read A/D- if ‘on’, call FIR - else ‘out’ = ‘in’- write D/A

#include "myWorkcfg.h" // FIRST: config file header#include "codec.h" // serial port code access#include "coeffs.h" // fir filter coeff access#include "dipMonitor.h" // DIP init and reader access#include <evmdm6437.h> // allows access to EVM init fxn

#define FIRSZ 64

void isrAudio(void);void fir(short data[ ], short coeff[ ], short result[ ], int firsz, int bufsz);

short sw0 = 0; // controls run/bypass of FIRsshort sw1 = 0; // low pass vs high pass filtershort buf[2*FIRSZ]; // interlaced stereo data buffr

extern cregister volatile unsigned int CSR; // control status registerextern cregister volatile unsigned int ICR; // interrupt clear registerextern cregister volatile unsigned int IER; // interrupt enable reg.

// ========= MAIN - init and return to begin BIOS Scheduler environment...=====void main(void){

short i; // loop counter

EVMDM6437_init(); // init EVM6437 HWinitCodec(); // init McBSP1; s/u AIC via I2C initDipSwitches(); // init the DIP switch reader

for (i = 0; i < 2*FIRSZ; i++) // for size of stereo bufferbuf[i] = 0; // clear delay line

ICR = 0x10; // clear INT4 (precaution)IER |= 0x10; // enable INT4 as CPU interruptMCBSP1_SPCR = 0x00010001; // start McBSP

}// ===== isrAudio() - Serial Port Interrupt Service Routine: BIOS HWI ========void isrAudio(void){

static short i; // loop counterstatic int dataIn, dataOut; // i/f to MCBSP read/writestatic short dataOutL, dataOutR; // FIR results of L & R channels

dataIn = MCBSP1_DRR_32BIT; // get one stereo sample (L & R Data)

buf[0] = (short)dataIn; // put Left data sample in delay linebuf[1] = (short)(dataIn >> 16); // put Right data sample in delay line

for (i = FIRSZ-2; i >= 0; i--) // for 2*(#coeffs-1) buf[i+2] = buf[i]; // move all data down 1 pair

if( sw0 == 1 ){ // if SW0 is down...fir(&buf[0], &coeffs[sw1][0], &dataOutL, FIRSZ, 1); // FIR: 1 sample Lfir(&buf[1], &coeffs[sw1][0], &dataOutR, FIRSZ, 1); // FIR: 1 sample R

dataOut = 0x0000FFFF & dataOutL; // left result is 16 LSBsdataOut |= 0xFFFF0000 & (dataOutR << 16); // right result is 16 MSBs

}else // if filtering is 'off'...

dataOut = dataIn; // new input copied to output

MCBSP1_DXR_32BIT = dataOut; // output 1 stereo result to codec} 38

functionprototypes

functionprototypes

Working with TCF Files

Create a new TCF file based

on the DM6437 ‘seed’ file

Define an HWI on Int12 that

calls the isrAudio() function

Add an IDL object that calls

the readDipSwitches()

functionT TO


Lab Details

Filter Debug ReleaseOff 4.6% 1.4%On 68% 3.9%

These are the results I got running labs 3C and 3D.

Yours may not be exact, but they should be close.

Key points to make –

with the filter off, load is low since no math is being done

filter on – load is VERY high unoptimized

optimization is a BIG help to performance – and is easy

ti

Technical TrainingOrganization

47

C62/C64 APIThe C62 and C64 modules provide certain target-specific functions and definitions for the TMS320C6000 family of processors.

❏ C64_disableIER : disables interrupts by clearing the bits specified by mask in the IER. Returns bits cleared.

This value should be passed to C64_enableIER to re-enable masked interrupts

• oldmask = C64_disableIER(mask); // mask = C64_EINTxx where xx=int. #

❏ C64_enableIER. ASM macro to enable selected interrupts in IER

• C62_enableIER(oldmask);

❏ C64_plug. Plug interrupt vector

• C64_plug(vecid, fxn, dmachan);

HWI API ❏ HWI_dispatchPlug. Plug the HWI dispatcher

•HWI_dispatchPlug(vecid, fxn, dmachan, attrs);

❏ HWI_eventMap. Assign interrupt source number to an HWI object.

• HWI_eventMap(vectID, eventID);

❏ HWI_isHWI. Check current thread calling context.

typedef struct HWI_Attrs {

Uns intrMask; /* IER bitmask, 1="self" (default) */

Uns ccMask /* CSR CC bitmask, 1="leave alone" */

Arg arg; /* fxn arg (default = 0)*/

} HWI_Attrs;

DSP/BIOS supports the C64x+ interrupt selector through the HWI Module. You can route one of the 128 system events to a specific HWI object by specifying the event number as the "interrupt selection number“ in the HWI Object Properties. This one-to-one mapping supports up to 12 maskable interrupts. The C64x+ event combiner is supported by the ECM Module. If the 16 HWI objects are sufficient for the number of HWI functions your application needs to run, you need not enable the ECM module. You do not need to know whether your C function will be run by the HWI module or ECM module when you write the function. (The ECM module uses the HWI dispatcher, and so its functions cannot be completely written in assembly.)

ECM API ❏ ECM_disableEvent. Disable the specified event at run-time.

❏ ECM_dispatch. Handle events from the event combiner.

❏ ECM_dispatchPlug. Create an ECM dispatcher table entry.

•ECM_dispatchPlug(eventId, fxn, *attrs);

❏ ECM_enableEvent. Enable the specified event at run-time.

dsp/bios system integration workshop copyright © 2004 texas instruments. all rights reserved. t to...

Documents