dsp tms320
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3-1Central Processing Unit (CPU)
Central Processing Unit (CPU)
The TMS320C5x DSP central processing unit (CPU) can perform high-speed
arithmetic within a short instruction cycle by means of its highly parallel archi-
tecture, which consists of the following elements:
- Program controller
- Central arithmetic logic unit (CALU)
- Parallel logic unit (PLU)
- Auxiliary register arithmetic unit (ARAU)
- Memory-mapped registers
This chapter does not discuss the memory and peripheral segments, except
in relation to the CPU.
Topic Page
3.1 Functional Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Central Arithmetic Logic Unit (CALU) 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Parallel Logic Unit (PLU) 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Auxiliary Register Arithmetic Unit (ARAU) 3-17. . . . . . . . . . . . . . . . . . . . .
3.5 Summary of Registers 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
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Functional Overview
3-2
3.1 Functional Overview
The block diagram shown in Figure 3–1 outlines the principal blocks and datapaths within the ’C5x. The succeeding sections provide further details of the
functional blocks of the CPU.
The internal hardware of the ’C5x executes functions that other processors
typically implement in software or microcode. For example, the ’C5x contains
hardware for single-cycle 16
16-bit multiplication, data shifting, and ad-
dress manipulation. This hardware-intensive approach provides computing
power previously unavailable on a single chip.
Table 3–1 presents a summary of the ’C5x’s internal hardware. This summary
table is alphabetized. The table includes the internal processing elements,
registers, and buses. All of the symbols used in the table correspond to the the
functional blocks illustrated in Figure 3–1, the succeeding block diagrams in
this chapter, and the text throughout this document.
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Functional Overview
3-3Central Processing Unit (CPU)
Figure 3–1. Block Diagram of ’C5x DSP – Central Processing Unit (CPU)
P–SCALER(–6,0,1,4)
PRESCALERSFL(0–16)
TREG2(4)
32
DATA BUS
PROGRAM BUS
D15–D0
RBIT
A15–A0
DBMR
MUX
32
ACCB(32)
32
ACCLACCH
32
ALU(32)
3232
MUX
MUX
MUX
PREG(32)
MULTIPLIER
TREG0
MUX
MUX
B1
B2DARAM
B0DARAM
MUX
from IREG
7 LSB
MUX
9
MUX
SARAM
ARAU
MUX
3
33
PROGRAM BUS
CBSR2
CBSR1
CBCR(8)
AR7
AR6
AR4
AR3
AR2
AR1
ARCR
INDX
Serial Port 1TREG1(5)
BRCR
GREG
IFR
IMR
RPTC
PMST
ST1
ST0
BMAR
IREG
PFC
MCS
Instruction
Address
ROM
PASR
COMPARE
PAER
(8x16)
Stack
PC
MUX
NMI
WE
RD
CLKIN2
X2/CLKIN
CLKOUT1
X1
4INT(1–4)
MP/MC
RS
HOLDA
HOLD
XF
BR
READY
STRB
RW
PS
DS
IS
CLKMD3
CLKMD2
P R
O G R A M B
U S
D A T A B U S
CBER2
CBER1
AR5
BIO
M U X
M U X
Notes: All registers and data lines are 16-bits wide unless otherwise specified.†Not available on all devices.
Data/Program
Data/Program
PLU
Data
32
32
32
CLKMD1
AR0
PA0
PA15
I/O Ports
†
DATA BUS
.
.
.
PRESCALERSFR(0–16)
POSTSCALER(0–7)
IACK
IAQ
P r o g r a m C o n t r o l l e r
D R B
ST0 [ARP] ST0 [DP]
ST1 [C]
16IOWSR
CWSR(5)
PDWSR
Softwarewait–states
Serial Port 2
†Time-DivisionMultiplexedSerial Port
†Buffered
SerialPort
Timer
†Host PortInterface
Emulation
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Functional Overview
3-4
Table 3–1. ’C5x CPU Internal Hardware Summary
Symbol Name
A15–A0 Address bus
ACC(32) Accumulator
ACCB(32) Accumulator buffer
ACCH Accumulator high byte
ACCL Accumulator low byte
ALU(32) Arithmetic logic unit
AR0–AR7 Auxiliary registers
ARAU Auxiliary register arithmetic unit
ARB(3) Auxiliary register buffer bits
ARCR Auxiliary register compare register
ARP(3) Auxiliary register pointer bits
BMAR Block move address register
BRAF(1) Block repeat active flag bit
BRCR Block repeat counter register
C Carry bit
CALU Central arithmetic logic unit
CBCR(8) Circular buffer control register
CBER1, CBER2 Circular buffer end registers
CBSR1, CBSR2 Circular buffer start registers
CNF Configuration control bit
COMPARE Compare of program address
D15–D0 Data bus
DATA BUS Data bus
DBMR Dynamic bit manipulation register
dma(7) Data memory address (immediate register)
DP(9) Data memory page pointer bits
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Functional Overview
3-5Central Processing Unit (CPU)
Table 3–1. ’C5x CPU Internal Hardware Summary (Continued)
Symbol Name
DRB Direct data memory address bus
GREG Global memory allocation register
HM(1) Hold mode bit
IFR Interrupt flag register
IMR Interrupt mask register
INDX Index register
INTM(1) Interrupt mode bit
IPTR(5) Interrupt vector pointer bits
IREG Instruction register
MCS Microcall stack
MP/MC Microprocessor/microcomputer bit
MULTIPLIER Multiplier
MUX Multiplexer
NDX(1) Enable extra index register bit
OV(1) Overflow bit
OVLY(1) RAM overlay bit
OVM(1) Overflow mode bit
P-SCALER (–6, 0, 1, 4) Product shifter
PAER Block repeat program address end register
PASR Block repeat program address start register
PC Program counter
PFC Prefetch counter
PLU Parallel logic unit
PM(2) Product shifter mode bits
PMST Processor mode status register
POSTSCALER(0–7) Accumulator postscaling shifter
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Functional Overview
3-6
Table 3–1. ’C5x CPU Internal Hardware Summary (Continued)
Symbol Name
PREG(32) Product register
PRESCALER, SFL(0–16),
SFR(0–16)
Prescaling shifters
PROGRAM BUS Program bus
RAM(1) Program RAM enable bit
RPTC Repeat counter register
ST0, ST1 Status registers
STACK Stack
SXM(1) Sign-extension mode bit
TC(1) Test/control bit
TREG0 Temporary register (multiplicand)
TREG1(5) Temporary register (dynamic shift count)
TREG2(4) Temporary register (bit pointer in dynamic bit test)
TRM(1) Enable multiple temporary registers bit
XF(1) External flag pin status bit