dsm design and verification flow lecture 21 alessandra nardi

DSM Design and Verification Flow

Lecture 21

Alessandra Nardi

Outline

• Conventional design flow review

• Emerging problems

• Emerging design flow

• Design methodology challenges– Signal Integrity– Reliability– Manufacturability– Power

Conventional Design FlowFunct. Spec

Logic Synth.

Gate-level Net.

RTL

Layout

Floorplanning

Place & Route

Front-end

Back-end

Behav. Simul.

Gate-Lev. Sim.

Stat. Wire Model

Parasitic Extrac.

Verification at different levels of abstraction

BehavioralHDL

System Simulators

HDL Simulators

Code Coverage

Gate-level Simulators

Static Timing Analysis

Layout vs Schematic (LVS)

RTL

Gate-level

PhysicalDomain

Ver

ific

atio

n

Verification Techniques

• Simulation (functionalfunctional and timingtiming)– Behavioral– RTL– Gate-level (pre-layout and post-layout)– Switch-level– Transistor-level

• Formal Verification (functionalfunctional)• Static Timing Analysis (timingtiming)

Goal:Goal: Ensure the design meets its functional and timing requirements at each of these levels of abstraction

Classification of Simulators

Logic Simulators

Emulator-based Schematic-basedHDL-based

Event-driven Cycle-based Gate System

Conventional Design FlowFunct. Spec

Logic Synth.

Gate-level Net.

RTL

Layout

Floorplanning

Place & Route

Front-end

Back-end

Behav. Simul.

Gate-Lev. Sim.

Stat. Wire Model

Parasitic Extrac.

Emerging challenges Wire load model

• Synthesis flow involves the use of statistical wire-load models:– Wire load models available in the library are a statistical

average based on several previous designs– Wire length is a function of the fanout: far from accurate

given that fanout are largely design specific

• Long and painful to achieve timing convergence between pre-layout and post-layout

• The problem of timing convergence can be addressed by using wire-load models specific to the design (aka custom wire-load models)

• Custom wire-load model can be obtained by parasitic estimation:– Perform initial placement – Generate estimated loads– Use these to generate custom models

• Notice that parasitic estimation is not based on actual routing data (as in the case of parasitic extraction)

Emerging challenges Wire load model

• Need to achieve timing convergence with minimal number of iterations– Routing in general is an extremely computationally expensive

task– Delays are increasingly dominated by interconnects

• Transition to a timing-driven placement and route approach

• Router must adhere to signal integrity, electromigration, power and other such specifications

Emerging challengesFloorplan, Place&Route

• As design get larger, and process geometries smaller than 0.35mm, the impact of wire resistance, capacitance and inductance (aka parasitics) becomes significant– Need to model them

• Parasitic extraction follows layout– Large run time involved (trade-off for different

levels of accuracy)– Large sizes of files generated (Reduced Order

Modeling)

Emerging challengesParasitic Extraction

DSM design flow

More emerging issues

• Signal IntegritySignal Integrity (SI) : Ensure signals travel from source to destination without significant degradation– Crosstalk: noise due to interference with

neighboring signals– Reflections from impedence discontinuity– Substrate and supply grid noise

• ReliabilityReliability– Electromigration– Electrostatic Discharge (ESD)

• ManufacturabilityManufacturability– Parametric yield– Defect-related yield


• PowerPower– Power reduction at RTL level and at gate level

• Library-level: use of specially designed low-power cells

• Design technique

– It is critical that power issues be addressed early in the design process (as opposed to late in the design flow)

– Power tools:• Power estimation: (Design Power - Synopsys)

• Power optimization: take into consideration power just as synthesis uses timing and area (Power Compiler - Synopsys)


Overview Emerging Challenges

• Conventional design flow Emerging design flow– Higher level of abstraction– More accurate interconnect model– Interaction between front-end and back-end

• Signal Integrity• Reliability• Power• Manufacturability

Paradigm: Issues must be addressed early in the design flow – no more clear logical/physical dichotomy

New generation of design methodologies/tools needed

The Role of Interconnects in DSM Designs

Outline

• Interconnects parameters description

• Circuit models for interconnects

• Technology scaling and its impact on interconnects

Introduction

• Interconnect: conductive path

• Ideally: wire only connects functional elements (devices, gates, blocks, …) and does not affect design performance

• This assumption was approximately true for “large” design, it is unacceptable for DSM designs

Introduction

• Real wire has: – Resistance

– Capacitance

– Inductance

• Therefore wiring forms a complex geometry that introduces capacitive, resistive and inductive parasitics. Effects:– Impact on delay, energy consumption, power distribution

– Introduction of noise sources, which affects reliability

To evaluate the effect of interconnects on design performance we have to model them

Interconnects - Resistance

L

W

H

HW

L

A

LR

Material Resistivity [-m]

Silver (Ag) 1.6x10-8

Copper (Cu) 1.7x10-8

Gold (Au) 2.2x10-8

Aluminium (Al) 2.7x10-8

Tungsten (W) 5.5x10-8

Interconnects - Capacitance

• Parallel Plate CapacitanceL

W

H

DielectricSubstrate

tdi

WLt

Cppdi

di

Keep in mind:– C is proportional to the overlap between conductors– C is inversely proportional to their separation


• Fringing Capacitance

DielectricSubstrateCpp

Cfr

DielectricSubstrate

H

LHt

Cdi

difr )/log(

2


• Total Capacitance

DielectricSubstrate

+

H w

Keep in mind:– C is proportional to the overlap between conductors– C is inversely proportional to their separation

2

HWw

Fringing versus Parallel Plate

(from [Bakoglu89])

Taken from “Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic Copyright 2002 J. Rabaey et al.

Interwire Capacitance

fringing parallel


Interconnects - Inductance

• It can be evaluated with the aid of its definition: v=Ldi/dt– It is possible to calculate the inductancefrom its geometry

and its enviroment

• A simpler approach relies on the fact that the capacitance c and inductance l (per unit length) are related: cl=( and are the permittivity and permeability of the surrounding dielectric)

Caveat: conductor must be surrounded by a uniform dielectric

Simplifications• Inductive effects can be ignored if the resistance is

substantial (e.g. a long Al wire with small cross-section) or if the rise and fall times of the applied signals are slow

• When the wires are short, the cross-section is large or the material has low-resistivity, a capacitance-only model can be used

• When the separation between neighboring wires is large or when wires only run together for a short distance, inter-wire capacitance can be ignored, and all the parasitic capacitance can be modeled as capacitance to ground

Electrical Wire Model

• Ideal Wire:– Simplistic– Useful for early phase of the design– OK for small components, e.g. gates

• To study the effects of parasitics we need to model them

Electrical Wire ModelLumped vs Distributed

Lumped Distributed

R

C

r

c

r

c

r

c

r

c

Electrical Wire Model – Lumped C

• If resistive component is small and switching frequencies are in the low to medium range, it makes sense to consider only capacitive component– Wire still represents an equipotential region– Only impact on perfomance is the loading effect

• Popular model

C

Electrical Wire Model – Lumped RC

• If wire resistance is significant, a resistive-capacitive model is needed

• Lumped RC model is pessimistic and inaccurate for long interconnect wire– Distributed rc-model is complex and no closed form

solution exists– Elmore delay formula: lumped RC comes to help

R

C

Electrical Wire Model – Lumped RCElmore Delay

Consider an RC-tree:– The network has a single input node– All capacitors between node and ground– The network does not contain any resistive loop

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i


RC-tree property:– Unique resistive path between the source node s

and any other node i of the network path resistance Rii

Example: R44=R1+R3+R4

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i


RC-tree property:– Extended to shared path resistance Rik:

Example: Ri4=R1+R3

Ri2=R1

)])()([( s.t. kspathispathRRR jjik

R1

C1

s

R 2

C2

R 4

C4

C3

R3

Ci

Ri

1

2

3

4

i


• Assuming:– Each node is initially discharged to ground

– A step input is applied at time t=0 at node s

• The Elmore delay at node i is:

• It is an approximation: it is equivalent to first-order time constant of the network– Proven acceptable

– Powerful mechanism for a quick estimate

N

kikkDi RC

1


• Special case: RC-chain (or ladder)– Shared-path resistance path resistance

N

kkkkDN RC

1

R1

C1

R2

C2

RN

CN

Vin VN


Time-constant of resistive-capacitive wire

22

1

2

)1( 22

11

rcL

N

NrcL

NNRCCkRRC

N

N

k

N

kkkkDN

R

C

R

C

R

C

Vin VN

R=r · L/N

C=c·L/N

– Delay of wire is quadratic function of its length– Delay of distributed rc-line is half of lumped RC

Electrical Wire ModelThe Distributed RC-line


Interconnects – Why do we care?• Technology scaling: miniaturization of devices (scale

L, W, TOX, VTH)• Device Scaling Faster, smaller devices

L[m]=0.35, 0.25, 0.18, 0.12, etc S0.7

• Interconnect Scaling Larger delays!– Local interconnects: Almost constant– Global interconnects:RC delay goes as 1/S or 1/S3

• Also, parasitics give rise to a whole set of signal integrity issues

Design paradigm shift from device-centric to interconnect-centric

Interconnects – Why do we care?

ITRS 2001

Modern Interconnect


Example: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric


New Interconnect Materials

• Aluminium Copper– Lower resistivity– Higher immunity to Electromigration

• SiO2 Low-k dielectrics

Overview

• DSM challenges– Emerging design flow– Interconnect-centric design paradigm– Signal Integrity– Manufacturability, Reliability– Power Estimation

• Interconnects– Description of parasitics– Wire models– Why do we care– New materials

dsm design and verification flow lecture 21 alessandra nardi

Documents

dsm design flow slide

postlayout slide

basedgatesystem slide

placeroute slide

wire model parasitic

wireload models specific

levels of abstraction

wire load models available