dsd 2007 concurrent error detection for fsms designed for implementation with embedded memory blocks...
TRANSCRIPT
DSD 2007
Concurrent Error Detection for FSMs Designed for Implementation
with Embedded Memory Blocks of FPGAs
Andrzej Krasniewski
Institute of TelecommunicationsWARSAW UNIVERSITY OF TECHNOLOGY
CED for FSMs Designed for Implementation with EMBs of FPGAs - 2DSD’07 A.Krasniewski
Why CED for FSMs implemented with SRAM-based FPGAs? configuration memory - susceptible to transient faults embedded memory (major component of FSMs) -
more susceptible to transient faults than logic architectural features of FPGAs with embedded
memory make CED relatively inexpensive
Earlier proposed techniques, intended for FSMs implemented with gates and FFs (standard cells) - unsuitable
GOALDevelop a low-cost CED scheme for FSMs implemented using embedded memory of FPGAs
Motivation
CED for FSMs Designed for Implementation with EMBs of FPGAs - 3DSD’07 A.Krasniewski
Implementation of FSMs using FPGAs with embedded memory
Concurrent error detection
- architecture
- effectiveness of fault detection
- overhead
Conclusion
OUTLINE
CED for FSMs Designed for Implementation with EMBs of FPGAs - 4DSD’07 A.Krasniewski
Implementation of FSMs using FPGAs with embedded memory
Concurrent error detection
- architecture
- effectiveness of fault detection
- overhead
Conclusion
OUTLINE
CED for FSMs Designed for Implementation with EMBs of FPGAs - 5DSD’07 A.Krasniewski
IOEs IOEs IOEs IOEsIOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
DSPblock
LABs
M4K RAM block
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
M-RAM block
M512 RAM blockAlteraStratix
Embedded memory in FPGAs - Example
CED for FSMs Designed for Implementation with EMBs of FPGAs - 6DSD’07 A.Krasniewski
read/write memory modules• RAM• FIFO• shift registers
read-only memory modules (ROMs)• implementation of combinational logic• implementation of sequential logic (FSMs)
Embedded memory in FPGAs - Applications
CED for FSMs Designed for Implementation with EMBs of FPGAs - 7DSD’07 A.Krasniewski
ROM
m+p
ADDRESS REGISTER
p
n
m
address
output
input
SIMPLE STRUCTUREentire combinational logic located in memory (ROM)
ROM-based FSM design
next state
w
w < m+p
ADDRESS MODIFIER(gates)
ADDRESS REGISTER
p
n
m
address
output
input
EXTENDED STRUCTURE
next state
ROM
limited applicability – requires large memory
CED for FSMs Designed for Implementation with EMBs of FPGAs - 8DSD’07 A.Krasniewski
Embedded Memory
LUTs in PLBs (Xilinx CLBs, Altera LEs)
ADDRESS REGISTER
address
output
input
next state
ROM
FSM design for FPGA with embedded mem.
CED scheme in [DFT’04]
ADDRESS MODIFIER
flip-flops in PLBs(internal register of Emb Mem)
CED for FSMs Designed for Implementation with EMBs of FPGAs - 9DSD’07 A.Krasniewski
Embedded Memory
ADDRESS REGISTER
address
output
input
next state
ROM
flip-flops in PLBs(internal register of Emb Mem)
FSM design for FPGA with embedded mem.
Embedded Memory
studies in synthesis of FPGA-based circuits
new CED scheme
ADDRESS MODIFIER
CED for FSMs Designed for Implementation with EMBs of FPGAs - 10DSD’07 A.Krasniewski
ADDRESS REGISTER
embeddedmemory
input X
next state Q
memory H
FSM design for FPGA with embedded mem.
memory GADDRESS MODIFIER
clockA1 A2
„ROM”
Qa, Qb
Xa, Xb
embeddedmemory
programmablelogic
components
Xb, Xc Qb, Qc
output Y
input X, next state Q
group a → Addr Reggroup b → Addr Reg & Mem Ggroup c → Mem G
CED for FSMs Designed for Implementation with EMBs of FPGAs - 11DSD’07 A.Krasniewski
Implementation of FSMs using FPGAs with embedded memory
Concurrent error detection
- architecture
- effectiveness of fault detection
- overhead
Conclusion
OUTLINE
CED for FSMs Designed for Implementation with EMBs of FPGAs - 12DSD’07 A.Krasniewski
GOAL: low-cost solution
Assumptions
ADDR REG
address
output
input
next state
memory H(„ROM”)
memory G(ADDR MOD) CED scheme:
can add to the width of the mem. word cannot add to the width of mem. address
state encoded with a minimal no. of bits earlier proposed CED techniques for sequential circuits(based on state encoding with EDC) - not applicable
• one extra bit of address → size of the required memory doubles
• address space of EMBs - quite limited (address 13 bits)
• width of the embedded memory word can be extended significantly with no impact on the performance (speed) of the circuit
CED for FSMs Designed for Implementation with EMBs of FPGAs - 13DSD’07 A.Krasniewski
INPUT
clockXapQab’
address A
ADDRESS REGISTER
ADDRESSPARITY
CHECKER
ERR4OUTPUT
ERR2
Xb Qa Qb A2
A1AUXILIARYCHECKER
next state
OUTPUTPARITY
CHECKER
ADDRESS MODIFIER
pXab’
Qb+ pQab+’ pAQc+Qa+ pYpQc+’ LY
pXQcpA2’A2
pXQcpA2’ pXc’ pQc’
pXab’ Xa Xb Xc pXc’
„ROM”ERR1
ERR3
Proposed CED scheme
CED for FSMs Designed for Implementation with EMBs of FPGAs - 14DSD’07 A.Krasniewski
Error detection mechanisms
ERR1parity checking for address to memory H
ERR2parity checking for data feeding memory G only
ERR3parity checking for output
ERR4checking for address legality (optional)
Checkers implemented with PLBs(outputs – in two-rail code)
CED for FSMs Designed for Implementation with EMBs of FPGAs - 15DSD’07 A.Krasniewski
INPUT
clockXapQab’
address A
ADDRESS REGISTER
ADDRESSPARITY
CHECKER
ERR4OUTPUT
ERR2
Xb Qa Qb A2
A1AUXILIARYCHECKER
next state
OUTPUTPARITY
CHECKER
ADDRESS MODIFIER
pXab’
Qb+ pQab+’ pAQc+Qa+ pYpQc+’ LY
pXQcpA2’A2
pXQcpA2’ pXc’ pQc’
pXab’ Xa Xb Xc pXc’
„ROM”ERR1
ERR3
parity checking for address to memory H
CED for FSMs Designed for Implementation with EMBs of FPGAs - 16DSD’07 A.Krasniewski
INPUT
clockXapQab’
address A
ADDRESS REGISTER
ADDRESSPARITY
CHECKER
ERR4OUTPUT
ERR2
Xb Qa Qb A2
A1AUXILIARYCHECKER
next state
OUTPUTPARITY
CHECKER
ADDRESS MODIFIER
pXab’
Qb+ pQab+’ pAQc+Qa+ pYpQc+’ LY
pXQcpA2’A2
pXQcpA2’ pXc’ pQc’
pXab’ Xa Xb Xc pXc’
„ROM”ERR1
ERR3
parity checking for data feeding memory G only
CED for FSMs Designed for Implementation with EMBs of FPGAs - 17DSD’07 A.Krasniewski
INPUT
clockXapQab’
address A
ADDRESS REGISTER
ADDRESSPARITY
CHECKER
ERR4OUTPUT
ERR2
Xb Qa Qb A2
A1AUXILIARYCHECKER
next state
OUTPUTPARITY
CHECKER
ADDRESS MODIFIER
pXab’
Qb+ pQab+’ pAQc+Qa+ pYpQc+’ LY
pXQcpA2’A2
pXQcpA2’ pXc’ pQc’
pXab’ Xa Xb Xc pXc’
„ROM”ERR1
ERR3
parity checking for output
CED for FSMs Designed for Implementation with EMBs of FPGAs - 18DSD’07 A.Krasniewski
INPUT
clockXapQab’
address A
ADDRESS REGISTER
ADDRESSPARITY
CHECKER
ERR4OUTPUT
ERR2
Xb Qa Qb A2
A1AUXILIARYCHECKER
next state
OUTPUTPARITY
CHECKER
ADDRESS MODIFIER
pXab’
Qb+ pQab+’ pAQc+Qa+ pYpQc+’ LY
pXQcpA2’A2
pXQcpA2’ pXc’ pQc’
pXab’ Xa Xb Xc pXc’
„ROM”ERR1
ERR3
checking for address legality
CED for FSMs Designed for Implementation with EMBs of FPGAs - 19DSD’07 A.Krasniewski
in fault-free operation some state-input combinations never occur (in address register)
input (x1x2) state code q2q1q0 state
00 01 10 11
0 0 0 s1 s1 - s4 s2
0 1 0 s2 - s4 s5 -
1 0 1 s3 s3 s3 s1 s2
0 0 1 s4 s2 s1 s4 -
1 1 1 s5 s3 s2 s4 s1
01011 - illegal address
11000 - illegal address
illegal state code
Legality of address
CED for FSMs Designed for Implementation with EMBs of FPGAs - 20DSD’07 A.Krasniewski
Implementation of FSMs using FPGAs with embedded memory
Concurrent error detection
- architecture
- effectiveness of fault detection
- overhead
Conclusion
OUTLINE
CED for FSMs Designed for Implementation with EMBs of FPGAs - 21DSD’07 A.Krasniewski
Target faultspermanent or transient faults (in particular, SEU-induced) associated with a single input or output of any component that result in an incorrect state or output of the circuit
THEOREMThe proposed CED scheme guarantees the detection of each target fault,provided that two different transient faults do not occur in two consecutive clock cycles. Faults are detected with no latency(no later than in the cycle in which an incorrect state is present in the address register).
Proof: by examining all possible fault classes
the feature not provided by a majority (if not all) of earlier CED techniques
Note: detection of faults in input X
Effectiveness of fault detection
Address legality checking – optional enhances detectability of multiple faults
CED for FSMs Designed for Implementation with EMBs of FPGAs - 22DSD’07 A.Krasniewski
Implementation of FSMs using FPGAs with embedded memory
Concurrent error detection
- architecture
- effectiveness of fault detection
- overhead
Conclusion
OUTLINE
CED for FSMs Designed for Implementation with EMBs of FPGAs - 23DSD’07 A.Krasniewski
EMBs of different size: 512 - 16K bits with configurable data width: 1, 2, 4, 8, or 16 bits
for 4K EMBs: Altera APEX II, StratixXilinx Virtex, Virtex-E, Spartan II
no extension of max EMB address space
Cost (overhead) – Experimental study
proprietary tool FSMdec [BoFL07]
‘original’ circuit
synthesis of FSMfor EMB-basedimplementation
circuit with CED
design of CED scheme
evaluationof overhead
CED for FSMs Designed for Implementation with EMBs of FPGAs - 24DSD’07 A.Krasniewski
2 parity bits associated with circuit input extension of mem G word by 2* bits extension of mem H word by 4*(5*) bits extension of address register by 6* bits address and auxiliary parity checkers output parity checker
circuitindependent
circuitdependent
EXTRA LOGIC
Cost (overhead)
* fewer in some cases
extra PLBs
extra EMBs
logic cell = 4-input LUT + FF
10 extra logic cells = 1 extra EMB of 1K
CED for FSMs Designed for Implementation with EMBs of FPGAs - 25DSD’07 A.Krasniewski
EMB configuration no. EMBs inputs/ outputs/ states
EMB size mem G mem H orig. with
CED
EMB overhead
[%]
extra logic cells
combined overhead
[%]
bbsse 7/7/16 2K 1K2 12816 2+1 3+2 66.7 10 83.3
4K 25616 25616 1+1 1+2 50.0 10 62.5
8K 51216 51216 1+1 1+2 50.0 10 56.3
16K 1K16 1K16 1+1 1+2 50.0 10 53.1
ex1 9/19/20 8K 4K2 51216 2+1 3+1 33.3 14 39.2
16K 2K8 1K16 1+1 1+1 0.0 14 4.4
mark1 5/16/15 1K 5122 6416 2+2 3+2 25.0 13 57.5
2K 2568 12816 1+2 1+2 0.0 13 21.7
4K 25616 25616 1+2 1+2 0.0 13 10.8
8K 51216 51216 1+2 1+2 0.0 13 5.4
planet 7/19/48 8K 4K2 51216 2+1 3+1 33.3 14 39.2
16K 1K16 1K16 1+1 1+1 0.0 14 4.4
styr 9/10/30 16K 8K2 1K16 2+2 3+2 25.0 11 26.7
average overhead = 27.2%
Cost (overhead) – Experimental results
CED for FSMs Designed for Implementation with EMBs of FPGAs - 26DSD’07 A.Krasniewski
proposed method
Jha et al. IEEE Trans. CAD,
1993
Zeng et al. ITC’99
circuit extra EMBs+cells (combined) [%]
extra literals [%] extra literals [%]
bbase 63.8 181.7 - ex1 21.8 271.4 208.6 mark1 23.9 366.3 137.5 opus 46.9 102.1 - planet 21.8 214.9 374.2 pma 20.7 97.8 107.8 styr 26.7 135.3 127.8
difficult to draw conclusions, but ...
intended for FSMs implemented with standard cells
Cost (overhead) estimation – comparison
CED for FSMs Designed for Implementation with EMBs of FPGAs - 27DSD’07 A.Krasniewski
Implementation of FSMs using FPGAs with embedded memory
Concurrent error detection
- architecture
- effectiveness of fault detection
- overhead
Conclusion
OUTLINE
CED for FSMs Designed for Implementation with EMBs of FPGAs - 28DSD’07 A.Krasniewski
detection of all permanent and transient faults associated with single in/out of components
no latency low-cost
average overhead < 30%
CED scheme for an FSM implemented using an FPGA with embedded memory
Conclusion
CED for FSMs Designed for Implementation with EMBs of FPGAs - 29DSD’07 A.Krasniewski