DPSK Modulation: In DPSK, during HIGH state of the modulating signal flead signal is allowed to pass and during LOW state of the modulating signal flag signal is allowed to pass. Figure below shows DPSK [10] modulator circuit. The Opamp is tied in the inverting amplifier mode. The closed loop voltage gain of the Opamp is given byRF + rDS (on) 3AV(CL) = RI + rDS (on) 1,2Where: rDS (on) 3 is the drain- source resistance of Q3 FETrDS (on) 1,2 is drain-resistance of the conducting FET(Q1 or Q2)The drain source resistance is of the order of 100 which is very small compared to RF and RI.HenceRFAV(CL) = - RIDPSK Modulator Circuit DPSK Demodulation:DPSK Demodulation [12,13 & 14]is done with PLL IC 565[3 4 5]. DPSK [10] signal is given as input at DPSK input terminal of PLL as shown in the figure below.A capacitor C is connected between pin7 and power supply forms first order low pass filter with an internal resistance 3.6KW, The capacitor C should be large enough to eliminate variations in the demodulated output voltage in order to stabilize the VCO frequency. The cut-off frequency of Low pass filter is made equal to carrier frequency. The cutoff frequency of low pass filter is given by1fH = -2pRCR = 3.6KW, fH = 18.7KHzThe value of C designed by1C = -2pRfH1C = = 2.3nF2px3.6Kx18.7KC selected is 3nFDPSK Modulator Circuit

DPSK and PSK modulated signals